Foxconn H61A01 Schematics
5
4
3
2
1
Cover Sheet
Block Diagram
D D
Clock Distribution
Power Delivery Map 4
Power On Sequence
Reset/power good
STRAP
CPU 1-6 8-13
DDR3-1:CHA
DDR3-2:CHB
PCIE X16 16
Clock Gen
PCH 1-8
VGA
C C
DVI
PCIE 1X 28
AUDIO_ALC888S/ALC662
AUDIO CONN/SPDIF/CD-IN
LAN_RTL8111E
LAN/USB2.0 CONN
Front USB2.0 Header
SIO-ITE8728F-CX
PS2/FAN
1
2
3
5
6
7
14
15
17
18-25
26
27
29
30
31
32
33
34
35
H61A01
Fab 1.1
Micro ATX 9.6X8.0
CPU:
Intel Sandy Bridge processors in LGA1155 Package
System Chipset:
PCH
Main Memory:
Dual Channel / DDR-III * 2 (Max 8GB)
On Board Device:
SIO:IT8728F/CX
LAN:RealTek RTL8111E-VB-GR
HDA Codec:ALC888S/ALC662
BIOS:SPI Flash ROM 4M
Expansion Slots:
PCI EXPRESS 16X SLOT *1
PCI EXPRESS 1X SLOT * 2
TPM/LPT/COM 36
ATX CONN/FP PANEL/RSMRST
FOX2/1D05/1D8V/VCCSA
37
38
5V_DUAL/3.3V_SB/3.3V_DUAL 39
B B
1D5V_STR
CPU_VCCIO
VCORE/AXG PWM
VCORE/AXG DRIVER
XDP
THROUGH HOLE
Changelist
40
41
42
43
44
45
46
Fab.A
SKUVersion Function BOM
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Cover Sheet
Cover Sheet
Cover Sheet
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
148Tuesday, April 24, 2012
148Tuesday, April 24, 2012
148Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
4
3
2
1
D D
BLOCK DIAGRAM
POWER
SUPPLY
CONNECTOR
PCIE (GEN 2)
VREG
VRD12
PCIE GEN2 x16
INTEL PROCESSOR
Sandy Bridge
LGA1155
DMI
FDI
CHANNEL A DDR3 SDRAM (800/1066/1333)
CHANNEL B DDR3 SDRAM (800/1066/1333)
DDR3 SDRAM CONN x1
DDR3 SDRAM CONN x1
XDP
C C
PCIE X1
PCIE X1
PCIE X1
VGA
DVI-D
B B
PCI EXPRESS (lane 5)
PCI EXPRESS (lane 4)
PCI EXPRESS (lane 3)
VGA
Display port B
SATA 2.0 (4 PORTS) SPI
SATA
INTEL
PCH
SPI I/F
LPC I/F
PCI EXPRESS (lane 2)
USB
HDA Link
PCI EXPRESS (lane 6)
TPM
LAN
RTL8111E-VL-CG
10/100/1000
USB
REAR*6 / FRONT*4
AUDIOCODEC
ALC888S/ALC662
PCIE to PCI
IT8893E/CX
PCI SLOTx2
KB
INTR
CIR
COM1
SIO
IT8728F/CX
LPT
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
248Tuesday, April 24, 2012
248Tuesday, April 24, 2012
248Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
CLOCK DISTRIBUTION
D D
14.318MHZ
X'TAL
4
CK505
SRC
SRC
DOT96
CPU0
48M
REF(14M)
3
48M
2
1
PCH_CLK_DMI
(FOR USB)
CLKIN_SATA
CLKIN_BCLK
CLKIN_DOT_96
REFCLK14IN
CLKOUT_ITPXDP_P/N
CLKOUT_PCIE0_P/N
XDP 100M
PCIE 100M
CPU
BCLK_P/NCLKOUT_DMI_P/N
XDP
ITPCLK_P/N
GLAN
REFCLK_P/N
PCIE to PCI
CLKOUT_PCIE2_P/N
C C
CLKOUT_PCIE3_P/N
CLKOUT_PCIE4_P/N
PCICLKIN
CLKOUT_PCIE5_P/N
PCICLK2
PCH
CLKOUTFLEX3
B B
25MHZ
X'TAL
Buffer Through Mode
FCI Mode
CLKOUT_PCI0
PCIE 100M
PCIE 100M
PCIE 100M
PCIE 100M
PCIE 100M
48M
33M
REFCLK_P/N
PCIE X1
CLK_P/N
PCIE X1
CLK_P/N
PCIE X1
CLK_P/N
PCIE X16
CLK_P/NCLKOUT_PEG_A_P/N
SIO_48M
SIO
PCICLK
CLKOUT_PCI4
REFCLK14IN
CLKIN_DMI_P/N
CLKIN_DOT_96P/N
A A
CLKIN_SATA_P/N
32.768KHZ
X'TAL
5
4
3
33M
2
GND
GND
GND
GND
Title
Title
Title
Clock Distribution
Clock Distribution
Clock Distribution
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
TPM
PCICLK
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
H61A01
H61A01
H61A01
1
348Tuesday, April 24, 2012
348Tuesday, April 24, 2012
348Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
4
3
2
1
POWER DELIVERY MAP
+12V_VIN(4PIN)
LYN/HVN(95W)
+VCORE (CPU Vcore)
SWITCHING
D D
DDR3(2 DIMM)
+V_1.5_SM=1.5V
+V_SM_VTT=0.75V 1A
SWITCHING
Icc=20A
Max=25A
+V_1.5_SM(1.5V) to
+V_SM_VTT (0.75V)
Icc=0.75A Max=1A
Icc=85A
Max=112A
SWITCHING
Icc=25A
Max=35A
SWITCHING
IccMax=17A
RTL8111E GbE Lan
+3VDUAL
70mA
C C
DVDD12/EVDD12
300mA
+12V
HDA Codec
+5VA
Voltage=5V
Icc=200mA
VCC
Voltage=3.3V
Icc=40mA
SIO 8728
3D3V_SYS
B B
Icc=50mA
3D3V_SB
Icc=50mA(S0)
3D3V_SB
Icc=38mA(S3)
12V TO +5VA
Icc=200mA
+3V
5VSB_SYS
5VSB_SYS to
3D3V_SB
+V_1.5_SM to
+V_1.05_PCH
Icc=6.5A
Max=8A
+3V
+3V TO
+V_1.8_SFR
Icc=1.5A
Max=1.6A
RTC
Battery
Voltage=1.1V
Icc(Max)=85A Max=112A
4-Phases Swithing
+V_1.1_AXG(Havendale only)
Voltage=1.1V
Icc=25A Max=35A
+V_1.5_SM(DDR III)
Voltage=1.5V Icc=4.5A
+VCCSA(0.925/0.85V)
IccMax=8.8A
+V_1.1_VTT(1.1/1.05V)
IccMax=8.5A
VCCPLL(1.8V) 1A
Cougar_Point(5.5W)
VCCCORE(+V_1.05_PCH)
Voltage=1.05V
Icc(Max)=6.2A
VCCME(+V_1.05_ME)
Voltage=1.05V
Icc(Max)=1.8A
VccADPLL 0.2A
VCCDMI 0.0655A
VccDFTERM=1.8V 0.2A
VCCVRM=1.8V 0.159A
+3VDUAL 0.123A
3.3V 0.409A
VccADAC=3.3V 0.068A
VccSusHDA=3.3V 0.01A
VccDSW3_3=3.3V 0.003A
VccSPI=3.3V 0.02A
VCCRTC 0.0022A
5V_SYS
5V_Dual to
+3VDUAL
Icc=1.25A
PCI Express X16
+12V=5.5A
+3VDUAL
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)
+3V=3A
PCI Express X1
+12V_SYS
Icc=0.5A
+3V_PCIAUX(3.3vAUX)
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(No wake)
3D3V_SYS
Icc=3A
PCI Express X1
+12V_SYS
Icc=0.5A
+3V_PCIAUX(3.3vAUX)
Icc(Max)=0.375A(S0)
Icc(Max)=0.02A(S3~S5)
3D3V_SYS
Icc=3A
PCI Express X1
+12V_SYS
Icc=0.5A
+3V_PCIAUX(3.3vAUX)
Icc(Max)=0.375A(S0)
Icc(Max)=0.02A(S3~S5)
3D3V_SYS
Icc=3A
12V+3V5VSB
PS2
+5V_DUAL=500mA(S0, S1)
+5V_DUAL=2mA(S3)
USB2.0 10 Ports
+5V_DUAL_USB=5A(S0, S1)
+5V_DUAL_USB=0.1A(S3)
A A
5
ACPI
Controller
+5V_DUAL
ACPI
Controller
+5V_DUAL_USB
4
+5V
+5VSB
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Power Delivery Map
Power Delivery Map
Power Delivery Map
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
448Tuesday, April 24, 2012
448Tuesday, April 24, 2012
448Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
4
3
2
1
POWER ON SEQUENCE
D D
C C
B B
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Power On Sequence
Power On Sequence
Power On Sequence
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
1.1Custom
1.1Custom
1.1Custom
of
of
of
548Tuesday, April 24, 2012
548Tuesday, April 24, 2012
548Tuesday, April 24, 2012
5
4
3
2
1
RESET / Power Good MAP
CPU-Sandy Bridge
Sequence Signal Name:
O_PWRBTN#IN
(1)
S_SLP_S4# S_SLP_S3#
(2)
O_PSON#
(3)
D D
B_ATX_PWROK
(4)
PCH_MEPWRGD
(5)
S_PCH_SYSPWROK P_VR_READY
(6)
PWRGD_3V
(7)
H_DRAMPWRGD
(8)
H_PWRGD
(9)
S_PLTRST#
(10)
X_PLTRST_PCIE_SLOT# K_PCIRST#_SLOT
(11)
A_Z_RST#
(12)
D3_RESET#
H_RESET#_R S_PLTRST#_R
HD Audio
C C
VRD 12
B B
RESET#
VR_RDY
S_SLP_M#
(12)
(9)
SYS_PWROK
HDA_RST#
(8)
PCH
PCIRST#
UNCOREPWRGOOD
SM_DRAMPWROK
Front Panel
FR_RST
PWRBTN#
SYS_RESET#
DRAMPWROK
PROCPWRGD
SLP_S4# SLP_S4_S5#
(7)
(3)
(3)
PLTRST# LRESET#
(10)
RSMRST#
PWROK
APWROK
PWRBTN#
PROCPWRGD
PWROK
> 1ms
(1)
(A2)
(6)
(2)
Buffer (UH2)
PANSWH#
SLP_S3#SLP_S3#
RSMRST#
PWR_GOOD_3V
PWRON
RESET*
(9)
(A1)
3VSB
PCIRST1#
PCIRST2#
SIO-8728F
PCIRST3# PWRGD
ATXPWRGD
PWR_GOOD_3V
PWRGD_PS
100~120ms
SM_DRAMRST*
(11)
PS_ON#
(11)
(11)
(5)
(4)
(8)
5V_SB3D3V_SB
DDRIII Slots
D3_RESET#
TPM
PERST#
LAN
PERST#
PCI-E 1x Slot1
PWRGD
PCI-E 1x Slot1
PWRGD
PCI-E 1x Slot1
PWRGD
PCI-E 16x Slot1
ATX Power
PSON
PWROK
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
Reset/power good
Reset/power good
Reset/power good
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
648Tuesday, April 24, 2012
648Tuesday, April 24, 2012
648Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
4
3
2
1
IRQ Routing Table
INTA# INTB# INTC# INTD# IDSEL REQn# GNTn#
Slot1 A B C D 16 0 0
D D
INTA# INTB# INTC# INTD# IDSEL REQn# GNTn#
Slot2 ABC D 172 2
STRAPPING Table
CPU side
CFG[17:0] Description
[2]
[6:5]
C C
PCI Express static x16
lane numbering reversal
PCI Express Bifurcation
1: normal
0: lane numbers reversed
00: 1x8, 2x4 PCI Express
01: reserved
10: 2x8 PCI Express
11: 1x16 PCI Express
Default
Default
B B
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
STRAP
STRAP
STRAP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
748Tuesday, April 24, 2012
748Tuesday, April 24, 2012
748Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
D D
V_1D05V_CPU
H_VIDSCK_VR44
H_VIDSOUT_VR44
H_VIDALERT_N_VR44
MINIMIZE STUB BETWEEN THESE AND RESISTORS AT SINAI PAGE
PLACE IN CRB AREA
PCH_PECI20,36
H_PROCHOT_N36,44
PCH_THERMTRIP_N20
DMI/FDI TERMINATION VOLTAGE
DC COUPLED: TX/RX TO VCC ISF SAMPLED HIGH
DC COUPLED: TX/RX TO VSS IF SAMPLED LOW
AC COUPLED: TX SET TO VCC/2, RX SET TO VSS REGARDLESS OF THIS STRAP
C C
PROC_SEL
For future processor compatibility
V_NAND_IO
R559
R559
*
*
2.2KOhm
2.2KOhm
+/-1%
+/-1%
C298
C298
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
R560 4.7KOhm +/-1%
R560 4.7KOhm +/-1%
*
*
H_SKTOCC_N21
NVR_CLE 22
PLACE R381, R382,C437 IN SOCKET CAVITY
V_SM
R381
R381
*
*
100 Ohm
100 Ohm
+/-1%
B B
+/-1%
PRO_DDR_VREF
R382
R382
*
*
100 Ohm
100 Ohm
+/-1%
+/-1%
R234
R234
*
*
*
*
51
51
+/-1%
+/-1%
Dummy
Dummy
Dummy
Dummy
DEFENSIVE SITE
V_1D05V_CPU
R215
R215
1K
1K
+/-1%
+/-1%
C437
C437
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
R211
R211
*
*
1K
1K
+/-1%
+/-1%
Dummy
Dummy
R212
R212
*
*
1K
1K
+/-1%
+/-1%
Dummy
Dummy
PCH_THERMTRIP_N
V_1D8V_SFR V_NAND_IO
H_CATERR_N
H_PECI
H_PWRGD
R201
R201
*
*
91 Ohm
91 Ohm
+/-1%
+/-1%
Dummy
Dummy
4
Place R216 & R213 near CPU
R213
R213
R216
R216
*
*
*
*
75
75
110Ohm
110Ohm
+/-1%
+/-1%
+/-1%
+/-1%
H_DRAMPWRGD21
CPU_RST_N46
H_PROCHOT_N
PCH_THERMTRIP_N
H_SKTOCC_N
PROC_SEL
PRO_DDR_VREF
C_CPU_CLK_DP23
C_CPU_CLK_DN23
H_PWRGD21,44,46
CFG046
H_PWRGD
R666 124
R666 124
H_PM_SYNC_020
CFG0
TP1TP1
TP2TP2
TP3TP3
TP4TP4
TP5TP5
TP6TP6
TP7TP7
TP8TP8
TP9TP9
TP10TP10
TP11TP11
TP12TP12
TP13TP13
TP14TP14
TP15TP15
TP25TP25
TP26TP26
TERMINATION IDEALLY TO BE
PLACED PLACE CLOSE TO EACH OTHER TO REDUCE STUB
NEXT TO IT OR WITHIN 1.5 OF CPU.
PLACE TRST* TERMINATION
ANYWHERE ON ROUTE.
VIDALERT_N
*
*
CPU_RST_N
H_PM_SYNC_0
H_PECI
H_CATERR_N
CFG0
CFG1
CFG2
CFG3
CFG4
SWITCH_SEL_CPU
CFG6
CFG7
CFG8CFG8
CFG9CFG9
CFG10
CFG11CFG11
CFG12CFG12
CFG13CFG13
CFG14CFG14
CFG15CFG15
TPEV_SNB_PCUSTB_0
TPEV_SNB_PCUSTB_1
PLACE TDO TERMINATION
NEAR XDP CONNECTOR
AJ19
AJ33
AJ22
AT14
W2
W1
C37
B37
A37
J40
F36
E38
J35
E37
H34
G35
K32
H36
J36
J37
K36
L36
N35
L37
M36
J38
L35
M38
N36
N38
N39
N37
N40
G37
G36
AY3
H7
H8
U1E
U1E
BCLK[0]
BCLK#[0]
VIDSCLK
VIDSOUT
VIDALERT#
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
PM_SYNC
PECI
CATERR#
PROCHOT#
THERMTRIP#
SKTOCC#
FC_K32
SM_VREF
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD30
RSVD31
RSVD32
RSVD33
CPU_SKT_H2
CPU_SKT_H2
H_TRST_N
H_TDO
H_TMS
H_TDI
H_PRDY_N
H_PROCHOT_N
H_TCK
3
?
?
SKT_H2
SKT_H2
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
VCC_VALIDATION_SENSE
VSSU_VALIDATION_SENSE
VCCAXG_VALIDATION_SENSE
VSSGT_VALIDATION_SENSE
MISC
MISC
5 OF 11
5 OF 11
VCCIO_SELECT
VCCSA_VID_0
VCCSA_SENSE
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
VSSAXG_SENSE
VSSAXG_SENSE
TRST#
PRDY#
PREQ#
BCLK_ITP
BCLK_ITP#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RN39
RN39
*
*
1
2
3
4
5
6
7 8
51
51
+/-5%
+/-5%
RN40
RN40
*
*
1
2
3
4
5
6
7 8
51
51
+/-5%
+/-5%
TDO
TDI
TCK
TMS
DBR#
?
?
V_1D05V_CPU
P33
P34
T2
A36
B36
AB4
AB3
L32
M32
L39
L40
M40
L38
J39
K38
K40
E39
C40
D40
H40
H38
G38
G40
G39
F38
E40
F40
B39
J33
L34
L33
K34
N33
M34
AV1
AW2
L9
J9
K9
L31
J31
K31
AD34
AD35
VCCIO_SELECT
VCCSA_SENSE
VCC_SENSE
VSS_SENSE
VCCP_SENSE
VSSP_SENSE
VCCAXG_SENSE
VSSAXG_SENSE
H_TDO
H_TDI
H_TCK
H_TMS
H_TRST_N
H_PRDY_N
H_PREQ_N
H_DBR_N
ITP_CLKINP
ITP_CLKINN
TPEV_SNB_MBP0
TPEV_SNB_MBP1
TPEV_SNB_MBP2
TPEV_SNB_MBP3
TPEV_SNB_MBP4
TPEV_SNB_MBP5
TPEV_SNB_MBP6
TPEV_SNB_MBP7
#REFDE46#REFDE46
1 2
VCCSA_VID 40
H_VCCSA_SENSE 40
H_VCC_SENSE 44
H_VSS_SENSE 44
H_VCCIO_SENSE 43
H_VSSIO_SENSE 43
H_VCCAGX_SENSE 44
H_VSSAGX_SENSE 44
ITP_CLKINP 46
ITP_CLKINN 46
2
VCCIO_SEL 36,43
H_TDO 46
H_TDI 46
H_TCK 46
H_TMS 46
H_TRST_N 46
H_PRDY_N 46
H_PREQ_N 46
TPEV_SNB_MBP0 46
TPEV_SNB_MBP1 46
TPEV_SNB_MBP2 46
TPEV_SNB_MBP3 46
TPEV_SNB_MBP4 46
TPEV_SNB_MBP5 46
TPEV_SNB_MBP6 46
TPEV_SNB_MBP7 46
PLTRST_N21,36,46
R214 0 +/-5%
R214 0 +/-5%
*
*
Dummy
Dummy
3D3V_DUAL 3D3V_SYS
#REFDE41#REFDE41
1 2
*
*
3D3V_SUS
V_1D05V_CPU
*
*
135
DS
Q40
Q40
G
2N7002
2N7002
C292
C292
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
642
*
*
Dummy
Dummy
7 8
R210
R210
220 Ohm
220 Ohm
+/-1%
+/-1%
RN59
RN59
10K
10K
+/-5%
+/-5%
VCCIO_SELECT
*
*
FP_RST# 21,39,46
R300 4.7KOhm
R300 4.7KOhm
*
*
DS
Q42
Q42
G
2N7002
2N7002
C306
C306
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
+/-1%
+/-1%
CPU_RST_N
1
Need to be double checked.
A A
V_1D05V_CPU
*
*
R296
R296
10K
10K
Dummy
Dummy
Need check the power and the value of R221
according to the latest CPU datasheet
SWITCH_SEL_CPU
5
4
3
2
Title
Title
Title
CPU1-MSIC
CPU1-MSIC
CPU1-MSIC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
H61A01
H61A01
H61A01
1
848Tuesday, April 24, 2012
848Tuesday, April 24, 2012
848Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
D D
U1C
U1C
B11
X_1X16_RXP016
X_1X16_RXN016
X_1X16_RXP116
X_1X16_RXN116
X_1X16_RXP216
X_1X16_RXN216
X_1X16_RXP316
X_1X16_RXN316
X_1X16_RXP416
X_1X16_RXN416
X_1X16_RXP516
X_1X16_RXN516
X_1X16_RXP616
X_1X16_RXN616
X_1X16_RXP716
X_1X16_RXN716
X_1X16_RXP816
X_1X16_RXN816
X_1X16_RXP916
X_1X16_RXN916
X_1X16_RXP1016
H_DMI_RX_DP019
H_DMI_RX_DN019
H_DMI_RX_DP119
H_DMI_RX_DN119
H_DMI_RX_DP219
H_DMI_RX_DN219
H_DMI_RX_DP319
H_DMI_RX_DN319
R194 24.9+/-1%*R194 24.9+/-1%
X_1X16_RXN1016
X_1X16_RXP1116
X_1X16_RXN1116
X_1X16_RXP1216
X_1X16_RXN1216
X_1X16_RXP1316
X_1X16_RXN1316
X_1X16_RXP1416
X_1X16_RXN1416
X_1X16_RXP1516
X_1X16_RXN1516
C C
V_1D05V_CPU
B B
Short B4 & C4 together, route as a single 4 mil trace to R2
Route B5 to R2 as a aeperate 10 mil trace
X_1X16_RXP0
X_1X16_RXN0
X_1X16_RXP1
X_1X16_RXN1
X_1X16_RXP2
X_1X16_RXN2
X_1X16_RXP3
X_1X16_RXN3
X_1X16_RXP4
X_1X16_RXN4
X_1X16_RXP5
X_1X16_RXN5
X_1X16_RXP6
X_1X16_RXN6
X_1X16_RXP7
X_1X16_RXN7
X_1X16_RXP8
X_1X16_RXN8
X_1X16_RXP9
X_1X16_RXN9
X_1X16_RXP10
X_1X16_RXN10
X_1X16_RXP11
X_1X16_RXN11
X_1X16_RXP12
X_1X16_RXN12
X_1X16_RXP13
X_1X16_RXN13
X_1X16_RXP14
X_1X16_RXN14
X_1X16_RXP15
X_1X16_RXN15
*
PEG_RX[0]
B12
PEG_RX#[0]
D12
PEG_RX[1]
D11
PEG_RX#[1]
C10
PEG_RX[2]
C9
PEG_RX#[2]
E10
PEG_RX[3]
E9
PEG_RX#[3]
B8
PEG_RX[4]
B7
PEG_RX#[4]
C6
PEG_RX[5]
C5
PEG_RX#[5]
A5
PEG_RX[6]
A6
PEG_RX#[6]
E2
PEG_RX[7]
E1
PEG_RX#[7]
F4
PEG_RX[8]
F3
PEG_RX#[8]
G2
PEG_RX[9]
G1
PEG_RX#[9]
H3
PEG_RX[10]
H4
PEG_RX#[10]
J1
PEG_RX[11]
J2
PEG_RX#[11]
K3
PEG_RX[12]
K4
PEG_RX#[12]
L1
PEG_RX[13]
L2
PEG_RX#[13]
M3
PEG_RX[14]
M4
PEG_RX#[14]
N1
PEG_RX[15]
N2
PEG_RX#[15]
W5
DMI_RX[0]
W4
DMI_RX#[0]
V3
DMI_RX[1]
V4
DMI_RX#[1]
Y3
DMI_RX[2]
Y4
DMI_RX#[2]
AA4
DMI_RX_3
AA5
DMI_RX#[3]
P3
PE_RX[0]
P4
PE_RX#[0]
R2
PE_RX[1]
R1
PE_RX#[1]
T4
PE_RX[2]
T3
PE_RX#[2]
U2
PE_RX[3]
U1
PE_RX#[3]
B5
GRCOMV_CPU_VCCIO
PEG_ICOMPO
C4
PEG_RCOMPO
B4
PEG_ICOMPI
CPU_SKT_H2
CPU_SKT_H2
V_1D8V_SFR
4
?
?
SKT_H2
SKT_H2
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
C434 0.1uF 16V, X7R, +/-10%
C434 0.1uF 16V, X7R, +/-10%
DMIGEN PEG
DMIGEN PEG
Dummy
Dummy
PEG_TX[0]
PEG_TX#[0]
PEG_TX[1]
PEG_TX#[1]
PEG_TX[2]
PEG_TX#[2]
PEG_TX[3]
PEG_TX#[3]
PEG_TX[4]
PEG_TX#[4]
PEG_TX[5]
PEG_TX#[5]
PEG_TX[6]
PEG_TX#[6]
PEG_TX[7]
PEG_TX#[7]
PEG_TX[8]
PEG_TX#[8]
PEG_TX[9]
PEG_TX#[9]
PEG_TX[10]
PEG_TX#[10]
PEG_TX[11]
PEG_TX#[11]
PEG_TX[12]
PEG_TX#[12]
PEG_TX[13]
PEG_TX#[13]
PEG_TX[14]
PEG_TX#[14]
PEG_TX[15]
PEG_TX#[15]
DMI_TX[0]
DMI_TX#[0]
DMI_TX[1]
DMI_TX#[1]
DMI_TX[2]
DMI_TX#[2]
DMI_TX[3]
DMI_TX#[3]
PE_TX[0]
PE_TX#[0]
PE_TX[1]
PE_TX#[1]
PE_TX[2]
PE_TX#[2]
PE_TX[3]
PE_TX#[3]
3 OF 11
3 OF 11
*
*
3
C13
X_1X16_TXP0
C14
E14
E13
G14
G13
F12
F11
J14
J13
D8
D7
D3
C3
E6
E5
F8
F7
G10
G9
G5
G6
K7
K8
J5
J6
M8
M7
L6
L5
N5
N6
V7
V6
W7
W8
Y6
Y7
AA7
AA8
P8
P7
T7
T8
R6
R5
U5
U6
?
?
X_1X16_TXP0 16
X_1X16_TXN0
X_1X16_TXN0 16
X_1X16_TXP1
X_1X16_TXP1 16
X_1X16_TXN1
X_1X16_TXN1 16
X_1X16_TXP2
X_1X16_TXP2 16
X_1X16_TXN2
X_1X16_TXN2 16
X_1X16_TXP3
X_1X16_TXP3 16
X_1X16_TXN3
X_1X16_TXN3 16
X_1X16_TXP4
X_1X16_TXP4 16
X_1X16_TXN4
X_1X16_TXN4 16
X_1X16_TXP5
X_1X16_TXP5 16
X_1X16_TXN5
X_1X16_TXN5 16
X_1X16_TXP6
X_1X16_TXP6 16
X_1X16_TXN6
X_1X16_TXN6 16
X_1X16_TXP7
X_1X16_TXP7 16
X_1X16_TXN7
X_1X16_TXN7 16
X_1X16_TXP8
X_1X16_TXP8 16
X_1X16_TXN8
X_1X16_TXN8 16
X_1X16_TXP9
X_1X16_TXP9 16
X_1X16_TXN9
X_1X16_TXN9 16
X_1X16_TXP10
X_1X16_TXP10 16
X_1X16_TXN10
X_1X16_TXN10 16
X_1X16_TXP11
X_1X16_TXP11 16
X_1X16_TXN11
X_1X16_TXN11 16
X_1X16_TXP12
X_1X16_TXP12 16
X_1X16_TXN12
X_1X16_TXN12 16
X_1X16_TXP13
X_1X16_TXP13 16
X_1X16_TXN13
X_1X16_TXN13 16
X_1X16_TXP14
X_1X16_TXP14 16
X_1X16_TXN14
X_1X16_TXN14 16
X_1X16_TXP15
X_1X16_TXP15 16
X_1X16_TXN15
X_1X16_TXN15 16
H_DMI_TX_DP0 19
H_DMI_TX_DN0 19
H_DMI_TX_DP1 19
H_DMI_TX_DN1 19
H_DMI_TX_DP2 19
H_DMI_TX_DN2 19
H_DMI_TX_DP3 19
H_DMI_TX_DN3 19
DESIGN NOTE:
N/T: PCIE X4 LANES ARE NOT SUPPORTED ON DESKTOP CPU SKUS
V_1D05V_CPU
C428 0.1uF 16V, X7R, +/-10%
C428 0.1uF 16V, X7R, +/-10%
C410 0.1uF 16V, X7R, +/-10%
C410 0.1uF 16V, X7R, +/-10%
C443 0.1uF 16V, X7R, +/-10%
C443 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
Dummy
Dummy
*
*
Dummy
Dummy
*
*
V_1D05V_CPU
V_CPU_VCCIO
H_FDI_FSYNC0_122
H_FDI_LSYNC0_122
H_FDI_FSYNC1_122
H_FDI_LSYNC1_122
R374 24.9+/-1%*R374 24.9+/-1%
2
?
?
SKT_H2
SKT_H2
U1D
U1D
AC5
FDI_FSYNC_0
AC4
FDI_LSYNC_0
AE5
FDI_LSYNC_1
AE4
FDI_FSYNC_1
H_FDI_INT_122
*
AG3
AE2
AE1
V_1D05V_CPU
FDI_INT
FDI_COMPIO
FDI_ICOMPO
CPU_SKT_H2
CPU_SKT_H2
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
4 OF 11
4 OF 11
C286 0.1uF 16V, X7R, +/-10%
C286 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C302 0.1uF 16V, X7R, +/-10%
C302 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C299 0.1uF 16V, X7R, +/-10%
C299 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C287 0.1uF 16V, X7R, +/-10%
C287 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C313 0.1uF 16V, X7R, +/-10%
C313 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C320 0.1uF 16V, X7R, +/-10%
C320 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C285 0.1uF 16V, X7R, +/-10%
C285 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C343 0.1uF 16V, X7R, +/-10%
C343 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C281 0.1uF 16V, X7R, +/-10%
C281 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C293 0.1uF 16V, X7R, +/-10%
C293 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C332 0.1uF 16V, X7R, +/-10%
C332 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C323 0.1uF 16V, X7R, +/-10%
C323 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
C283 0.1uF 16V, X7R, +/-10%
C283 0.1uF 16V, X7R, +/-10%
Dummy
Dummy
*
*
FDI_TX[0]
FDI_TX[0]
FDI_TX[0]
FDI_TX#[0]
FDI_TX[1]
FDI_TX#[1]
FDI_TX[2]
FDI_TX#[2]
FDI_TX[3]
FDI_TX#[3]
FDI_TX[4]
FDI_TX#[4]
FDI_TX[5]
FDI_TX#[5]
FDI_TX[6]
FDI_TX#[6]
FDI_TX[7]
FDI_TX#[7]
FDI
FDI
LINK
LINK
AC8
AC7
AC2
AC3
AD2
AD1
AD4
AD3
AD7
AD6
AE7
AE8
AF3
AF2
AG2
AG1
?
?
1
H_FDI_TX_DP0 22
H_FDI_TX_DN0 22
H_FDI_TX_DP1 22
H_FDI_TX_DN1 22
H_FDI_TX_DP2 22
H_FDI_TX_DN2 22
H_FDI_TX_DP3 22
H_FDI_TX_DN3 22
H_FDI_TX_DP4 22
H_FDI_TX_DN4 22
H_FDI_TX_DP5 22
H_FDI_TX_DN5 22
H_FDI_TX_DP6 22
H_FDI_TX_DN6 22
H_FDI_TX_DP7 22
H_FDI_TX_DN7 22
Stiching CAP for FDI
A A
5
4
3
Stiching CAP for PEGStiching CAP for DMI
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
CPU2-PEG/DMI/FDI
CPU2-PEG/DMI/FDI
CPU2-PEG/DMI/FDI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
948Tuesday, April 24, 2012
948Tuesday, April 24, 2012
948Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
4
3
2
1
D D
C C
B B
D3_DATA_A[63..0]14
?
?
SKT_H2
SKT_H2
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
1 OF 11
1 OF 11
AU35
AW37
AU39
AU36
AW35
AY36
AU38
AU37
AR40
AR37
AN38
AN37
AR39
AR38
AN39
AN40
AG40
AG37
AE38
AE37
AG39
AG38
AE39
AE40
AV37
AP38
AK38
AF38
AV36
AP39
AK39
AF39
AW3
AW5
AW7
AW9
AL40
AL37
AJ38
AJ37
AL39
AL38
AJ39
AJ40
AW4
AW8
AN1
AN4
AR3
AR4
AN2
AN3
AR2
AR1
AV2
AV5
AU2
AU3
AU5
AY5
AY7
AU7
AV9
AU9
AV7
AY9
AK3
AP3
AV8
AK2
AP2
AV4
AJ3
AJ4
AL3
AL4
AJ2
AJ1
AL2
AL1
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
?
?
D3_DATA_A0
D3_DATA_A1
D3_DATA_A2
D3_DATA_A3
D3_DATA_A4
D3_DATA_A5
D3_DATA_A6
D3_DATA_A7
D3_DATA_A8
D3_DATA_A9
D3_DATA_A10
D3_DATA_A11
D3_DATA_A12
D3_DATA_A13
D3_DATA_A14
D3_DATA_A15
D3_DATA_A16
D3_DATA_A17
D3_DATA_A18
D3_DATA_A19
D3_DATA_A20
D3_DATA_A21
D3_DATA_A22
D3_DATA_A23
D3_DATA_A24
D3_DATA_A25
D3_DATA_A26
D3_DATA_A27
D3_DATA_A28
D3_DATA_A29
D3_DATA_A30
D3_DATA_A31
D3_DATA_A32
D3_DATA_A33
D3_DATA_A34
D3_DATA_A35
D3_DATA_A36
D3_DATA_A37
D3_DATA_A38
D3_DATA_A39
D3_DATA_A40
D3_DATA_A41
D3_DATA_A42
D3_DATA_A43
D3_DATA_A44
D3_DATA_A45
D3_DATA_A46
D3_DATA_A47
D3_DATA_A48
D3_DATA_A49
D3_DATA_A50
D3_DATA_A51
D3_DATA_A52
D3_DATA_A53
D3_DATA_A54D3_DATA_A54
D3_DATA_A55D3_DATA_A55
D3_DATA_A56D3_DATA_A56
D3_DATA_A57D3_DATA_A57
D3_DATA_A58D3_DATA_A58
D3_DATA_A59D3_DATA_A59
D3_DATA_A60D3_DATA_A60
D3_DATA_A61D3_DATA_A61
D3_DATA_A62D3_DATA_A62
D3_DATA_A63D3_DATA_A63
D3_DQS_A_DP014
D3_DQS_A_DP114
D3_DQS_A_DP214
D3_DQS_A_DP314
D3_DQS_A_DP414
D3_DQS_A_DP514
D3_DQS_A_DP614
D3_DQS_A_DP714
D3_DQS_A_DN014
D3_DQS_A_DN114
D3_DQS_A_DN214
D3_DQS_A_DN314
D3_DQS_A_DN414
D3_DQS_A_DN514
D3_DQS_A_DN614
D3_DQS_A_DN714
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_WE#
SA_CAS#
SA_RAS#
SA_BS_0
SA_BS[1]
SA_BS[2]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_CKE[0]
SA_CKE[1]
SA_CKE[3]
SA_CKE[2]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_CK[0]
SA_CK#[0]
SA_CK[1]
SA_CK#[1]
SA_CK[2]
SA_CK#[2]
SA_CK[3]
SA_CK#[3]
SM_DRAMRST#
SA_DQS[8]
SA_DQS#[8]
SA_ECC_CB[0]
SA_ECC_CB[1]
SA_ECC_CB[2]
SA_ECC_CB[3]
SA_ECC_CB[4]
SA_ECC_CB[5]
SA_ECC_CB[6]
SA_ECC_CB[7]
DDR_A
DDR_A
CPU_SKT_H2
CPU_SKT_H2
U1A
U1A
AV27
D3_MAA_A0
AY24
D3_MAA_A1
AW24
D3_MAA_A2
AW23
D3_MAA_A3
AV23
D3_MAA_A4
AT24
D3_MAA_A5
AT23
D3_MAA_A6
AU22
D3_MAA_A7
AV22
D3_MAA_A8
AT22
D3_MAA_A9
AV28
D3_MAA_A10
AU21
D3_MAA_A11
AT21
D3_MAA_A12
AW32
D3_MAA_A13
AU20
D3_MAA_A14
AT20
D3_MAA_A15
AW29
AV30
AU28
AY29
D3_SBS_A0
AW28
D3_SBS_A1
AV20
D3_SBS_A2
AU29
D3_SCS_A_#0
AV32
D3_SCS_A_#1
AW30
AU33
AV19
D3_SCKE_A0
AT19
D3_SCKE_A1
AU18
AV18
AV31
D3_ODT_A0
AU32
D3_ODT_A1
AU30
AW33
AY25
AW25
AU24
AU25
AW27
AY27
AV26
AW26
#REFDE34#REFDE34
AW18
AV13
AV12
AU12
AU14
AW13
AY13
AU13
AU11
AY12
AW12
12
*
*
DDR ECC IS NOT SUPPORTED ON DESKTOP SKUS
ECC TRACES ARE FOR ENGINEERING FUNCTION ONLY
DESIGN NOTE:
D3_MAA_A[15..0] 14
D3_WE_A# 14
D3_CAS_A# 14
D3_RAS_A# 14
D3_SBS_A[2..0] 14
D3_SCS_A_#0 14
D3_SCS_A_#1 14
D3_SCKE_A0 14
D3_SCKE_A1 14
D3_ODT_A0 14
D3_ODT_A1 14
D3_CK_DDR_A_DP0 14
D3_CK_DDR_A_DN0 14
D3_CK_DDR_A_DP1 14
D3_CK_DDR_A_DN1 14
D3_DRAMRST# 14,15
C560
C560
0.1uF
0.1uF
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
DESIGN NOTE:
RC FILTER
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
CPU3-DDR3_CHA
CPU3-DDR3_CHA
CPU3-DDR3_CHA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
10 48Tuesday, April 24, 2012
10 48Tuesday, April 24, 2012
10 48Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
4
3
2
1
D D
C C
B B
D3_DATA_B[63..0]15
AM10
AL10
AP10
AR10
AM12
AM13
AR13
AP13
AL12
AL13
AR12
AP12
AR28
AR29
AL28
AL29
AP28
AP29
AM28
AM29
AP32
AP31
AP35
AP34
AR32
AR31
AR35
AR34
AM32
AM31
AL35
AL32
AM34
AL31
AM35
AL34
AH35
AH34
AE34
AE35
AJ35
AJ34
AF33
AF35
AN13
AN29
AP33
AL33
AG35
AN12
AN28
AR33
AM33
AG34
AG7
AG8
AG5
AG6
AM7
AM6
AM9
AP7
AR7
AP6
AR6
AP9
AR9
AH7
AM8
AR8
AH6
AP8
AJ9
AJ8
AJ6
AJ7
AL7
AL6
AL9
AL8
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#7]
?
?
D3_DATA_B0
D3_DATA_B1
D3_DATA_B2
D3_DATA_B3
D3_DATA_B4
D3_DATA_B5
D3_DATA_B6
D3_DATA_B7
D3_DATA_B8
D3_DATA_B9
D3_DATA_B10
D3_DATA_B11
D3_DATA_B12
D3_DATA_B13
D3_DATA_B14
D3_DATA_B15
D3_DATA_B16
D3_DATA_B17
D3_DATA_B18
D3_DATA_B19
D3_DATA_B20
D3_DATA_B21
D3_DATA_B22
D3_DATA_B23
D3_DATA_B24
D3_DATA_B25
D3_DATA_B26
D3_DATA_B27
D3_DATA_B28
D3_DATA_B29
D3_DATA_B30
D3_DATA_B31
D3_DATA_B32
D3_DATA_B33
D3_DATA_B34
D3_DATA_B35
D3_DATA_B36
D3_DATA_B37
D3_DATA_B38
D3_DATA_B39
D3_DATA_B40
D3_DATA_B41
D3_DATA_B42
D3_DATA_B43
D3_DATA_B44
D3_DATA_B45
D3_DATA_B46
D3_DATA_B47
D3_DATA_B48
D3_DATA_B49
D3_DATA_B50
D3_DATA_B51
D3_DATA_B52
D3_DATA_B53
D3_DATA_B54
D3_DATA_B55
D3_DATA_B56
D3_DATA_B57
D3_DATA_B58
D3_DATA_B59
D3_DATA_B60
D3_DATA_B61
D3_DATA_B62
D3_DQS_B_DP015
D3_DQS_B_DP115
D3_DQS_B_DP215
D3_DQS_B_DP315
D3_DQS_B_DP415
D3_DQS_B_DP515
D3_DQS_B_DP615
D3_DQS_B_DP715
D3_DQS_B_DN015
D3_DQS_B_DN115
D3_DQS_B_DN215
D3_DQS_B_DN315
D3_DQS_B_DN415
D3_DQS_B_DN515
D3_DQS_B_DN615
D3_DQS_B_DN715
D3_DATA_B63
?
?
SKT_H2
SKT_H2
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_WE#
SB_CAS#
SB_RAS#
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_CKE[0]
SB_CKE[1]
SB_CKE[2]
SB_CKE[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_CK[0]
SB_CK[0]
SB_CK[0]
SB_CK#[0]
SB_CK[1]
SB_CK#[1]
SB_CK[2]
SB_CK#[2]
SB_CK[3]
SB_CK#[3]
SB_DIMM_DQVREF
SA_DIMM_DQVREF
SB_DQS[8]
SB_DQS#[8]
SB_ECC_CB[0]
SB_ECC_CB[1]
SB_ECC_CB[2]
SB_ECC_CB[3]
SB_ECC_CB[4]
SB_ECC_CB[5]
SB_ECC_CB[6]
SB_ECC_CB[7]
DDR_B
DDR_B
2 OF 11
2 OF 11
CPU_SKT_H2
CPU_SKT_H2
U1B
U1B
AK24
AM20
AM19
AK18
AP19
AP18
AM18
AL18
AN18
AY17
AN23
AU17
AT18
AR26
AY16
AV16
AR25
AK25
AP24
AP23
AM24
AW17
AN25
AN26
AL25
AT26
AU16
AY15
AW15
AV15
AL26
AP26
AM26
AK26
AL21
AL22
AL20
AK20
AL23
AM22
AP21
AN21
AH1
AH4
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
AN16
AN15
AL16
AM16
AP16
AR16
AL15
AM15
AR15
AP15
D3_MAA_B[15..0] 15
D3_CAS_B# 15
D3_RAS_B# 15
D3_SBS_B[2..0] 15
D3_SCS_B_#0 15
D3_SCS_B_#1 15
D3_SCKE_B0 15
D3_SCKE_B1 15
D3_ODT_B0 15
D3_ODT_B1 15
D3_CK_DDR_B_DP0 15
D3_CK_DDR_B_DN0 15
D3_CK_DDR_B_DP1 15
D3_CK_DDR_B_DN1 15
DIMM_DQ_CPU_VREF_B 15
DIMM_DQ_CPU_VREF_A 14
C540
C540
0.1uF
0.1uF
16V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%
D3_WE_B# 15
D3_MAA_B10
D3_MAA_B11
D3_MAA_B12
D3_MAA_B13
D3_MAA_B14
D3_MAA_B15
D3_SCS_B_#0
D3_SCS_B_#1
D3_SCKE_B0
D3_SCKE_B1
C541
C541
*
*
0.1uF
0.1uF
D3_MAA_B0
D3_MAA_B1
D3_MAA_B2
D3_MAA_B3
D3_MAA_B4
D3_MAA_B5
D3_MAA_B6
D3_MAA_B7
D3_MAA_B8
D3_MAA_B9
D3_SBS_B0
D3_SBS_B1
D3_SBS_B2
D3_ODT_B0
D3_ODT_B1
*
*
width 10mil spacing 12mil,near CPU
DDR ECC IS NOT SUPPORTED ON DESKTOP SKUS
ECC TRACES ARE FOR ENGINEERING FUNCTION ONLY
DESIGN NOTE:
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
CPU4-DDR3_CHB
CPU4-DDR3_CHB
CPU4-DDR3_CHB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
11 48Tuesday, April 24, 2012
11 48Tuesday, April 24, 2012
11 48Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
U1F
U1F
A12
VCC
D D
C C
B B
A13
A14
A15
A16
A18
A24
A25
A27
A28
B15
B16
B18
B24
B25
B27
B28
B30
B31
B33
B34
C15
C16
C18
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D14
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
D35
D36
E15
E16
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35
F15
F16
F18
F19
F21
F22
F24
F25
F27
F28
F30
F31
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CPU_SKT_H2
CPU_SKT_H2
SKT_H2
SKT_H2
REV = 1.6
REV = 1.6
CPU POWER
CPU POWER
6 OF 11
6 OF 11
4
V_CPU_CORE
?
?
F32
VCC
F33
VCC
F34
VCC
G15
VCC
G16
VCC
G18
VCC
G19
VCC
G21
VCC
G22
VCC
G24
VCC
G25
VCC
G27
VCC
G28
VCC
G30
VCC
G31
VCC
G32
VCC
G33
VCC
H13
VCC
H14
VCC
H15
VCC
H16
VCC
H18
VCC
H19
VCC
H21
VCC
H22
VCC
H24
VCC
H25
VCC
H27
VCC
H28
VCC
H30
VCC
H31
VCC
H32
VCC
J12
VCC
J15
VCC
J16
VCC
J18
VCC
J19
VCC
J21
VCC
J22
VCC
J24
VCC
J25
VCC
J27
VCC
J28
VCC
J30
VCC
K15
VCC
K16
VCC
K18
VCC
K19
VCC
K21
VCC
K22
VCC
K24
VCC
K25
VCC
K27
VCC
K28
VCC
K30
VCC
L13
VCC
L14
VCC
L15
VCC
L16
VCC
L18
VCC
L19
VCC
L21
VCC
L22
VCC
L24
VCC
L25
VCC
L27
VCC
L28
VCC
L30
VCC
M14
VCC
M15
VCC
M16
VCC
M18
VCC
M19
VCC
M21
VCC
M22
VCC
M24
VCC
M25
VCC
M27
VCC
M28
VCC
M30
VCC
?
?
V_1D1V_AXG
AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
T33
T34
T35
T36
T37
T38
T39
T40
U33
U34
U35
U36
U37
U38
U39
U40
W33
W34
W35
W36
W37
W38
Y33
Y34
Y35
Y36
Y37
Y38
3
U1G
U1G
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
VCCAXG
CPU_SKT_H2
CPU_SKT_H2
SKT_H2
SKT_H2
REV = 4
REV = 4
GFX POWERGFX POWER
GFX POWERGFX POWER
7 OF 11
7 OF 11
2
V_1D05V_CPU
M13
A11
A7
AA3
AB8
?
?
V_VCCSA
?
?
V_1D8V_SFR
AG33
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK30
AK11
AK12
AF8
AJ16
AJ17
AJ26
AJ28
AJ32
B9
D10
D6
E3
E4
G3
G4
J3
J4
J7
J8
L3
L4
L7
N3
N4
N7
R3
R4
R7
U3
U4
U7
V8
W3
H10
H11
H12
J10
K10
K11
L11
L12
M10
M11
M12
SKT_H2
SKT_H2
U1H
U1H
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCPLL
VCCPLL
CPU_SKT_H2
CPU_SKT_H2
?
?
IO/SA/PLL
IO/SA/PLL
POWER
POWER
8 OF 11
8 OF 11
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
AJ13
AJ14
AJ23
AJ24
AR20
AR21
AR22
AR23
AR24
AU19
AU23
AU27
AU31
AV21
AV24
AV25
AV29
AV33
AW31
AY23
AY26
AY28
AJ20
?
?
1
V_SM
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
CPU5-POWER
CPU5-POWER
CPU5-POWER
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
12 48Tuesday, April 24, 2012
12 48Tuesday, April 24, 2012
12 48Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
?
?
SKT_H2
SKT_H2
U1I
U1I
A17
VSS
A23
A26
A29
A35
AA33
AA34
AA35
D D
C C
B B
AA36
AA37
AA38
AD33
AD36
AD38
AD39
AD40
AE33
AE36
AF34
AF36
AF37
AF40
AG36
AH33
AH36
AH37
AH38
AH39
AH40
AJ12
AJ15
AJ18
AJ21
AJ25
AJ27
AJ36
AK10
AK13
AK14
AK16
AK22
AK28
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK40
AL11
AL14
AL17
AL19
AL24
AL27
AL30
AL36
AM11
AM14
AM17
AM21
AM23
AM25
AV39
AA6
AB5
AC1
AC6
AD5
AD8
AE3
AF1
AF5
AF6
AF7
AH2
AH3
AH5
AH8
AJ5
AK1
AK4
AK5
AK6
AK7
AK8
AK9
AL5
AM1
AM2
A4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_AK10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
CPU_SKT_H2
CPU_SKT_H2
REV = 4
REV = 4
9 OF 11
9 OF 11
?
?
4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
AM27
VSS
AM3
VSS
AM30
VSS
AM36
VSS
AM37
VSS
AM38
VSS
AM39
VSS
AM4
VSS
AM40
VSS
AM5
VSS
AN10
VSS
AN11
VSS
AN14
VSS
AN17
VSS
AN19
VSS
AN22
VSS
AN24
VSS
AN27
VSS
AN30
VSS
AN31
VSS
AN32
VSS
AN33
VSS
AN34
VSS
AN35
VSS
AN36
VSS
AN5
VSS
AN6
VSS
AN7
VSS
AN8
VSS
AN9
VSS
AP1
VSS
AP11
VSS
AP14
VSS
AP17
VSS
AP22
VSS
AP25
VSS
AP27
VSS
AP30
VSS
AP36
VSS
AP37
VSS
AP4
VSS
AP40
VSS
AP5
VSS
AR11
VSS
AR14
VSS
AR17
VSS
AR18
VSS
AR19
VSS
AR27
VSS
AR30
VSS
AR36
VSS
AR5
VSS
AT1
VSS
AT10
VSS
AT12
VSS
AT13
VSS
AT15
VSS
AT16
VSS
AT17
VSS
AT2
VSS
AT25
VSS
AT27
VSS
AT28
VSS
AT29
VSS
AT3
VSS
AT30
VSS
AT31
VSS
AT32
VSS
AT33
VSS
AT34
VSS
AT35
VSS
AT36
VSS
AT37
VSS
AT38
VSS
AT39
VSS
AT4
VSS
AT40
VSS
AT5
VSS
AT6
VSS
AT7
VSS
AT8
VSS
AT9
VSS
AU1
VSS
AU15
VSS
AU26
VSS
AU34
VSS
AU4
VSS
AU6
VSS
AU8
VSS
AV10
VSS
3
CPU_SKT_H2
AV11
AV14
AV17
AV35
AV38
AW10
AW11
AW14
AW16
AW36
AY11
AY14
AY18
AY35
AY37
U1K
U1K
VSS
VSS
VSS
AV3
VSS
VSS
VSS
AV6
VSS
VSS
VSS
VSS
VSS
VSS
AW6
VSS
VSS
VSS
VSS
VSS
AY4
VSS
AY6
VSS
AY8
VSS
B10
VSS
B13
VSS
B14
VSS
B17
VSS
B23
VSS
B26
VSS
B29
VSS
B32
VSS
B35
VSS
B38
VSS
B6
VSS
C11
VSS
C12
VSS
C17
VSS
C20
VSS
C23
VSS
C26
VSS
C29
VSS
C32
VSS
C35
VSS
C7
VSS
C8
VSS
D17
VSS
D2
VSS
D20
VSS
D23
VSS
D26
VSS
D29
VSS
D32
VSS
D37
VSS
D39
VSS
D4
VSS
D5
VSS
D9
VSS
E11
VSS
E12
VSS
E17
VSS
E20
VSS
E23
VSS
E26
VSS
E29
VSS
E32
VSS
E36
VSS
E7
VSS
E8
VSS
F1
VSS
F10
VSS
F13
VSS
F14
VSS
F17
VSS
F2
VSS
F20
VSS
F23
VSS
F26
VSS
F29
VSS
F35
VSS
F37
VSS
F39
VSS
F5
VSS
F6
VSS
F9
VSS
G11
VSS
G12
VSS
G17
VSS
G20
VSS
G23
VSS
G26
VSS
G29
VSS
G34
VSS
G7
VSS
VSS_NCTF
B3
VSS_NCTF
CPU_SKT_H2
G8
VSS
H1
VSS
H17
VSS
H2
VSS
H20
VSS
H23
VSS
H26
VSS
H29
VSS
H33
VSS
H35
VSS
H37
VSS
H39
VSS
H5
VSS
H6
VSS
H9
VSS
J11
VSS
J17
VSS
J20
VSS
J23
VSS
J26
VSS
J29
VSS
J32
VSS
K1
VSS
K12
VSS
K13
VSS
K14
VSS
K17
VSS
K2
VSS
K20
VSS
K23
VSS
K26
VSS
K29
VSS
K33
VSS
K35
VSS
K37
VSS
K39
VSS
K5
VSS
K6
VSS
L10
VSS
L17
VSS
L20
VSS
L23
VSS
L26
VSS
L29
VSS
L8
VSS
M1
VSS
M17
VSS
M2
VSS
M20
VSS
M23
VSS
M26
VSS
M29
VSS
M33
VSS
M35
VSS
M37
VSS
M39
VSS
M5
VSS
M6
VSS
M9
VSS
N8
VSS
P1
VSS
P2
VSS
P36
VSS
P38
VSS
P40
VSS
P5
VSS
P6
VSS
R33
VSS
R35
VSS
R37
VSS
R39
VSS
R8
VSS
T1
VSS
T5
VSS
T6
VSS
U8
VSS
V1
VSS
V2
VSS
V33
VSS
V34
VSS
V35
VSS
V36
VSS
V37
VSS
V38
VSS
V39
VSS
V40
VSS
V5
VSS
W6
VSS
Y5
VSS
Y8
VSS
2
U1_1
U1_1
PT44A11-6401
PT44A11-6401
?
?
SKT_H2
SKT_H2
U1J
U1J
REV = 4
REV = 4
BALLMAP_REV = 1.6
BALLMAP_REV = 1.6
AB7
RSVD1
AD37
RSVD2
AG4
RSVD3
AJ29
RSVD4
AJ30
RSVD5
AJ31
RSVD6
AV34
RSVD7
AW34
RSVD8
P35
RSVD9
P37
RSVD10
P39
RSVD11
R34
RSVD12
R36
RSVD13
R38
RSVD14
R40
RSVD15
A38
NCTF1
AU40
NCTF2
AW38
NCTF3
C2
NCTF4
D1
NCTF5
SPARES
SPARES
10 OF 11
10 OF 11
CPU_SKT_H2
CPU_SKT_H2
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
1
AT11
AP20
AN20
AU10
AY10
AF4
AB6
AE6
AJ11
D38
C39
C38
J34
N34
?
?
A A
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
CPU6-GND
CPU6-GND
CPU6-GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
13 48Tuesday, April 24, 2012
13 48Tuesday, April 24, 2012
13 48Tuesday, April 24, 2012
1.1C
1.1C
1.1C
of
of
of
5
CHANNEL A DIMM 1
SMB ADDRESS:000
D D
D3_ODT_A1 10
D3_ODT_A0 10
D3_DQS_A_DP0
195
167
68
79
53
ODT177ODT0
RSVD
NC/PAR_IN
NC/TEST4
NC/ERR_OUT
CB<0>39CB<1>40CB<2>45CB<3>46CB<4>
7
158
159
164
165
CB<5>
CB<6>
CB<7>
4
D3_DQS_A_DP[7..0] 10
D3_DQS_A_DN[7..0] 10
D3_DM_A3
D3_DM_A2
D3_DM_A1
D3_DM_A0
D3_DQS_A_DN3
D3_DQS_A_DP3
D3_DQS_A_DP2
D3_DQS_A_DN2
D3_DQS_A_DN1
D3_DQS_A_DP1
D3_DQS_A_DN0
16
15
6
DQS<1>
DQS<0>
DQS*<0>
D3_DQS_A_DP4
D3_DQS_A_DN4
85
34
25
84
33
24
DQS<4>
DQS<3>
DQS<2>
DQS*<4>
DQS*<3>
DQS*<2>
DQS*<1>
D3_DQS_A_DN7
D3_DQS_A_DP7
D3_DQS_A_DP6
D3_DQS_A_DN6
D3_DQS_A_DN5
D3_DQS_A_DP5
94
93
DQS<5>
43
112
103
111
102
DQS<7>
DQS<6>
DQS*<6>
DQS*<5>
134
126
125
135
42
DQS9*
DQS<8>
DQS*<8>
DQS*<7>
DM0/DQS9
DM1/DQS10
D3_DM_A4
203
152
143
204
153
144
DQS12*
DQS11*
DQS10*
DM4/DQS13
DM3/DQS12
DM2/DQS11
3
D3_DATA_A26
D3_DATA_A25
D3_DATA_A24
D3_DATA_A23
D3_DATA_A22
D3_DATA_A21
D3_DATA_A20
D3_DATA_A19
D3_DATA_A18
D3_DATA_A17
D3_DATA_A16
D3_DATA_A15
D3_DATA_A14
D3_DATA_A13
D3_DATA_A12
D3_DATA_A11
D3_DATA_A10
D3_DATA_A9
D3_DATA_A8
D3_DATA_A7
D3_DATA_A6
D3_DATA_A5
D3_DATA_A4
D3_DATA_A3
D3_DATA_A2
D3_DATA_A1
D3_DATA_A0
D3_DM_A7
D3_DM_A6
D3_DM_A5
122
123
128
129
161
230
221
212
231
162
222
213
DQ<0>3DQ<1>4DQ<2>9DQ<3>10DQ<4>
DQS17*
DQS15*
DQS14*
DQS13*
NC/DQS16*
DM8/DQS17
DM7/DQS16
DM6/DQS15
DM5/DQS14
DDRIII
DDRIII
13
131
132
137
138
140
141
146
147
DQ<5>
DQ<6>
DQ<7>
DQ<8>12DQ<9>
DQ<10>18DQ<11>19DQ<12>
DQ<13>
DQ<14>
DQ<15>
DQ<16>21DQ<17>22DQ<18>27DQ<19>28DQ<20>
DQ<21>
DQ<22>
DQ<23>
DQ<24>30DQ<25>31DQ<26>36DQ<27>37DQ<28>
D3_DATA_A31
D3_DATA_A30
D3_DATA_A29
D3_DATA_A28
D3_DATA_A27
149
150
155
156
DQ<29>
DQ<30>
2
D3_DATA_A35
D3_DATA_A34
D3_DATA_A33
D3_DATA_A32
DQ<31>
DQ<32>81DQ<33>82DQ<34>87DQ<35>88DQ<36>
D3_DATA_A39
D3_DATA_A38
D3_DATA_A37
D3_DATA_A36
D3_DATA_A40
200
201
206
207
DQ<37>
DQ<38>
DQ<39>
D3_DATA_A44
D3_DATA_A43
D3_DATA_A42
D3_DATA_A41
209
DQ<40>90DQ<41>91DQ<42>96DQ<43>97DQ<44>
D3_DATA_A49
D3_DATA_A48
D3_DATA_A47
D3_DATA_A46
D3_DATA_A45
210
215
216
100
DQ<45>
DQ<46>
DQ<47>
DQ<48>99DQ<49>
D3_DATA_A53
D3_DATA_A52
D3_DATA_A51
D3_DATA_A50
105
106
218
219
DQ<50>
DQ<51>
DQ<52>
DQ<53>
D3_DATA_A58
D3_DATA_A57
D3_DATA_A56
D3_DATA_A55
D3_DATA_A54
224
225
108
109
114
DQ<54>
DQ<55>
DQ<56>
DQ<57>
D3_DATA_A62
D3_DATA_A61
D3_DATA_A60
D3_DATA_A59
115
227
228
233
DQ<58>
DQ<59>
DQ<60>
DQ<61>
D3_DATA_A63
234
DIMM1
DIMM1
DDR III
DDR III
DQ<62>
DQ<63>
1
D3_DATA_A[63..0] 10
BLUE
C C
FREE1
FREE2
198
187
FREE349FREE4
48
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VTT
VTT
239
235
232
229
226
223
220
217
214
211
208
205
202
199
166
163
160
157
154
151
148
145
142
139
136
133
130
127
124
120
240
121
VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ
119
116
113
110
107
104
101
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD
197
194
191
189
186
183
182
179
176
173
170
VREFDQ1SCL
SDA
SA1
SA0
BA071BA1
CKE050CKE1
S0*
S1*76CK1/NU*64CK1/NU63CK0*
CK0
A261A3
A459A558A6
A756A9
A10/AP70A1155A12
A13
A14
A15
VREFCA
67
236
118
BA2
52
238
237
117
190
169
193
185
184A0188A1181
A8
180
178
175
177
CAS*74RAS*
WE*
RESET*
174
73
196
172
171
192
168
V_SM_VTT
CLOSE TO DIMM POWER PIN
V_SM
C550
C535
C535
C536
C536
C537
1.0uF
1.0uF
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
B B
V_SM V_SM
R512 1K +/-1%
R512 1K +/-1%
*
*
C534
C534
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
A A
16V, X7R, +/-10%
Dummy
Dummy
5
V_SM_VTT
C533
C533
*
*
10uF
10uF
D3_CA_VREF_A
C532
R501
R501
1K
1K
+/-1%
+/-1%
C532
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
*
*
C537
1.0uF
1.0uF
1.0uF
1.0uF
*
*
*
*
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
Dummy
Dummy
C606
C606
*
*
0.1uF
0.1uF
C545
C545
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
C538
C538
1.0uF
1.0uF
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
C550
C539
C539
0.1uF
0.1uF
0.1uF
0.1uF
*
*
*
*
Dummy
Dummy
PLACE BETWEEN DIMM1 AND
CPU
*
*
V_SM
EC47
EC47
820uF
820uF
+/-20%
+/-20%
EC59
EC59
820uF
820uF
*
*
+/-20%
+/-20%
Dummy
Dummy
DIMM_DQ_CPU_VREF_A11
R499 1K +/-1%
R499 1K +/-1%
*
*
C563
C563
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
PLACE RESISTORS CLOSE TO CH_A DIMMS
ON DIMM_VREF_A
4
V_SM
SMB_CLK_MAIN15,17,21,38,46
SMB_DATA_MAIN15,17,21,38,46
D3_SBS_A[2..0]10
D3_SCKE_A110
D3_SCKE_A010
D3_SCS_A_#110
D3_SCS_A_#010
D3_CK_DDR_A_DN110
D3_CK_DDR_A_DP110
D3_CK_DDR_A_DN010
D3_CK_DDR_A_DP010
D3_MAA_A[15..0]10
C543
*
*
R509
R509
1K
1K
+/-1%
+/-1%
C543
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
3
D3_CA_VREF_A
D3_DQ_VREF_A
D3_SBS_A2
D3_SBS_A1
D3_SBS_A0
D3_MAA_A0
D3_MAA_A1
D3_MAA_A2
D3_MAA_A3
D3_MAA_A4
D3_MAA_A5
D3_MAA_A6
D3_MAA_A7
D3_MAA_A8
D3_MAA_A9
D3_MAA_A10
D3_MAA_A11
D3_MAA_A12
D3_MAA_A13
D3_MAA_A14
D3_MAA_A15
D3_DQ_VREF_A
3D3V_SYS
C530
C530
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
DDR3-1:CHA
DDR3-1:CHA
DDR3-1:CHA
D3_WE_A# 10
D3_RAS_A# 10
D3_CAS_A# 10
D3_DRAMRST# 10,15
FOXCONN PCEG
FOXCONN PCEG
FOXCONN PCEG
H61A01
H61A01
H61A01
1
1.1C
1.1C
1.1C
of
of
of
14 48Tuesday, April 24, 2012
14 48Tuesday, April 24, 2012
14 48Tuesday, April 24, 2012
5
CHANNEL B DIMM 3
D D
SMB ADDRESS:010
D3_ODT_B1 11
D3_ODT_B0 11
195
167
68
79
53
ODT177ODT0
RSVD
NC/PAR_IN
NC/TEST4
NC/ERR_OUT
CB<0>39CB<1>40CB<2>45CB<3>46CB<4>
D3_DQS_B_DP0
D3_DQS_B_DN0
7
158
159
164
165
6
CB<5>
CB<6>
CB<7>
DQS<0>
DQS*<0>
4
D3_DQS_B_DP[7..0] 11
D3_DQS_B_DN[7..0] 11
D3_DM_B5
D3_DM_B4
D3_DM_B3
D3_DM_B2
D3_DM_B1
D3_DM_B0
D3_DQS_B_DN3
D3_DQS_B_DP3
D3_DQS_B_DP2
D3_DQS_B_DN2
D3_DQS_B_DN1
D3_DQS_B_DP1
16
15
DQS<1>
D3_DQS_B_DP4
D3_DQS_B_DN4
85
34
25
84
33
24
DQS<4>
DQS<3>
DQS<2>
DQS*<4>
DQS*<3>
DQS*<2>
DQS*<1>
D3_DQS_B_DN7
D3_DQS_B_DP7
D3_DQS_B_DP6
D3_DQS_B_DN6
D3_DQS_B_DN5
D3_DQS_B_DP5
94
93
DQS<5>
43
112
103
42
111
102
DQS<8>
DQS<7>
DQS<6>
DQS*<7>
DQS*<6>
DQS*<5>
143
134
126
125
144
135
DQS9*
DQS10*
DQS*<8>
DM0/DQS9
DM2/DQS11
DM1/DQS10
212
203
152
204
153
DQS13*
DQS12*
DQS11*
DM4/DQS13
DM3/DQS12
3
D3_DATA_B28
D3_DATA_B27
D3_DATA_B26
D3_DATA_B25
D3_DATA_B24
D3_DATA_B23
D3_DATA_B22
D3_DATA_B21
D3_DATA_B20
D3_DATA_B19
D3_DATA_B18
D3_DATA_B17
D3_DATA_B16
D3_DATA_B15
D3_DATA_B14
D3_DATA_B13
D3_DATA_B12
D3_DATA_B11
D3_DATA_B10
D3_DATA_B9
D3_DATA_B8
D3_DATA_B7
D3_DATA_B6
D3_DATA_B5
D3_DATA_B4
D3_DATA_B3
D3_DATA_B2
D3_DATA_B1
D3_DATA_B0
D3_DM_B7
D3_DM_B6
122
123
128
129
161
230
221
231
162
222
213
DQ<0>3DQ<1>4DQ<2>9DQ<3>10DQ<4>
DQS17*
DQS15*
DQS14*
NC/DQS16*
DM8/DQS17
DM7/DQS16
DM6/DQS15
DM5/DQS14
DDRIII
DDRIII
13
131
132
137
138
140
141
146
147
149
DQ<5>
DQ<6>
DQ<7>
DQ<8>12DQ<9>
DQ<10>18DQ<11>19DQ<12>
DQ<13>
DQ<14>
DQ<15>
DQ<16>21DQ<17>22DQ<18>27DQ<19>28DQ<20>
DQ<21>
DQ<22>
DQ<23>
DQ<24>30DQ<25>31DQ<26>36DQ<27>37DQ<28>
D3_DATA_B33
D3_DATA_B32
D3_DATA_B31
D3_DATA_B30
D3_DATA_B29
150
155
156
DQ<29>
DQ<30>
DQ<31>
DQ<32>81DQ<33>82DQ<34>87DQ<35>88DQ<36>
2
D3_DATA_B38
D3_DATA_B37
D3_DATA_B36
D3_DATA_B35
D3_DATA_B34
200
201
206
DQ<37>
D3_DATA_B39
D3_DATA_B42
D3_DATA_B41
D3_DATA_B40
207
DQ<38>
DQ<39>
DQ<40>90DQ<41>91DQ<42>96DQ<43>97DQ<44>
D3_DATA_B47
D3_DATA_B46
D3_DATA_B45
D3_DATA_B44
D3_DATA_B43
209
210
215
216
DQ<45>
DQ<46>
D3_DATA_B51
D3_DATA_B50
D3_DATA_B49
D3_DATA_B48
100
105
106
DQ<47>
DQ<48>99DQ<49>
DQ<50>
D3_DATA_B55
D3_DATA_B54
D3_DATA_B53
D3_DATA_B52
218
219
224
225
DQ<51>
DQ<52>
DQ<53>
DQ<54>
D3_DATA_B59
D3_DATA_B58
D3_DATA_B57
D3_DATA_B56
108
109
114
115
DQ<55>
DQ<56>
DQ<57>
DQ<58>
D3_DATA_B63
D3_DATA_B62
D3_DATA_B61
D3_DATA_B60
227
228
233
234
DQ<59>
DQ<60>
DQ<61>
DQ<62>
DIMM2
DIMM2
DDR III
DDR III
DQ<63>
1
D3_DATA_B[63..0] 11
White
C C
FREE1
FREE2
198
187
V_SM_VTT
CLOSE TO DIMM POWER PIN
V_SM
*
*
V_SM_VTT
C546
C546
*
*
10uF
V_SM
C607
C607
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
5
10uF
R646 1K +/-1%
R646 1K +/-1%
B B
A A
C589
C589
1.0uF
1.0uF
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
FREE349FREE4
48
*
*
VTT
240
*
*
Dummy
Dummy
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VTT
239
235
232
229
226
223
220
217
214
211
208
205
202
199
166
163
160
157
154
151
148
145
142
139
136
133
130
127
124
120
C593
C592
C592
0.1uF
0.1uF
*
*
*
*
C593
1.0uF
1.0uF
C559
C559
*
*
0.1uF
0.1uF
Dummy
Dummy
R645
R645
1K
1K
+/-1%
+/-1%
C603
C603
C587
C587
1.0uF
1.0uF
0.1uF
0.1uF
*
*
*
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
Dummy
Dummy
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
Dummy
Dummy
D3_CA_VREF_B
C601
C601
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
C594
C594
0.1uF
0.1uF
C595
C595
1.0uF
1.0uF
*
*
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%
C588
C588
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
C596
C596
0.1uF
0.1uF
*
*
Dummy
Dummy
121
4
VSS98VSS95VSS92VSS89VSS86VSS83VSS80VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS2VDDQ
119
116
113
110
107
104
101
DIMM_DQ_CPU_VREF_B11
V_SM
C562
C562
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
PLACE RESISTORS CLOSE TO CH_B DIMMS
ON DIMM_VREF_B
R506 1K +/-1%
R506 1K +/-1%
*
*
V_SM
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD78VDD75VDD72VDD69VDD66VDD65VDD62VDD60VDD57VDD54VDD51VDDSPD
197
194
191
189
186
183
182
179
176
173
170
3D3V_SYS
D3_CA_VREF_B
SMB_CLK_MAIN14,17,21,38,46
SMB_DATA_MAIN14,17,21,38,46
D3_SBS_B[2..0]11
D3_SCKE_B111
D3_SCKE_B011
D3_SCS_B_#111
D3_SCS_B_#011
D3_CK_DDR_B_DN111
D3_CK_DDR_B_DP111
D3_CK_DDR_B_DN011
D3_CK_DDR_B_DP011
D3_MAA_B[15..0]11
*
*
R496
R496
1K
1K
+/-1%
+/-1%
3
D3_DQ_VREF_B
D3_SBS_B2
D3_SBS_B1
D3_SBS_B0
D3_MAA_B0
D3_MAA_B1
D3_MAA_B2
D3_MAA_B3
D3_MAA_B4
D3_MAA_B5
D3_MAA_B6
D3_MAA_B7
D3_MAA_B8
D3_MAA_B9
D3_MAA_B10
D3_MAA_B11
D3_MAA_B12
D3_MAA_B13
D3_MAA_B14
D3_MAA_B15
D3_DQ_VREF_B
C531
C531
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
Dummy
Dummy
236
C542
C542
0.1uF
0.1uF
*
*
16V, X7R, +/-10%
16V, X7R, +/-10%
VREFDQ1SCL
SDA
SA1
SA0
BA071BA1
CKE050CKE1
S0*
S1*76CK1/NU*64CK1/NU63CK0*
CK0
A261A3
A459A558A6
A756A9
A10/AP70A1155A12
A13
A14
A15
VREFCA
67
BA2
52
118
238
237
117
190
169
193
185
184A0188A1181
3D3V_SYS
2
A8
180
178
175
177
CAS*74RAS*
WE*
RESET*
174
73
196
172
171
192
168
D3_WE_B# 11
D3_RAS_B# 11
D3_CAS_B# 11
D3_DRAMRST# 10,14
FOXCONN PCEG
FOXCONN PCEG
Title
Title
Title
DDR3-2:CHB
DDR3-2:CHB
DDR3-2:CHB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
FOXCONN PCEG
H61A01
H61A01
H61A01
1
1.1
1.1
1.1
of
of
of
15 48Tuesday, April 24, 2012
15 48Tuesday, April 24, 2012
15 48Tuesday, April 24, 2012
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