Foxconn G33M, G33M03 Schematics

5

D D

4

3

2

1

Foxconn G33M (G33M03)

C C

Page Index

01. Index Page

02. Clock Distribution

03. Power Delivery Map

04. CK505 ClockGen

05. VRD ISL6312

B B

06. LGA775 -1

07. LGA775 -2

08. Bearlake -GMCH -1

09. Bearlake -GMCH -2

10. Bearlake -GMCH -3

11. Bearlake -GMCH -4

12. DDR2 Channel A DIMM1,2

13. DDR2 Channel A Termination

14. DDR2 Channel B DIMM1,2

15. DDR2 Channel B Termination

A A

16. ACPI FOX ONE

17.PCI Express x16 Gfx Slot

18. VGA Connector

19. ICH9-1

5

4

20. ICH9-2

21. ICH9-3

22. ICH9-4

23. HDA Codec ALC888/883

24. Super I/O IT8718FX

25. PCI Express x1 Slot

26. PCI Slot

27. CPU/System Fan

28. Power/MISC Connectors

29. RTL8100C/8110S

30. LAN/USB Connectors

31. Parallel Port & KB/MS

32. Front USB Connector

33. FLASH/TPM

34. JMB368 & IDE

35. IEEE 1394 - V6308

36. History

37. GPIO / IRQ / IDSEL Map

3

FOXCONN PCEG

FOXCONN PCEG

Title

Title

Title

Index Page

Index Page

Index Page

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

FOXCONN PCEG

G33M03

G33M03

G33M03

1

137Thursday, April 26, 2007

137Thursday, April 26, 2007

137Thursday, April 26, 2007

CC

CC

CC

of

of

of

5

14.318MHz

4

3

2

1

CPU

D D

CPU 200/266/333 MHz Diff Pair

MCH 200/266/333 MHz Diff Pair

DDR2 4 Slots 12 Diff CLKs

PCI Express 100 MHz Diff Pair

DOT 96 MHz Diff Pair

PCI Express x16 Gfx

GMCH

Bearlake

Channel A DDR2

DIMM1

DIMM2

Channel B DDR2

DIMM1

C C

CK-505

PCI Express/DMI 100 MHz Diff Pair

DIMM2

PCI Express/DMI 100 MHz Diff Pair

USB/SIO 48 MHz

ICH 33 MHz

REF 14 MHz

DDR2 667/800

DDR2 667/800

ICH9

Azalia Bit Clock

B B

PCI 33 MHz

80 Port 33MHz

PCI Slot 1,2

80 Port

TPM 33 MHz

LAN 25 MHz

SIO 33 MHz

TPM 1.2

LAN

NINEVEH

32.768KHz

HD Audio

Super I/O

SATA 100 MHz Diff Pair

PCI Express 100 Mhz Diff Pair

A A

PCI Express 100 Mhz Diff Pair

XDP 100MHz Diff Pair

5

4

3

PCI Express x1 Slot 1

PCI Express x1 Slot 2

XDP

2

FOXCONN PCEG

FOXCONN PCEG

Title

Title

Title

CLOCK Distribution

CLOCK Distribution

CLOCK Distribution

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

FOXCONN PCEG

G33M03

G33M03

G33M03

1

237Thursday, April 26, 2007

237Thursday, April 26, 2007

237Thursday, April 26, 2007

of

of

of

CC

CC

CC

5

4

3

2

1

3.3V

ATX P/S

5V

D D

DDR2 Channel A

Vdd (Core)=1.8V
Ivdd(Max)=4.7A(per channel)

Vtt (Core)

0.9V
Ivterm(Max)=200mA
(per channel)

DDR2 Channel B

Vdd (Core)=1.8V
Ivdd(Max)=4.7A(per channel)

Vtt (Core)

0.9V
Ivterm(Max)=200mA
(per channel)

C C

5VDUAL
Icc(Max)=

4.345A(S0,S1)
22mA(S3)

Single Phase Switch
5V to 1.8V
Ivdd(Max)=14A
Ivdd(Max)=650mA(S3)
LDO

1.8V to 0.9V
Ivterm(Max)=1.2A

5VSB

12V

3.3V

VRD 11
Switching
3 Phase

Linear 1.8V
to 1.2V
6A

GMCH 1.25 V

21.34A
Switching

Proceessor

Vccp (CPU Vcore)
Voltage=1.15~1.5V
Icc(Max)=70A
3-Phases Swithing

1.2V FSB
Vtt=5.3A

Bearlake GMCH

FSB_Vtt

1.2V FSB Vtt
Icc(Max)=1.3A

1.8V VCCSM

1.8V VCC_SMCLK

Vcore (Core Logic)

1.25V
Icc(Max)=13.8A(Integrated)

*1.25V (DMI&PCIe)
VCCA_EXP 2.47A

1.25V
VCC_CL 4.3A

3.3V VCCA_DAC 66mA

3.3V VCC3_3 15.8mA

Super I/O

3.3V
Icc(Max)=50mA

3.3SBV
Icc(Max)=50mA(S0)

3.3SBV
Icc(Max)=38mA(S3)

USB2.0 12 Ports

+5V DUAL=5A(S0, S1)
+5V DUAL=20mA(S3)

PS2

+5V DUAL=345mA(S0, S1)
+5V DUAL=2mA(S3)

PCI Express X16
slot (1)

+12V=5.5A

3.3VSB
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)

+3.3V=3A

PCI Express X1

5V

5VSB

5VDUAL
Icc(Max)=

4.345A(S0,S1)
22mA(S3)

12V

Per slot (2)

HDA Codec

Vcc
5V
Icc(Max)=200mA

Vcc

3.3V
Icc(Max)=40mA

B B

LDO
12V
to 5V

5VSB

3.3V

Linear 1.25V
to 1.05V
V_1P05V_ICH
2A

Linear 1.8V
to 1.5V
V_1P5V_ICH

2.2A

RTC
Battery

5V_STBY to 3.3SB

1.5A

ICH9

1.25V VCCDMI 41mA

1.2V VCC_CPU_IO 14mA

1.05V (Core) VCC1_05

1.43A

1.5V (USB &SATA) VCC1_5A

1.652A

1.5V (PCIe)VCC1_5B

0.646A

1.5V VCCGLAN1_5
80mA

RTC=5uA

3.3V VccCL3_3 19mA

3.3V VccSUS3_3 212mA

3.3V VccLAN (10/100) 19mA

3.3V VccSUSHDA 32mA

3.3V VCC3_3 308mA

3.3V VccGLAN3_3 1mA

3.3V VccHDA 32mA

5V

+12V=0.5A

3.3VSB
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)

+3.3V=3A

PCI Slot

-12V
Icc(Max)=0.1A

5V
Icc(Max)=5A

3.3V
Icc(Max)=7.6A

12V
Icc(Max)=0.5A

3.3VSB
Icc(Max)=0.375A(wake)
Icc(Max)=0.02A(no wake)

-12V

Nineveh GbE Lan

A A

3.3V STBY
IO LED 15.5mA

1.8V ANALOG 418.2mA

1.0V Internal 1.8
to 1.0 VR core

277.2mA

5

BJT

CK505

Vdd (Core)

3.3V
Ivdd(Max)=250mA

4

3

2

Title

Title

Title

Power Delivery Map

Power Delivery Map

Power Delivery Map

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

FOXCONN PCEG

FOXCONN PCEG

FOXCONN PCEG

G33M03

G33M03

G33M03

1

337Thursday, April 26, 2007

337Thursday, April 26, 2007

337Thursday, April 26, 2007

CC

CC

CC

of

of

of

5

3D3V_SB

FB19

FB19

3D3V_CLK

*

*

FB 100 Ohm

FB 100 Ohm

*

*

D D

C C

PCI-E x1 (Slot1)

PCI-E JMicron 368

C172

C172

10uF

10uF

12

12

C194

C194

C178

C178

*

*

*

*

0.1uF

0.1uF

0.1uF

0.1uF

12

12

12

C195

C195

C205

C205

C206

C206

*

*

*

*

*

*

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

Please close to each power pin

CK_96M_P_GMCH8
CK_96M_N_GMCH8

CK_SATA_100M_P_ICH20
CK_SATA_100M_N_ICH20

CK_PWRGD19
CK_PE_100M_P_1PORT25
CK_PE_100M_N_1PORT25

*

*

CK_33M_ICH21
CK_33M_SIO24
CK_33M_TPM33

CK_33M_LAN29

CK_48M_ICH19
CK_24M_SIO24

12

C173

C173

0.1uF

0.1uF

near pin3

12

C198

C198

*

*

4.7uF

4.7uF

CK_33M_FWH33

3D3V_CLK

12

12

12

C175

C175

C174

C174

C191

C191

*

*

*

*

*

*

4.7uF

4.7uF

0.1uF

0.1uF

0.1uF

0.1uF

R131 22 +/-5%

R131 22 +/-5%

R139 22 +/-5%R139 22 +/-5%
R132 22 +/-5%R132 22 +/-5%
R129 33 +/-5%@TFR129 33 +/-5%@TF
R138 22 +/-5%R138 22 +/-5%

R143 33 +/-5%R143 33 +/-5%
R144 33 +/-5%R144 33 +/-5%

R146 0 +/-5%R146 0 +/-5%
R148 0 +/-5%R148 0 +/-5%

R163 0 +/-5%R163 0 +/-5%
R164 0 +/-5%R164 0 +/-5%

4

3D3V_SB

GSEL Pin
Hi: pin9&pin10 selects DOT 96Mhz
Low:pin9&pin10 selects PCIEX0.

R121 4.7K +/-5%R121 4.7K +/-5%

CK_14M_ICH19

CK_33M_PCI126
CK_33M_139435

@TF

@TF

R1580+/-5% R1580+/-5%
R1600+/-5% R1600+/-5%

CK_33M_PCI226

ICS_FSBSEL1

ICS_FSBSEL0
SEL24_48

96M_P_GMCH
96M_N_GMCH

SATA_100M_P_ICH
SATA_100M_N_ICH

PE_100M_P_1PORT
PE_100M_N_1PORT

3D3V_CLK

R13633+/-5% R13633+/-5%

CLK_TURBO1
CLK_TURBO2

R135 33+/-5%R135 33+/-5%
R134 33+/-5% @6308R134 33+/-5% @6308
R133 33+/-5%R133 33+/-5%

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

33M_PCI1
33M_PCI2

ICS_FSBSEL2

73

U14

U14

GND

FSLB/PCICLK4_2X
VDDPCI
PCICLK5_2X
PCICLK6_2X
VDD48
FSLA/USB_48
*SEL24_48#/24_48Mhz
GND
DOT96T_LR/PCIeT_LR10
DOT96C_LR/PCIeC_LR10
GND
SATACLKT_LR
SATACLKC_LR
VDDSATA
GND
Vtt_PwrGd/PD#/WOL_STOP#
PCIeT_LR0
PCIeC_LR0

3D3V_CLK

3

64

68

65

69

71

66

72

70

GND

DOC_1**67DOC_0**

REF0/GSEL*

PCICLK0_2X

PCICLK2_2X

FSLC/PCICLK3_2X

**SEL_STOP/PCICLK1_2X

ICS9LPRS919

ICS9LPRS919

GND19PCIeT_LR120PCIeC_LR121VDD22PCIeT_LR223PCIeC_LR224GND25VDD26PCIeT_LR327PCIeC_LR3

62

X163X2

GND

28

3D3V_CLK_REF_A

61

58

59

60

57

56

GND

SCLK

SDATA

VDDREF

CPUT_L0***

PCIeT_LR8/CPU_STOP#*

PCIeC_LR8/PCI_STOP#*

29

55

VDDCPU

CPUT_L1F

CPUC_L0***

CPUC_L1F

RESET_IN#/RESET#

**RLATCH

24.576Mhz

PCIeT_LR9

PCIeC_LR9

PCIeT_LR7

PCIeC_LR736PCIeT_LR635PCIeC_LR634PCIeT_LR533PCIeC_LR532GND31PCIeC_LR430PCIeT_LR4

ICS9LPRS919AKLF-T

ICS9LPRS919AKLF-T

GNDA
VDDA

GND

25Mhz

VDD
VDD
GND

GND

*

*

Place near Clock generator

200M_P_CPU
200M_N_CPU

3D3V_CLK

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

X2

X2

*

*

XTAL-14.318MHz

XTAL-14.318MHz

C169

C169

12

33pF

33pF

CP6 COPPERCP6 COPPER

200M_P_GMCH
200M_N_GMCH

FP_RSTJ 6,19,28

SLP_S4J 16,19

24M_1394
3D3V_CLK_REF_A

25M_LAN

2

C168

C168

12

33pF

33pF

*

*

12

CP7 COPPERCP7 COPPER

3D3V_CLK

12

R13033+/-5% R13033+/-5%
R13733+/-5% R13733+/-5%

R140 33+/-5%R140 33+/-5%
R142 33+/-5%R142 33+/-5%

SMB_DATA_MAIN 27,33
SMB_CLK_MAIN 27,33

CK_200M_P_CPU 6
CK_200M_N_CPU 6

R14533+/-5% @6308R14533+/-5% @6308

R15133+/-5% R15133+/-5%

CK_200M_P_GMCH 8
CK_200M_N_GMCH 8

CK_24M_1394 35

CLK_25M_LAN 29

1

PCI-E x16 Slot

SEL24_48

High: 24 MHZ
Low: 48 MHz

R147 4.7K

R147 4.7K
R150 4.7K

R150 4.7K

dummy

dummy

+/-5%

+/-5%
+/-5%

+/-5%

3D3V_SB

PE_100M_P_GMCH
PE_100M_N_GMCH
PE_100M_N_ICH
PE_100M_P_ICH

PE_100M_N_JMB
PE_100M_P_JMB
PE_100M_N_16PORT
PE_100M_P_16PORT

RN15 0 +/-5%

RN15 0 +/-5%

*

*

1

2

3

4

5

6

7 8

RN13 0 +/-5%

RN13 0 +/-5%

*

*

1

2

3

4

5

6

7 8

CK_PE_100M_P_GMCH 8
CK_PE_100M_N_GMCH 8
CK_DMI_N_ICH 19
CK_DMI_P_ICH 19

CK_PE_100M_N_JMB 34

CK_PE_100M_P_JMB 34
CK_PE_100M_N_16PORT 17
CK_PE_100M_P_16PORT 17

B B

*

*

C163

C163

12

10pF

10pF

dummy

dummy

CLK_TURBO2

R116

R116

4.7K

4.7K

+/-5%

+/-5%

*

*

*internal pull-up resistor
**internal pull-down resistor
RESET pin is 3.3V tolerant

SMBus Address :1101-0010

CLK_25M_LAN
CK_24M_SIO
CK_48M_ICH
CK_33M_1394
CK_33M_PCI1
CK_33M_SIO
CK_33M_ICH
CK_33M_FWH

CK_14M_ICH
CK_33M_PCI2

C156

C156

12

10pF

10pF

dummy

dummy

12

*

*

CK_24M_1394

C182

C182

10pF

10pF

dummy

dummy

3

FSB_VTT

R166 470

R166 470

R162 470

R162 470

R161 470

R161 470

BSEL TABLE

00
0

FS_AFS_BFS_C

1
010

+/-5%

+/-5%

+/-5%

+/-5%

+/-5%

+/-5%

FSB Frequency
133MHz(533)
200MHz(800)

0
0

266MHz(1066)
333MHz(1333)100

CLK_TURBO1

R117

R117

4.7K

4.7K

+/-5%

+/-5%

C186

C186

12

10pF

A A

10pF

*

*

*

*

dummy

dummy

C177

C177

C180

C180

12

3.3pF

3.3pF

10pF

10pF

*

*

*

*

50V, NPO, +/-0.25pF

50V, NPO, +/-0.25pF

dummy

dummy

Add for SI

C162

C162

C167

C167

12

12

10pF

10pF

10pF

10pF

*

*

*

*

dummy

dummy

dummy

dummy

C161

C161

C165

C165

12

10pF

10pF

*

*

dummy

dummy

C160

C160

12

12

10pF

10pF

10pF

10pF

*

*

dummy

dummy

dummy

dummy

EMI CAPS.

5

4

3D3V_SB 3D3V_CLK_REF_A

FB18

FB18

*

*

FB 100 Ohm

FB 100 Ohm

FSBSEL0

FSBSEL1

FSBSEL2

FSBSEL0 6,8

FSBSEL1 6,8

FSBSEL2 6,8

12

C170

C170

*

*

0.1uF

0.1uF

2

Close to pin 48, 61

12

C184

C184

*

*

0.1uF

0.1uF

ICS_FSBSEL0

ICS_FSBSEL1

ICS_FSBSEL2

R165 2.2K

R165 2.2K

R169 2.2K

R169 2.2K

R159 2.2K

R159 2.2K

Title

Title

Title

CK505 ClockGen

CK505 ClockGen

CK505 ClockGen

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+/-5%

+/-5%

+/-5%

+/-5%

+/-5%

+/-5%

FSBSEL0 6,8

FSBSEL1 6,8

FSBSEL2 6,8

FOXCONN PCEG

FOXCONN PCEG

FOXCONN PCEG

G33M03

G33M03

G33M03

1

of

of

of

437Thursday, April 26, 2007

437Thursday, April 26, 2007

437Thursday, April 26, 2007

AC

AC

AC

5

12V_VRM

2

4

5

1

3

PWR2

PWR2
HM3502E-P1

HM3502E-P1

pwr4nwp1h128

+/-1%

+/-1%

R292

R292
680

680

+/-5%

+/-5%

r0603h6

r0603h6

R248

R248
100

100

+/-1%

+/-1%

r0603h6

r0603h6

R259

R259

39.2K

39.2K

+/-1%

+/-1%

r0603h6

r0603h6

dummy

dummy

pwr4nwp1h128

R281 20K

R281 20K

C322 22pF

C322 22pF

C0603

C0603

R266 0

R266 0

r0603h6

r0603h6

1 2

C336 680pF

C336 680pF

*

*

VCCP

R237

R237
100

100

+/-1%

+/-1%

r0603h6

r0603h6

C308

C308

0.1uF

0.1uF

*

*

C0603

C0603

dummy

dummy

R268

R268

*

*

0

0

*

*

+/-5%

+/-5%

r0603h6

r0603h6

*

*

C0603

C0603

12

+/-1%r0603h6

+/-1%r0603h6

*

*

R267 51

R267 51

C320

C320

10nF

10nF

C0603

C0603

C321 1.5nF

C321 1.5nF

1 2

IDROOP

1 2

*

*

*

*

D D

VTT_OUT_RIGHT

VR_READY

C281

C281

0.1uF

0.1uF

*

*

C0603

C0603

dummy

dummy

VR_READY19
VR_EN6,16

VIDO724
VIDO624
VIDO524
VIDO424
VIDO324
VIDO224
VIDO124

VIDO024

VID_SELECT6

Place
close to
inductor

C C

5V_SYS

B B

*

*

T

T

VCC_SENSE6

VSS_SENSE6

*

*

R256 1.15K

R256 1.15K

RT1

RT1

10K

10K

+/-1%

+/-1%

R249 487

R249 487

Close to PWM IC

R240 0

R240 0

r0603h6

r0603h6

R243 0

R243 0

r0603h6

r0603h6

R280 100K

+/-5%r0603h6

+/-5%r0603h6

R285 4.75K

R0603

R0603

R278 0 dummy

R278 0 dummy

*

*

R0603

R0603

R289

R289
681

681

+/-1%

+/-1%

*

*

dummyR280 100K

dummy
dummyR285 4.75K

dummy

+/-1%r0603h6

+/-1%r0603h6

C140

C140

12

1nF

1nF

*

*

50V, X7R, +/-10%

50V, X7R, +/-10%

C0603

C0603

dummy

dummy

U17 ISL6312CRZU17 ISL6312CRZ

37

PGOOD

36

EN

46

VID7

47

VID6

48

VID5

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

6

VRSEL

13

*

*

COMP

14

FB

15

IDROOP

+/-1%

+/-1%

16

VDIFF

IDROOP

R250

R250
20K

20K

+/-5%

+/-5%

r0603h6

r0603h6

dummy

dummy

18

VSEN

C309

C309

*

*

10nF

10nF

dummy

dummy

17

RGND

C315

C315

0.1uF

0.1uF

C0603

C0603

dummy

dummy

12

OFS

7

DRSEL

8

OVPSEL

11

REF

45

FS

9

SS

R242

R242

R279

R279

*

*

100K

100K

240K

240K

+/-1%

+/-1%

+/-5%

+/-5%

R0603

R0603

BOTTOM PAD
CONNECT TO GND
Through 8 VIAs

4

C132

C132

0.1uF

0.1uF

*

*

5V_SYS 12V_VRM

C318

C318

4.7uF

4.7uF

*

*

25V,Y5V,+80/-20%

25V,Y5V,+80/-20%

c0805h13

c0805h13

10

PVCC1_2

VCC

UGATE1
PHASE1
LGATE1

UGATE2
PHASE2
LGATE2

UGATE3
PHASE3
LGATE3

EN_PH4

GND

49

C0603

C0603

BOOT1

ISEN1+

ISEN1-

BOOT2

ISEN2+

ISEN2-

PVCC3

BOOT3

ISEN3+

ISEN3-

ISEN4+

ISEN4-

PWM4

29
31
32

33
30

R222 51+/-1%

R222 51+/-1%

35
34

27
26

25
28

R236 51+/-1%

R236 51+/-1%

19
20

42

*

*

40
39

38
41

R238 51+/-1%

R238 51+/-1%

44
43

PHASE3

R231 51+/-1%

R231 51+/-1%

21
22

24
23

*

*

R216

R216

2.2

2.2

r0805h6

r0805h6

12

L10 Choke 1.1uH

L10 Choke 1.1uH

*

*

C136

C136

10uF

10uF

-0.1

-0.1

C1206h18

C1206h18

dummy

dummy

C285

C285

12

1uF

1uF

*

*

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

C0805

C0805

r0603h6

r0603h6

PHASE1

r0603h6

r0603h6

PHASE2

C294

C294

1uF

1uF

C0805

C0805

r0603h6

r0603h6

r0603h6

r0603h6

PHASE4

PWM4

R219 0

R219 0

r0603h6

r0603h6

R215 2.2

R215 2.2

r0805h6

r0805h6

R213 6.2K

R213 6.2K

R223 2.2

R223 2.2

r0805h6

r0805h6

R230 6.2K

R230 6.2K

R228 2.2

R228 2.2

r0805h6

r0805h6

R217 2.2

R217 2.2

r0805h6

r0805h6

R232 6.2K

R232 6.2K

*

*

R221 6.2K

R221 6.2K

+/-5%

+/-5%

R218 15K

R218 15K

R225

R225

2.2K

2.2K

+/-5%

+/-5%

r0603h6

r0603h6

*

*

16V, +/-20%

16V, +/-20%

*

*

*

*

+/-1%R0603

+/-1%R0603

+/-1%R0603

+/-1%R0603

*

*

+/-1%R0603

+/-1%R0603

dummy

dummy

+/-5%r0603h6

+/-5%r0603h6

EC4

EC4

1500uF

1500uF

*

*

16V, +/-20%

16V, +/-20%

C284 0.1uF

C284 0.1uF

25V, X7R, +/-10%

25V, X7R, +/-10%

+/-1%R0603

+/-1%R0603

C283 0.1uF

C283 0.1uF

1 2

C289 0.1uF

C289 0.1uF

*

*

C302 0.1uF

C302 0.1uF

C286 0.1uF

C286 0.1uF

C304 0.1uF

C304 0.1uF

*

*

C0603

C0603

25V, X7R, +/-10%

25V, X7R, +/-10%

*

*

C295 0.1uF

C295 0.1uF

5V_SYS

12V_VRM

EC16

EC16

1500uF

1500uF

*

*

ISEN1

*

*
*

*

ISEN2

12V_VRM

25V, X7R, +/-10%C0603

25V, X7R, +/-10%C0603

*

*

ISEN3

ISEN4

*

*

16V, +/-20%

16V, +/-20%

*

*

C299

C299

0.1uF

0.1uF

*

*

C0603

C0603

C298

C298

0.1uF

0.1uF

*

*

C0603

C0603

C292

C292

0.1uF

0.1uF

*

*

C0603

C0603

EC5

EC5

EC6

EC6

1500uF

1500uF

1500uF

1500uF

*

*

16V, +/-20%

16V, +/-20%

R104 2.2

R104 2.2

r0805h6 +/-5%

r0805h6 +/-5%

R92 0

R92 0

r0805h6 +/-5%

r0805h6 +/-5%

C278

C278

0.1uF

0.1uF

C0603

C0603

R171 2.2

R171 2.2

r0805h6 +/-5%

r0805h6 +/-5%

R101 0

R101 0

r0805h6 +/-5%

r0805h6 +/-5%

R580

R580

*

*

160K

160K

+/-5%

+/-5%

3

R212 0

R212 0

r0805h6 +/-5%

r0805h6 +/-5%

R105 2.2

R105 2.2

r0805h6 +/-5%

r0805h6 +/-5%

R102

R102
10K

10K

+/-1%

+/-1%

R0603

R0603

R170

R170
10K

10K

+/-1%

+/-1%

R0603

R0603

R103

R103
10K

10K

+/-1%

+/-1%

R0603

R0603

2

VIN

C126

C126

0.1uF

0.1uF

*

*

C0603

C0603

dummy

dummy

VIN

DS

Q9

G

AOD452Q9AOD452

DS

Q4

G

G

AOD472Q4AOD472

VIN

DS

Q18

Q18

G

AOD452

AOD452

DS

Q20

Q20

G

G

AOD472

AOD472

VIN

DS

Q10

Q10

G

AOD452

AOD452

DS

Q5

G

G

AOD472Q5AOD472

DS

AOD472Q3AOD472

DS

DS

AOD472Q6AOD472

Q3

*

*

Q19

Q19

AOD472

AOD472

*

*

Q6

*

*

12

12

12

12

C95

C95

*

*

1uF

1uF

C0805

C0805

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

L12

L12

*

*

1 2

R113

R113

Choke 400nH

Choke 400nH

2.2

2.2

r0805h6

r0805h6

C149

C149

1nF

1nF

C0603

C0603

PHASE1
ISEN1

12

C128

C128

*

*

1uF

1uF

C0805

C0805

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

L21

L21

*

*

1 2

R174

R174

Choke 400nH

Choke 400nH

2.2

2.2

r0805h6

r0805h6

C212

C212

1nF

1nF

C0603

C0603

PHASE2
ISEN2

12

C202

C202

*

*

1uF

1uF

C0805

C0805

L13

L13

*

*

1 2

R114

R114

Choke 400nH

Choke 400nH

2.2

2.2

r0805h6

r0805h6

C152

C152

1nF

1nF

C0603

C0603

PHASE3
ISEN3

OS-CON

*

*

OS-CON

*

*

OS-CON

*

*

TC6

TC6

680uF

680uF

4V,+/-20%

4V,+/-20%

ce35d80h90

ce35d80h90

TC2

TC2

680uF

680uF

4V,+/-20%

4V,+/-20%

ce35d80h90

ce35d80h90

TC7

TC7

680uF

680uF

4V,+/-20%

4V,+/-20%

ce35d80h90

ce35d80h90

TC5

TC5

680uF

680uF

*

*

*

*

4V,+/-20%

4V,+/-20%

ce35d80h90

ce35d80h90

0.8V~1.6V/70A

TC1

TC1

680uF

680uF

*

*

4V,+/-20%

4V,+/-20%

ce35d80h90

ce35d80h90

TC8

TC8

680uF

680uF

*

*

*

*

4V,+/-20%

4V,+/-20%

ce35d80h90

ce35d80h90

TC4

TC4

680uF

680uF

4V,+/-20%

4V,+/-20%

ce35d80h90

ce35d80h90

dummy

dummy

TC9

TC9

680uF

680uF

4V,+/-20%

4V,+/-20%

ce35d80h90

ce35d80h90

dummy

dummy

*

*

TC3

TC3

680uF

680uF

4V,+/-20%

4V,+/-20%

ce35d80h90

ce35d80h90

VCCP

*

*

1

EC12

EC12

3300uF

3300uF

6.3V, +/-20%

6.3V, +/-20%

VCCP

*

*

EC13

EC13

3300uF

3300uF

6.3V, +/-20%

6.3V, +/-20%

*

*

EC14

EC14

3300uF

3300uF

6.3V, +/-20%

6.3V, +/-20%

12V_VRM

U12

PWM4

U12

7

PVCC

6

VCC

3

PWM

4

GND

ISL6612ACBZA-T

ISL6612ACBZA-T

BOOT
UGATE
PHASE
LGATE

R123 4.7

R123 4.7

+/-5%r0805h6

+/-5%r0805h6

C155 0.22uF

C155 0.22uF

1 2

16V, X7R, +/-10%C0805

16V, X7R, +/-10%C0805

*

*

A A

5

R112 2.2

R112 2.2

2

r0805h6 +/-5%

r0805h6 +/-5%

1
8
5

C139 0.1uF

C139 0.1uF

25V, X7R, +/-10%C0603

25V, X7R, +/-10%C0603

*

*

VIN

R107

R107
10K

10K

DS

+/-1%

+/-1%

Q7

R0603

R100 2.2

R100 2.2

r0805h6 +/-5%

r0805h6 +/-5%

R124 0

R124 0

r0805h6 +/-5%

r0805h6 +/-5%

4

R0603

3

G

AOD452Q7AOD452

DS

DS

Q14

Q14

G

G

AOD472

AOD472

AOD472

AOD472

12

C124

C124

*

*

1uF

1uF

C0805

C0805

L11

L11

*

*

1 2

R106

R106

Choke 400nH

Choke 400nH

2.2

2.2

Q11

Q11

r0805h6

r0805h6

12

C130

C130

*

*

1nF

1nF

C0603

C0603

PHASE4
ISEN4

Title

Title

Title

VRD ISL6312

VRD ISL6312

VRD ISL6312

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

FOXCONN PCEG

FOXCONN PCEG

FOXCONN PCEG

G33M03

G33M03

G33M03

1

537Thursday, April 26, 2007

537Thursday, April 26, 2007

537Thursday, April 26, 2007

CC

CC

CC

of

of

of

5

HDJ[63..0]

2 OF 7

2 OF 7

U15B

HDJ0
HDJ1
HDJ2
HDJ3
HDJ4

D D

C C

B B

A A

*

*

HDJ5
HDJ6
HDJ7
HDJ8
HDJ9
HDJ10
HDJ11
HDJ12
HDJ13
HDJ14
HDJ15

HDBIJ08
HDSTBNJ08
HDSTBPJ08

HDJ16
HDJ17
HDJ18
HDJ19
HDJ20
HDJ21
HDJ22
HDJ23
HDJ24
HDJ25
HDJ26
HDJ27
HDJ28
HDJ29
HDJ30
HDJ31

HDBIJ18
HDSTBNJ18
HDSTBPJ18

VTT_OUT_LEFT

C187

C187

1uF

1uF

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

C0603

C0603

HDBIJ0

HDBIJ1 HDBIJ3

R316 62R316 62

R356 100

R356 100

R306 49.9 +/-1%dummyR306 49.9 +/-1%dummy
R307 49.9 +/-1%

R307 49.9 +/-1%

R303 49.9 +/-1%R303 49.9 +/-1%
R315 49.9 +/-1%R315 49.9 +/-1%

R207 49.9 +/-1%R207 49.9 +/-1%
R336 49.9 +/-1%R336 49.9 +/-1%

U15B

B4

D00#

C5

D01#

A4

D02#

C6

D03#

A5

D04#

B6

D05#

B7

D06#

A7

D07#

A10

D08#

A11

D09#

B10

D10#

C11

D11#

D8

D12#

B12

D13#

C12

D14#

D11

D15#

A8

DBI0#

C8

DSTBN0#

B9

DSTBP0#

G9

D16#

F8

D17#

F9

D18#

E9

D19#

D7

D20#

E10

D21#

D10

D22#

F11

D23#

F12

D24#

D13

D25#

E13

D26#

G13

D27#

F14

D28#

G14

D29#

F15

D30#

G15

D31#

G11

DBI1#

G12

DSTBN1#

E12

DSTBP1#

Place at CPU end of route

Place at CPU end of route

dummy

dummy

RN20

RN20

51

51

*

*

1

2

3

4

5

6

7 8

8p4r0603h7

8p4r0603h7

RN22

RN22

51

51

*

*

1

2

3

4

5

6

7 8

8p4r0603h7

8p4r0603h7

dummy

dummy

10 mils width
7 mils spacing to low speed signals
14mils spacing to high speed signals
max. 1200mils

10 mils width
7 mils spacing to low speed signals
14mils spacing to high speed signals
max. 1200mils

R154

R154
100

100

+/-1%

+/-1%

R153

R153
200 Ohm

200 Ohm

+/-1%

+/-1%

5

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#

DBI2#
DSTBN2#
DSTBP2#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DBI3#
DSTBN3#
DSTBP3#

CPU_Conroe_Rev1.0_LGA775

CPU_Conroe_Rev1.0_LGA775

cpu_lga775

cpu_lga775

HBR0J

CPU_PWRG

TESTHI_13

+/-5%

+/-5%

TESTHI_10
TESTHI_11

TESTHI_9

+/-5%

+/-5%

TESTHI_8
TESTHI_12

HCOMP4
HCOMP5

10 mils width
7 mils spacing to low speed signals
14mils spacing to high speed signals
max. 1200mils

HCOMP2
HCOMP3

HCOMP0
HCOMP1

R155 10R155 10

C188

C188

12

220pF

220pF

*

*

50V, X7R, +/-10%

50V, X7R, +/-10%

C0603

C0603

dummy

dummy

G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D19
G20
G19

D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
C20
A16
C17

HDJ32
HDJ33
HDJ34
HDJ35
HDJ36
HDJ37
HDJ38
HDJ39
HDJ40
HDJ41
HDJ42
HDJ43
HDJ44
HDJ45
HDJ46
HDJ47

HDBIJ2

HDJ48
HDJ49
HDJ50
HDJ51
HDJ52
HDJ53
HDJ54
HDJ55
HDJ56
HDJ57
HDJ58
HDJ59
HDJ60
HDJ61
HDJ62
HDJ63

VTT_OUT_RIGHT

VTT_OUT_RIGHT

C366

C366

12

0.1uF

0.1uF

*

*

C0603

C0603

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C365

C365

*

*

1uF

1uF

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

C0603

C0603

HDBIJ2 8
HDSTBNJ2 8
HDSTBPJ2 8

HDBIJ3 8
HDSTBNJ3 8
HDSTBPJ3 8

VTT_OUT_RIGHT

R322 62R322 62

VTT_OUT_RIGHT

R345 62R345 62

Place at CPU end of route

FSB_VTT

VTT_OUT_LEFT

VTT_OUT_RIGHT

place TRSTJ termination anywhere on route
place TCK/TDI/TMS terminations near CPU within 1.5 inch

VTT_OUT_LEFTFSB_VTT

HCPURSTJ

R338 130

R0603 +/-1%

R0603 +/-1%

R340 130

R0603 +/-1%

R0603 +/-1%

R156 51R156 51

R157 51R157 51

R308 51R308 51

R339 62

R339 62

dummy

dummy

R324 62R324 62
R323 62R323 62
R325 62R325 62

R311 62R311 62
R577 62

R577 62

R333

R333
100

100

+/-1%

+/-1%

R318

R318
200 Ohm

200 Ohm

+/-1%

+/-1%

4

HDJ[63..0] 8

HAJ[35..3]

HAJ[35..3]8

4 mils width, 10 mils spacing

HIERRJ

FORCEPHJ

dummyR338 130

dummy

PROCHOTJ

dummyR340 130

dummy

TESTHI_0

TESTHI_2_7

TESTHI_1

HTDO
HTDI
HTMS
HTRSTJ

HTCK
HTRSTJ

dummy

dummy

R317 10R317 10

4

CPU_GTLREF2CPU_GTLREF3

C354

C354

12

220pF

220pF

*

*

50V, X7R, +/-10%

50V, X7R, +/-10%

C0603

C0603

dummy

dummy

3

HAJ[35..3]

HAJ[35..3]8

U15A

HAJ3
HAJ4
HAJ5
HAJ6
HAJ7
HAJ8

HAJ9
HAJ10
HAJ11
HAJ12
HAJ13
HAJ14
HAJ15
HAJ16

HREQJ[4..0]8

HAJ17
HAJ18
HAJ19
HAJ20
HAJ21
HAJ22
HAJ23
HAJ24
HAJ25
HAJ26
HAJ27
HAJ28
HAJ29
HAJ30
HAJ31
HAJ32
HAJ33
HAJ34
HAJ35

HADSTBJ18

VTT_OUT_RIGHT

C362

C362

*

*

1uF

1uF

C0603

C0603

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

VTT_OUT_RIGHT

*

*

C361

C361

*

*

1uF

1uF

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

C0603

C0603

HREQJ0
HREQJ1
HREQJ2
HREQJ3
HREQJ4

HADSTBJ08
PECI20,24

GTLREF voltage should be 0.67*VTT
12 mils width, 15 mils spacing

R335

R335

divider should be within 1.5" of the GTLREF pin

100

100

0.22nF caps should be placed near CPU pin

+/-1%

+/-1%

place series resistor as close to divider

R305 10

R305 10

R320

R320
200 Ohm

200 Ohm

+/-1%

+/-1%

R326 51R326 51
R349 51R349 51
RN19

RN19

51

+/-5%

51

+/-5%

1

2

3

4

5

6

7 8

8p4r0603h7

8p4r0603h7

Place BPM termination near CPU

VTT_OUT_RIGHT

R334

R334
100

100

+/-1%

+/-1%

R319

R319
200 Ohm

200 Ohm

+/-1%

+/-1%

U15A

L5

A03#

P6

A04#

M5

A05#

L4

A06#

M4

A07#

R4

A08#

T5

A09#

U6

A10#

T4

A11#

U5

A12#

U4

A13#

V5

A14#

V4

A15#

W5

A16#

N4

RSVD1

P5

RSVD2

K4

REQ0#

J5

REQ1#

M6

REQ2#

K6

REQ3#

J6

REQ4#

R6

ADSTB0#

G5

PCREQ#

AB6

A17#

W6

A18#

Y6

A19#

Y4

A20#

AA4

A21#

AD6

A22#

AA5

A23#

AB5

A24#

AC5

A25#

AB4

A26#

AF5

A27#

AF4

A28#

AG6

A29#

AG4

A30#

AG5

A31#

AH4

A32#

AH5

A33#

AJ5

A34#

AJ6

A35#

AC4

RSVD3

AE4

RSVD4

AD5

ADSTB1#

CPU_Conroe_Rev1.0_LGA775

CPU_Conroe_Rev1.0_LGA775

cpu_lga775

cpu_lga775

+/-5%r0603h6

+/-5%r0603h6

C356

C356

12

220pF

220pF

*

*

50V, X7R, +/-10%

50V, X7R, +/-10%

C0603

C0603

dummy

dummy

HBPM5J
HBPM4J
HBPM3J
HBPM2J
HBPM0J
HBPM1J

GTLREF voltage should be 0.67*VTT
12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin

0.22nF caps should be placed near CPU pin
place series resistor as close to divider

R304 10

R304 10

3

D2

ADS#

C2

BNR#

D4

HIT#

RSP#

BPRI#
DBSY#
DRDY#

HITM#

IERR#

INIT#
LOCK#
TRDY#

BINIT#
DEFER#
EDRDY#

MCERR#

AP0#
AP1#

BR0#
TESTHI08
TESTHI09
TESTHI10

DP0#

DP1#

DP2#

DP3#
GTLREF1

GTLREF0

CS_GTLREF

FC15

RESET#

RS0#

RS1#

RS2#

1 OF 7

1 OF 7

HGTLREF_1

If not used, pull up through 51 to 1k ohm
to vtt_out_right or ground respectively,i.e
reserved the termination circuit

R350 0

R350 0
R348 0

R348 0
R332 0

R332 0
R351 0

R351 0

reserve for Kentsfield CPU support

+/-5%r0603h6

+/-5%r0603h6

C355

C355

12

220pF

220pF

*

*

50V, X7R, +/-10%

50V, X7R, +/-10%

C0603

C0603

dummy

dummy

TP_RSPJ

H4
G8
B2
C1
E4

HIERRJ

AB2
P3
C3
E3

TP_BINITJ

AD3
G7

CPU_GTLREF2

F2

TP_MCERRJ

AB3

TP_APJ0

U2

TP_APJ1

U3

HBR0J

F3

TESTHI_8

G3

TESTHI_9

G4

TESTHI_10

H5

TP_DPJ0

J16

TP_DPJ1

H15

TP_DPJ2

H16

TP_DPJ3

J17

HGTLREF_1

H2

HGTLREF_0

H1
E24
H29

G23
B3

F5
A3

TESTHI_8

+/-5%r0603h6

+/-5%r0603h6

TESTHI_9

+/-5%r0603h6

+/-5%r0603h6
+/-5%r0603h6

+/-5%r0603h6

H_TEST

+/-5%r0603h6

+/-5%r0603h6

HGTLREF_0

HADSJ 8

HBNRJ 8

HITJ 8

TP12TP12

HBPRIJ 8

HDBSYJ 8
HDRDYJ 8
HITMJ 8

INITJ 20
HLOCKJ 8
HTRDYJ 8

TP11TP11

HDEFERJ 8

TP13TP13
TP20TP20

TP21TP21

HBR0J 8

TP8TP8
TP6TP6
TP4TP4
TP1TP1

HCPURSTJ 8

HRSJ0 8
HRSJ1 8
HRSJ2 8

THERMDA/THERMDC

1. width=10 mils, spacing=10 mils.

2. route the lines in parallel

FP_RSTJ4,19,28

FSBSEL04,8
FSBSEL14,8
FSBSEL24,8

VTT_OUT_LEFT VTT_OUT_LEFT

R35251R352
51

TP_CPU_G1

VTT_OUT_RIGHT

2

VID_SELECT5

CK_200M_P_CPU4
CK_200M_N_CPU4

VCC_SENSE5
VSS_SENSE5

1D5V_ICH

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

placed near pin D23, within 500 mils

HTCK

AE1

HTDI

AD1

HTDO

AF1

HTMS

AC1

HTRSTJ

AG1

HBPM0J

AJ2

HBPM1J

AJ1

HBPM2J

AD2

HBPM3J

AG2

HBPM4J

AF2

HBPM5J

FSBSEL0
FSBSEL1
FSBSEL2

AG3
AC2
AK3

AJ3

G29
H30
G30

R34451R344
51

RN21

RN21

*

*

1
3
5
7 8

680

680

RN18

RN18

*

*

1
3
5
7 8

680

680

2

FP_RSTJ

SMIJ20
A20MJ20
FERRJ20
INTR20

NMI20
IGNNEJ20
STPCLKJ20

HVCCA7

HVSSA7

HVCCIOPLL7

VID024
VID124
VID224
VID324
VID424
VID524
VID624
VID724

THERMDA24
THERMDC24

dummy

dummy

R239 0 r0603h6+/-5%

R239 0 r0603h6+/-5%
R234 0 r0603h6+/-5%

R234 0 r0603h6+/-5%

dummy

dummy

HVCCPLL

C420

C420

10uF

10uF

C0805

C0805

12

12

*

*

*

*

U15D

U15D

4 OF 7

4 OF 7

TCK
TDI
TDO
TMS
TRST#

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#

DBR#
ITPCLKOUT0

ITPCLKOUT1
BSEL0

BSEL1
BSEL2

VTTPWRGD

VTT_OUT1
VTT_OUT2

VTT_SEL

CPU_Conroe_Rev1.0_LGA775

CPU_Conroe_Rev1.0_LGA775

cpu_lga775

cpu_lga775

MS_ID0

MS_ID1

For CPU before Conroe

2
4
6

2
4
6

HVCCPLL

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7

C478

C478

10nF

10nF

50V, X7R, +/-10%

50V, X7R, +/-10%

C0603

C0603

A29

VTT1

B25

VTT2

B29

VTT3

B30

VTT4

C29

VTT5

A26

VTT6

B27

VTT7

C28

VTT8

A25

VTT9

A28

VTT10

A27

VTT11

C30

VTT12

A30

VTT13

C25

VTT14

C26

VTT15

C27

VTT16

B26

VTT17

D27

VTT18

D28

VTT19

D25

VTT20

D26

VTT21

B28

VTT22

D29

VTT23

D30

VTT24

AM6
AA1

J1
F27

R32851R328
51

VID3
VID2
VID1
VID0

VID7
VID6
VID5
VID4

1

3 OF 7

3 OF 7

U15C

U15C

P2

SMI#

K3

A20M#

R3

FERR#/PBE#

K1

LINT0

L1

LINT1

N2

IGNNE#

M3

STPCLK#

A23

VCCA

B23

VSSA

D23

RSVD5

C23

VCCIOPLL

AM2

VID0

AL5

VID1

AM3

VID2

AL6

VID3

AK4

VID4

AL4

VID5

AM5

FC11

AM7

FC12

AN7

FC16

F28

BCLK0

G28

BCLK1

AE8

SKTOCC#

AL1

THERMDA

AK1

THERMDC

AN3

VCCSENSE

AN4

VSSSENSE

AN5

VCC_MB_REG

AN6

VSS_MB_REG

Changed pin name

Changed pin name
from RSV

from RSV

F29

RSVD9

AL3

VRDSEL

CPU_Conroe_Rev1.0_LGA775

CPU_Conroe_Rev1.0_LGA775

cpu_lga775

cpu_lga775

TESTHI00
TESTHI01
TESTHI11
TESTHI12
TESTHI02
TESTHI03
TESTHI04
TESTHI05
TESTHI06
TESTHI07

FORCEPH

TESTHI13

PWRGOOD
PROCHOT#

THERMTRIP#

BOOTSELECT

PROCHOTJ

RSVD11

RSVD12

COMP0
COMP1
COMP2
COMP3
COMP4
COMP5

RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD21
RSVD24

MSID1
MSID0

FC27
FC26

LL_ID0
LL_ID1

FC23

TESTHI_0

F26

TESTHI_1

W3

TESTHI_11

P1

TESTHI_12

W2
F25
G25
G27
G26
G24
F24

FORCEPHJ

AK6
G6

TESTHI_13

L2
AH2
N1

PROCHOTJ

AL2
M2

HCOMP0

A13

HCOMP1

T1

HCOMP2

G2

HCOMP3

R1

HCOMP4

J2

HCOMP5

T2
N5

AE6

H_TEST

C9

CPU_GTLREF3

G10
D16
A20
E23
F23
J3

V1
W1

TP_CPU_G1

G1
E29

CPU_BOOT

Y1

TP_CPU_V2

V2

TP_CPU_AA2

AA2
A24

R353 0

R353 0

r0603h6 +/-5%

r0603h6 +/-5%

dummy

dummy

TESTHI_2_7

CPU_PWRG 19
THERMTRIPJ 20

When terminated,
it must use +-1% resistor

MS_ID1

Stuff it will only support

MS_ID0

Conroe and future processor

R152

R152
1K

1K

-0.05

-0.05

dummy

dummy

ICH_THRM_UP 19,24

Stuff to enable Thermal event

FSB_VTT

VTT_OUT_RIGHT

R214 1KR214 1K

VTT_OUT_RIGHT

R358

R358
680

680

dummy

dummy

Q24

Q24
MMBT3904_NL

MMBT3904_NL

VTT_OUT_LEFT

VTT_SEL VTT
No Connect 1.2V

1.2V 1.2V
Vss 1.1V

C375

C375

12

0.1uF

0.1uF

*

*

16V, Y5V, +80%/-20%

16V, Y5V, +80%/-20%

dummy

dummy

VTT_OUT_RIGHT
VTT_OUT_LEFT

VTT_SEL

R343

R343

0 dummy

0 dummy

R342

R342

0 dummy

0 dummy

R32751R327
51

VTT_SEL 16

VTT_OUT_RIGHT

R357

R357
1K

1K

dummy

dummy

B

E C

stuff for only support 65W CPU

FOXCONN PCEG

FOXCONN PCEG

Title

Title

Title

LGA775 -1

LGA775 -1

LGA775 -1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

FOXCONN PCEG

G33M03

G33M03

G33M03

1

TESTHI_12 7

TP18TP18
TP16TP16

VR_EN 5,16

VR_EN 5,16

of

of

of

637Thursday, April 26, 2007

637Thursday, April 26, 2007

637Thursday, April 26, 2007

R309

R309
51

51

dummy

dummy

CC

CC

CC

5

4

3

2

1

FSB_VTT

U15E

U15E

5 OF 7

AG22

K29

AM26

AL8

AE12

D D

C C

B B

AE11

AL18

AC25

AN14
AD28

AC29

AC27
AM18
AM19

AC26

AF15
AE14

AC24
AC23

AN26
AN25
AN11
AN18

AD24
AE23
AE22
AN19

AE21
AM30
AE19
AC30
AE15

AN21
AC28
AE18
AD25

AD26

AJ26

AM29

AJ12

AD27

AG29
AM22

AK18

AH28
AH21

W23
W24
W25

T25
Y28

W30

Y30

Y26

M29

U24
J23

AB8

J8
J28
T30

AM9
AC8

N23

W29

U29

Y23

Y27
Y25

V8

K8

M30

K27

M24

T8
N25

W26

M8

N30

M25
M26

L8
U25

Y8

U23

M23

N27
U28

K28

U8

AD8

K24

5 OF 7

VCCP1

VCCP93

VCCP2

VCCP94

VCCP3

VCCP95

VCCP4

VCCP96

VCCP5

VCCP97

VCCP6

VCCP98

VCCP7

VCCP99

VCCP8

VCCP100

VCCP9

VCCP101

VCCP10

VCCP102

VCCP11

VCCP103

VCCP12

VCCP104

VCCP13

VCCP105

VCCP14

VCCP106

VCCP15

VCCP107

VCCP16

VCCP108

VCCP17

VCCP109

VCCP18

VCCP110

VCCP19

VCCP111

VCCP20

VCCP112

VCCP21

VCCP113

VCCP22

VCCP114

VCCP23

VCCP115

VCCP24

VCCP116

VCCP25

VCCP117

VCCP26

VCCP118

VCCP27

VCCP119

VCCP28

VCCP120

VCCP29

VCCP121

VCCP30

VCCP122

VCCP31

VCCP123

VCCP32

VCCP124

VCCP33

VCCP125

VCCP34

VCCP126

VCCP35

VCCP127

VCCP36

VCCP128

VCCP37

VCCP129

VCCP38

VCCP130

VCCP39

VCCP131

VCCP40

VCCP132

VCCP41

VCCP133

VCCP42

VCCP134

VCCP43

VCCP135

VCCP44

VCCP136

VCCP45

VCCP137

VCCP46

VCCP138

VCCP47

VCCP139

VCCP48

VCCP140

VCCP49

VCCP141

VCCP50

VCCP142

VCCP51

VCCP143

VCCP52

VCCP144

VCCP53

VCCP145

VCCP54

VCCP146

VCCP55

VCCP147

VCCP56

VCCP148

VCCP57

VCCP149

VCCP58

VCCP150

VCCP59

VCCP151

VCCP60

VCCP152

VCCP61

VCCP153

VCCP62

VCCP154

VCCP63

VCCP155

VCCP64

VCCP156

VCCP65

VCCP157

VCCP66

VCCP158

VCCP67

VCCP159

VCCP68

VCCP160

VCCP69

VCCP161

VCCP70

VCCP162

VCCP71

VCCP163

VCCP72

VCCP164

VCCP73

VCCP165

VCCP74

VCCP166

VCCP75

VCCP167

VCCP76

VCCP168

VCCP77

VCCP169

VCCP78

VCCP170

VCCP79

VCCP171

VCCP80

VCCP172

VCCP81

VCCP173

VCCP82

VCCP174

VCCP83

VCCP175

VCCP84

VCCP176

VCCP85

VCCP177

VCCP86

VCCP178

VCCP87

VCCP179

VCCP88

VCCP180

cpu_lga775

cpu_lga775

VCCP89

VCCP181

VCCP90

VCCP182

VCCP91

VCCP183

VCCP92

VCCP184

CPU_Conroe_Rev1.0_LGA775

CPU_Conroe_Rev1.0_LGA775

AK12
AH22
T29
AM14
AM25
AE9
Y29
AK25
AK19
AG15
J22
T24
AG21
AM21
J25
U30
AL21
AG25
AJ18
J19
AH30
J15
AG12
AJ22
J20
AH18
AH26
W27
AL25
AN8
AH14
U27
T23
R8
AK22
AN29
AG11
AK26
J10
AJ15
AG26
AN9
AH15
AF18
AL15
J26
J18
J21
AG27
AK15
AF11
AD23
AM15
AF8
AK21
AG30
AJ21
AM11
AL11
AJ11
K30
AL14
AN30
AH25
AL12
AJ9
AK11
AG14
N29
AL30
AJ25
AH9
J29
J11
K25
P8
K23
AL19
AM8
T26
N28
AH12
AL22
AN15
AJ8
U26
AJ19
T27
AK8
AN12
AG9
N26

VCCPVCCP VCCP

U15F

U15F

AF9

VCCP185

AF22

VCCP186

AH11

VCCP187

AJ14

VCCP188

AH19

VCCP189

AH29

VCCP190

AH27

VCCP191

AG28

VCCP192

AL26

VCCP193

AM12

VCCP194

J24

VCCP195

J13

VCCP196

T28

VCCP197

W28

VCCP198

J12

VCCP199

J27

VCCP200

AG19

VCCP201

AL9

VCCP202

AD30

VCCP203

AF21

VCCP204

Y24

VCCP205

AK14

VCCP206

J9

VCCP207

M27

VCCP208

AF14

VCCP209

J30

VCCP210

AG18

VCCP211

AA8

VCCP212

AG8

VCCP213

AL29

VCCP214

AD29

VCCP215

W8

VCCP216

AH8

VCCP217

N24

VCCP218

AN22

VCCP219

J14

VCCP220

K26

VCCP221

AF19

VCCP222

N8

VCCP223

AF12

VCCP224

M28

VCCP225

AK9

VCCP226

C10

VSS1

D12

VSS2

C24

VSS4

K2

VSS5

C22

VSS6

AN1

VSS7

B14

VSS8

K7

VSS9

AE16

VSS10

B11

VSS11

AL10

VSS12

AK23

VSS13

H12

VSS14

AF7

VSS15

AK7

VSS16

H7

VSS17

E14

VSS18

L28

VSS19

Y5

VSS20

E11

VSS21

AL16

VSS22

AL24

VSS23

AK13

VSS24

D21

VSS26

AL20

VSS27

D18

VSS28

AN2

VSS29

AK16

VSS30

AK20

VSS31

AM27

VSS32

AM1

VSS33

AL13

VSS34

AL17

VSS35

C19

VSS36

E28

VSS37

AH7

VSS38

AK30

VSS39

D24

VSS40

CPU_Conroe_Rev1.0_LGA775

CPU_Conroe_Rev1.0_LGA775

cpu_lga775

cpu_lga775

VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104

VSS106
VSS107
VSS108
VSS109
VSS110
VSS111

VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125

6 OF 7

6 OF 7

AL23
A12
L25
J7
AE28
AE29
K5
J4
AE30
AN20
AF10
AE24
AM24
AN23
H9
H8
H13
AC6
AC7
AH6
C16
AM16
AE25
AE27
AJ28
AJ7
F19
AH13
AD7
AH16
AK17
E17
AH17
AH20
AE5
AH23
AE7
AM13
AH24
AJ30
AJ10
AF3
AK5
AJ16
AF6
AK29
AJ17
F22
AH3
AK10
AM10
F16
AJ23
F13
AG7
F10
L26
AD4
H11
L24
L23
AM23
A15
AH10

B24
L3
H27
A21
AE2
AJ29

AK27
AK28
B20
AM20
H26
B17
H25
H24
AA3
AA7
H23
AA6
H10

TESTHI_126

U15G

U15G

H22

VSS126

H21

VSS127

H20

VSS128

H19

VSS129

H18

VSS130

AB7

VSS131

H17

VSS132

AJ24

VSS133

AM17

VSS134

AC3

VSS135

H14

VSS136

P28

VSS137

V6

VSS138

AK2

VSS139

P27

VSS140

P26

VSS141

AM28

VSS142

AJ13

VSS143

W4

VSS144

P25

VSS145

AJ20

VSS146

W7

VSS147

P23

VSS148

AG13

VSS149

AG16

VSS150

AG17

VSS151

C7

VSS152

Y2

VSS153

L30

VSS154

L29

VSS155

D15

VSS156

AL27

VSS157

Y7

VSS158

L27

VSS159

AA29

VSS160

N6

VSS161

N7

VSS162

AA28

VSS163

AN13

VSS164

AA27

VSS165

AA26

VSS166

P4

VSS167

AA25

VSS168

AA24

VSS169

P7

VSS170

E26

VSS171

V30

VSS172

R2

VSS173

V29

VSS174

V28

VSS175

R5

VSS176

V27

VSS177

R7

VSS178

E20

VSS179

AN10

VSS180

V25

VSS181

T3

VSS182

V24

VSS183

V23

VSS184

T6

VSS185

AL7

VSS186

E25

VSS187

U1

VSS188

R29

VSS189

R28

VSS190

R27

VSS191

R26

VSS192

R25

VSS193

U7

VSS194

R24

VSS195

R23

VSS196

P30

VSS197

V3

VSS198

P29

VSS199

AF16

VSS200

AE10

VSS201

AF13

VSS202

H6

VSS203

A18

VSS204

A2

VSS205

E2

VSS206

D9

VSS207

C4

VSS208

A6

VSS209

D6

VSS210

CPU_Conroe_Rev1.0_LGA775

CPU_Conroe_Rev1.0_LGA775

cpu_lga775

cpu_lga775

7 OF 7

7 OF 7

VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219

VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249

VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261

VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276

RSVD26

COMP6
COMP7

RSVD31

COMP8
RSVD33
RSVD34
RSVD35
RSVD36

D5
A9
D3
B1
B5
B8
AJ4
AE26
AH1

V7
C13
AK24
AB30
L6
L7
AB29
M1
AB28
E8
AG20
AN17
AB27
AB26
AN16
M7
AB25
AB24
AB23
N3
AA30
F4
AG10
AE13
AF30
H28
F7
AF29
AF28

AF27
AF26
AF25
AN28
AN27
AF24
AF23
AG24
AF17
AN24
H3

P24
AE20
AE17
E27
T7
R30
AJ27
AB1
AM4
V26
AA23
AL28
AF20
AG23

F6
Y3

AE3
E7

B13
D14
E6
D1
E5

IMPSEL
HCOMP6

HCOMP7

HCOMP8

VCCP

*

*

HVCCIOPLL6

HVCCA6

HVSSA6

12

12

C247

C247

C243

C243

*

*

10uF

10uF

10uF

10uF

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

*

*

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

HVCCIOPLL

HVCCA

12

C254

C254

10uF

10uF

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

L0805 10uH

L0805 10uH

+/-20%

+/-20%

HVSSA

12

C258

C258

*

*

10uF

10uF

L15

L15

0805h14

0805h14

12

C263

C263

*

*

10uF

10uF

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

*

*

PLL Supply Filter

12

12

12

C197

C197

C196

C196

*

*

10uF

10uF

10uF

10uF

Place these caps. inside CPU socket
10uF/SP caps. co-layout

12

C269

C269

*

*

10uF

10uF

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

12

12

12

C255

C255

C248

C248

C244

C244

*

*

*

*

*

*

10uF

10uF

10uF

10uF

10uF

10uF

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

12

*

*

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

L14

L14
L0805 10uH

L0805 10uH

0805h14

0805h14
+/-20%

+/-20%

12

C259

C259

10uF

10uF

12

12

C270

C270

C264

C264

*

*

*

*

10uF

10uF

10uF

10uF

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

12

12

12

C256

C256

C245

C245

C249

C249

*

*

*

*

*

*

10uF

10uF

10uF

10uF

10uF

10uF

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

12

12

12

C271

C271

C265

C265

C260

C260

*

*

*

*

*

*

10uF

10uF

10uF

10uF

10uF

10uF

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

A A

5

4

VTT_OUT_RIGHT

R310 49.9 +/-1%dummyR310 49.9 +/-1%dummy
R312 49.9 +/-1%

R312 49.9 +/-1%

10 mils width
7 mils spacing to low speed signals
14mils spacing to high speed signals
max. 1200mils

dummy

dummy

HCOMP6
HCOMP7

3

R204 24.9 +/-1%R204 24.9 +/-1%

15 mils width
7 mils spacing to low speed signals
14mils spacing to high speed signals
max. 1200mils

HCOMP8

2

R302 51R302 51

IMPSEL

FOXCONN PCEG

FOXCONN PCEG

Title

Title

Title

LGA775 -2

LGA775 -2

LGA775 -2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

FOXCONN PCEG

G33M03

G33M03

G33M03

1

737Thursday, April 26, 2007

737Thursday, April 26, 2007

737Thursday, April 26, 2007

of

of

of

CC

CC

CC

5

U1MCH

HAJ[35..3]6

D D

HREQJ[4..0]6

HADSTBJ06
HADSTBJ16

HDSTBPJ06
HDSTBNJ06
HDBIJ06
HDSTBPJ16

FSB_VTT

HDSTBNJ16
HDBIJ16
HDSTBPJ26
HDSTBNJ26
HDBIJ26
HDSTBPJ36
HDSTBNJ36
HDBIJ36

HADSJ6
HTRDYJ6
HDRDYJ6
HDEFERJ6
HITMJ6
HITJ6
HLOCKJ6
HBR0J6
HBNRJ6
HBPRIJ6
HDBSYJ6
HRSJ06
HRSJ16
HRSJ26
HCPURSTJ6

R177

R177
301

301

+/-1%

+/-1%

R176

R176

100

100

+/-1%

+/-1%

r0603h6

r0603h6

C C

B B

A A

HAJ3

J42

HAJ4

L39

HAJ5

J40

HAJ6

L37

HAJ7

L36

HAJ8

K42

HAJ9

N32

HAJ10

N34

HAJ11

M38

HAJ12

N37

HAJ13

M36

HAJ14

R34

HAJ15

N35

HAJ16

N38

HAJ17

U37

HAJ18

N39

HAJ19

R37

HAJ20

P42

HAJ21

R39

HAJ22

V36

HAJ23

R38

HAJ24

U36

HAJ25

U33

HAJ26

R35

HAJ27

V33

HAJ28

V35

HAJ29

Y34

HAJ30

V42

HAJ31

V38

HAJ32

Y36

HAJ33

Y38

HAJ34

Y39

HAJ35

AA37

HREQJ0

F40

HREQJ1

L35

HREQJ2

L38

HREQJ3

G43

HREQJ4

J37

M34
U34

M42

HDBIJ0

HDBIJ1

HDBIJ2

HDBIJ3

Resistor and Capacitor
next to each other.

R190 51R190 51

C213

C213

12

0.1uF

0.1uF

*

*

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

HSWING voltage should be 0.25*FSB_VTT
10 mils width, 10 mils spacing
max. 3 inches long

M43
M40
G35
H33

J33
G27
H27
G29

B38
C38

E33
W40

Y40
W41

T43

Y43
U42

V41

AA42

W42
G39
U40
U41

AA41

U39
C31

HSWING

5

U16B

U16B

FSB_AB_3
FSB_AB_4
FSB_AB_5
FSB_AB_6
FSB_AB_7
FSB_AB_8
FSB_AB_9
FSB_AB_10
FSB_AB_11
FSB_AB_12
FSB_AB_13
FSB_AB_14
FSB_AB_15
FSB_AB_16
FSB_AB_17
FSB_AB_18
FSB_AB_19
FSB_AB_20
FSB_AB_21
FSB_AB_22
FSB_AB_23
FSB_AB_24
FSB_AB_25
FSB_AB_26
FSB_AB_27
FSB_AB_28
FSB_AB_29
FSB_AB_30
FSB_AB_31
FSB_AB_32
FSB_AB_33
FSB_AB_34
FSB_AB_35

FSB_REQB_0
FSB_REQB_1
FSB_REQB_2
FSB_REQB_3
FSB_REQB_4

FSB_ADSTBB_0
FSB_ADSTBB_1

FSB_DSTBPB_0
FSB_DSTBNB_0
FSB_DINVB_0
FSB_DSTBPB_1
FSB_DSTBNB_1
FSB_DINVB_1
FSB_DSTBPB_2
FSB_DSTBNB_2
FSB_DINVB_2
FSB_DSTBPB_3
FSB_DSTBNB_3
FSB_DINVB_3

FSB_ADSB
FSB_TRDYB
FSB_DRDYB
FSB_DEFERB
FSB_HITMB
FSB_HITB
FSB_LOCKB
FSB_BREQ0B
FSB_BNRB
FSB_BPRIB
FSB_DBSYB
FSB_RSB_0
FSB_RSB_1
FSB_RSB_2
FSB_CPURSTB

Bearlake G33

Bearlake G33

U1MCH

FSB_DB_0
FSB_DB_1
FSB_DB_2
FSB_DB_3
FSB_DB_4
FSB_DB_5
FSB_DB_6
FSB_DB_7
FSB_DB_8

FSB_DB_9
FSB_DB_10
FSB_DB_11
FSB_DB_12

FSB

FSB

FSB_DB_13
FSB_DB_14
FSB_DB_15
FSB_DB_16
FSB_DB_17
FSB_DB_18
FSB_DB_19
FSB_DB_20
FSB_DB_21
FSB_DB_22
FSB_DB_23
FSB_DB_24
FSB_DB_25
FSB_DB_26
FSB_DB_27
FSB_DB_28
FSB_DB_29
FSB_DB_30
FSB_DB_31
FSB_DB_32
FSB_DB_33
FSB_DB_34
FSB_DB_35
FSB_DB_36
FSB_DB_37
FSB_DB_38
FSB_DB_39
FSB_DB_40
FSB_DB_41
FSB_DB_42
FSB_DB_43
FSB_DB_44
FSB_DB_45
FSB_DB_46
FSB_DB_47
FSB_DB_48
FSB_DB_49
FSB_DB_50
FSB_DB_51
FSB_DB_52
FSB_DB_53
FSB_DB_54
FSB_DB_55
FSB_DB_56
FSB_DB_57
FSB_DB_58
FSB_DB_59
FSB_DB_60
FSB_DB_61
FSB_DB_62
FSB_DB_63

FSB_SWING

FSB_RCOMP

FSB_SCOMP

FSB_SCOMPB

FSB_DVREF

FSB_ACCVREF

HPL_CLKINP
HPL_CLKINN

1 OF 8

1 OF 8

FSB_VTT

4 mils width, 6 mils spacing in the breakout
4 mils width, 14 mils spacing after the breakout
max. 750 mils
routed on a single layer and matched within 50mils

HDJ0

R40

HDJ1

P41

HDJ2

R41

HDJ3

N40

HDJ4

R42

HDJ5

M39

HDJ6

N41

HDJ7

N42

HDJ8

L41

HDJ9

J39

HDJ10

L42

HDJ11

J41

HDJ12

K41

HDJ13

G40

HDJ14

F41

HDJ15

F42

HDJ16

C42

HDJ17

D41

HDJ18

F38

HDJ19

G37

HDJ20

E42

HDJ21

E39

HDJ22

E37

HDJ23

C39

HDJ24

B39

HDJ25

G33

HDJ26

A37

HDJ27

F33

HDJ28

E35

HDJ29

K32

HDJ30

H32

HDJ31

B34

HDJ32

J31

HDJ33

F32

HDJ34

M31

HDJ35

E31

HDJ36

K31

HDJ37

G31

HDJ38

K29

HDJ39

F31

HDJ40

J29

HDJ41

F29

HDJ42

L27

HDJ43

K27

HDJ44

H26

HDJ45

L26

HDJ46

J26

HDJ47

M26

HDJ48

C33

HDJ49

D35

HDJ50

E41

HDJ51

B41

HDJ52

D42

HDJ53

C40

HDJ54

C35

HDJ55

B40

HDJ56

D38

HDJ57

D37

HDJ58

B33

HDJ59

D33

HDJ60

C34

HDJ61

B35

HDJ62

A32

HDJ63

D32

HSWING

B25

HRCOMP

D23

HSCOMP

C25

HSCOMPJ

D25

MCH_GTLREF

D24
B24
R32
U32

COMP SIGNAL TERMINATION

R182 49.9

R182 49.9

+/-1%

+/-1%

R181 49.9

R181 49.9

+/-1%

+/-1%

HRCOMP

R194 16.5 +/-1%R194 16.5 +/-1%

10 mils width, 7 mils spacing
max. 500 mils
5 on 5 mils in breakout, max 250 mils

HDJ[63..0]

CK_200M_P_GMCH 4
CK_200M_N_GMCH 4

HSCOMPJ

C223

C223

12

2.7pF

2.7pF

*

*

50V, NPO, +/-0.25pF

50V, NPO, +/-0.25pF

C0603

C0603

dummy

dummy

HSCOMP

C222

C222

12

2.7pF

2.7pF

*

*

50V, NPO, +/-0.25pF

50V, NPO, +/-0.25pF

C0603

C0603

dummy

dummy

*

*

4

CK_PE_100M_P_GMCH4

CK_PE_100M_N_GMCH4

SDVO_CTRLDATA17
SDVO_CTRLCLK17

C208

C208

1uF

1uF

C0603

C0603

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

4

HDJ[63..0] 6

EXP_RXP017
EXP_RXN017
EXP_RXP117
EXP_RXN117
EXP_RXP217
EXP_RXN217
EXP_RXP317
EXP_RXN317
EXP_RXP417
EXP_RXN417
EXP_RXP517
EXP_RXN517
EXP_RXP617
EXP_RXN617
EXP_RXP717
EXP_RXN717
EXP_RXP817
EXP_RXN817
EXP_RXP917
EXP_RXN917
EXP_RXP1017
EXP_RXN1017
EXP_RXP1117
EXP_RXN1117
EXP_RXP1217
EXP_RXN1217
EXP_RXP1317
EXP_RXN1317
EXP_RXP1417
EXP_RXN1417
EXP_RXP1517
EXP_RXN1517

DMI_RXP019
DMI_RXN019
DMI_RXP119
DMI_RXN119
DMI_RXP219
DMI_RXN219
DMI_RXP319
DMI_RXN319

FSB_VTT

R173

R173
100

100

+/-1%

+/-1%

R172

R172
200 Ohm

200 Ohm

+/-1%

+/-1%

3

U1MCH

U16A

MCH_GTLREF

C221

C221

12

220pF

220pF

*

*

50V, X7R, +/-10%

50V, X7R, +/-10%

C0603

C0603

dummy

dummy

F13
E13
K15

J15

F12
E12

J12
H12

J11
H11

F7
E7
E5

F6
C2
D2
G6
G5

L9

L8
M8
M9
M4

L4
M5
M6
R9

R10

T4
R4
R6
R7

W2

V1

Y8

Y9

AA7
AA6
AB3
AA4

B12
B13

G17
E17

FSBSEL04,6

FSBSEL14,6

FSBSEL24,6

U16A

PEG_RXP_0
PEG_RXN_0
PEG_RXP_1
PEG_RXN_1
PEG_RXP_2
PEG_RXN_2
PEG_RXP_3
PEG_RXN_3
PEG_RXP_4
PEG_RXN_4
PEG_RXP_5
PEG_RXN_5
PEG_RXP_6
PEG_RXN_6
PEG_RXP_7
PEG_RXN_7
PEG_RXP_8
PEG_RXN_8
PEG_RXP_9
PEG_RXN_9
PEG_RXP_10
PEG_RXN_10
PEG_RXP_11
PEG_RXN_11
PEG_RXP_12
PEG_RXN_12
PEG_RXP_13
PEG_RXN_13
PEG_RXP_14
PEG_RXN_14
PEG_RXP_15
PEG_RXN_15

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_RXP_2
DMI_RXN_2
DMI_RXP_3
DMI_RXN_3

EXP_CLKINP
EXP_CLKINN

SDVO_CTRLDATA
SDVO_CTRLCLK

Bearlake G33

Bearlake G33

EXP_RXP0
EXP_RXN0
EXP_RXP1
EXP_RXN1
EXP_RXP2
EXP_RXN2
EXP_RXP3
EXP_RXN3
EXP_RXP4
EXP_RXN4
EXP_RXP5
EXP_RXN5
EXP_RXP6
EXP_RXN6 EXP_TXN6
EXP_RXP7
EXP_RXN7
EXP_RXP8
EXP_RXN8
EXP_RXP9
EXP_RXN9
EXP_RXP10
EXP_RXN10
EXP_RXP11
EXP_RXN11
EXP_RXP12
EXP_RXN12
EXP_RXP13
EXP_RXN13
EXP_RXP14
EXP_RXN14
EXP_RXP15
EXP_RXN15

DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3

R189 51R189 51

GTLREF voltage should be 0.67*VTT = 0.75V
12 mils width, 15 mils spacing
divider should be within 1.5" of the GTLREF pin
220pF caps should be placed near MCH pin
place series resistor as close to divider
Resistor and Capacitor next to each other

U1MCH

PEG_TXP_0

PEG_TXN_0

PEG_TXP_1

PEG_TXN_1

PEG_TXP_2

PEG_TXN_2

PEG_TXP_3

PEG_TXN_3

PEG_TXP_4

PEG_TXN_4

PEG_TXP_5

PEG_TXN_5

PEG_TXP_6

PEG_TXN_6

PEG_TXP_7

PEG_TXN_7

PEG_TXP_8

PEG_TXN_8

PEG_TXP_9

PEG_TXN_9

PEG_TXP_10

PCIE

PCIE

PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_TXP_13
PEG_TXN_13
PEG_TXP_14
PEG_TXN_14
PEG_TXP_15
PEG_TXN_15

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
DMI_TXP_2
DMI_TXN_2
DMI_TXP_3

DMI

DMI

DMI_TXN_3

EXP_COMPO

EXP_COMPI

2 OF 8

2 OF 8

R167 10KR167 10K

R168 10KR168 10K

R185 10KR185 10K

R183 1K

FSBSEL0_R

FSBSEL1_R

FSBSEL2_R

dummyR183 1K

dummy

-0.05r0603h6

-0.05r0603h6

ATX: dummy
BTX: pop

3

EXP_TXP0

D11

EXP_TXN0

D12

EXP_TXP1

B11

EXP_TXN1

A10

EXP_TXP2

C10

EXP_TXN2

D9

EXP_TXP3

B9

EXP_TXN3

B7

EXP_TXP4

D7

EXP_TXN4

D6

EXP_TXP5

B5

EXP_TXN5

B6

EXP_TXP6

B3
B4

EXP_TXP7

F2

EXP_TXN7

E2

EXP_TXP8

F4

EXP_TXN8

G4

EXP_TXP9

J4

EXP_TXN9

K3

EXP_TXP10

L2

EXP_TXN10

K1

EXP_TXP11

N2

EXP_TXN11

M2

EXP_TXP12

P3

EXP_TXN12

N4

EXP_TXP13

R2

EXP_TXN13

P1

EXP_TXP14

U2

EXP_TXN14

T2

EXP_TXP15

V3

EXP_TXN15

U4

DMI_TXP0

V7

DMI_TXN0

V6

DMI_TXP1

W4

DMI_TXN1

Y4

DMI_TXP2

AC8

DMI_TXN2

AC9

DMI_TXP3

Y2

DMI_TXN3

AA2

GMCH_EXP_COMP

AC11
AC12

width 10 mils, spacing 6 mils at breakout
10 mils after that

GMCH_EXP_SLR

EXP_TXP0 17
EXP_TXN0 17
EXP_TXP1 17
EXP_TXN1 17
EXP_TXP2 17
EXP_TXN2 17
EXP_TXP3 17
EXP_TXN3 17
EXP_TXP4 17
EXP_TXN4 17
EXP_TXP5 17
EXP_TXN5 17
EXP_TXP6 17
EXP_TXN6 17
EXP_TXP7 17
EXP_TXN7 17
EXP_TXP8 17
EXP_TXN8 17
EXP_TXP9 17
EXP_TXN9 17
EXP_TXP10 17
EXP_TXN10 17
EXP_TXP11 17
EXP_TXN11 17
EXP_TXP12 17
EXP_TXN12 17
EXP_TXP13 17
EXP_TXN13 17
EXP_TXP14 17
EXP_TXN14 17
EXP_TXP15 17
EXP_TXN15 17

DMI_TXP0 19
DMI_TXN0 19
DMI_TXP1 19
DMI_TXN1 19
DMI_TXP2 19
DMI_TXN2 19
DMI_TXP3 19
DMI_TXN3 19

R235 24.9

R235 24.9

2

FSBSEL0_R
FSBSEL1_R VSYNC_P
FSBSEL2_R
TP_ALLZTEST

TP10TP10

TP_XORTEST

TP7TP7

GMCH_EXP_SLR

GMCH_EXP_EN_HDR17

Enable TLS

Controller Link Routing

1. width=4 mils, Spacing=7 mils

2. CL_CLK and CL_DATA should be length
matched to within 100 mils

1D25V_MCH

+/-1%

+/-1%

1D25V_MCH

R263

R263
1K

1K

+/-1%

+/-1%

R262

R262
392 Ohm

392 Ohm

+/-1%

+/-1%

min. 4 mils width
10 mils spacing
5 mils min. for max. of 300 mils in breakout

GMCH_EXP_EN_HDR

R1861KR186
1K

CL_DATA

CL_DATA20

CL_CLK

CL_CLK20

CL_VREF_MCH
CL_RST

CL_RST20

PWRGD_3V

placed close to GMCH within 500 mils
4 mils width
6 mils spacing to static signals
12 mils spacing to toppling signals

CL_VREF_MCH

C324

C324

0.349V

12

0.1uF

0.1uF

*

*

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

Place close to VREF Pin

R192 1.3K +/-1%R192 1.3K+/-1%

2

AD12
AD13

AA12

AM15

AA10
AA11

G20

K20
G18

E18
K17

G15

M18
V31

AM5

AA9
Y12
U30

U31
R29
R30

U12
U11
R12
R13

J20
J18

F20

J17

L17
E20
N18
N15
N17
L15
L18

U16E

U16E

BSEL0
BSEL1
BSEL2
ALLZTEST
XORTEST
RESERVED_11
EXP_SLR
RESERVED_12
EXP_EN
RESERVED_13

RESERVED_14
TCEN
RESERVED_16
RESERVED_17
RESERVED_18
RESERVED_19
RESERVED_20
RESERVED_21
RESERVED_15

CL_DATA
CL_CLK
CL_VREF
CL_RSTB
CL_PWROK

RESERVED_22
RESERVED_23
RESERVED_24
RESERVED_25

RESERVED_26
RESERVED_27
RESERVED_28
RESERVED_29

RESERVED_30
RESERVED_31
RESERVED_32
RESERVED_33

REFSET

CRT_GREENB

CRT_DDC_DATA

CRT_DDC_CLK

DPL_REFCLKINP
DPL_REFCLKINN

RESERVED_34
RESERVED_35
RESERVED_36

MISC VGA

MISC VGA

RESERVED_37

5 OF 8

5 OF 8

Bearlake G33

Bearlake G33

This part is just for its footprint of MCH
Del it in BOM

1

Placed both Resistors close to GMCH
Within 750 mils
W=4 mils, S=10 mils from GMCH to connector

HSYNC_P

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE
CRT_REDB

CRT_BLUEB

CRT_IREF

RSTINB

PWROK

ICH_SYNCB

VSS

NC

HEATSINK

HEATSINK

1
3 4
5 6
7 8

C15
E15

B18
C19
B20
C18
D19
D20

L13
M13

A20
C14

D13
M11

H18
F17
A14
AM18
AM17
J13

A42
R20

DDCA_CLK

DDCA_DATA

2

Header_2X4

Header_2X4

DDCA_DATA
DDCA_CLK

R195 39+/-1%R195 39+/-1%
R196 39+/-1%R196 39+/-1%

R200

R200

150

150

+/-1%

+/-1%

DDCA_DATA 18
DDCA_CLK 18

REFSET
CK_96M_P_GMCH

CK_96M_N_GMCH

TP_MCH_F13
TP_MCH_F17
TP_MCH_A14
ICH_PLTRSTJ
PWRGD_3V
ICH_SYNCJ

3D3V_SYS

3D3V_SYS

CK_96M_P_GMCH 4
CK_96M_N_GMCH 4

TP9TP9
TP5TP5

TP3TP3

ICH_PLTRSTJ 24,34
PWRGD_3V 16,19,20
ICH_SYNCJ 19

R184

R184

2.2K

2.2K

R191

R191

2.2K

2.2K

U16_1

U16_1

A

A

FOXCONN

FOXCONN

BC

BC

Heatsink

Heatsink

CLIP1N

CLIP1N

Clip_2P

Clip_2P

For GMCH heatsink hook

FOXCONN PCEG

FOXCONN PCEG

Title

Title

Title

Bearlake GMCH -1

Bearlake GMCH -1

Bearlake GMCH -1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

FOXCONN PCEG

G33M03

G33M03

G33M03

1

R201

R201

150

150

+/-1%

+/-1%

CLIP3N

CLIP3N

Clip_2P

Clip_2P

HSYNC 18
VSYNC 18

RED 18
GREEN 18
BLUE 18

R202

R202

150

150

+/-1%

+/-1%

Placed close to
GMCH within
300 mils

(R)

(R)

of

of

of

837Thursday, April 26, 2007

837Thursday, April 26, 2007

837Thursday, April 26, 2007

D

D

CC

CC

CC

5

U16C

U16C

M_MAA_A[14..0]12,13

D D

M_WE_AJ12,13
M_CAS_AJ12,13
M_RAS_AJ12,13

M_BS_A[2..0]12,13

C C

B B

A A

M_SCS_A0J12,15
M_SCS_A1J12,15
M_SCS_A2J12,15
M_SCS_A3J12,13

M_SCKE_A[3..0]12,13

M_ODT_A[3..0]12,13,15

CK_M_200M_P_DDR0_A12
CK_M_200M_N_DDR0_A12
CK_M_200M_P_DDR1_A12
CK_M_200M_N_DDR1_A12
CK_M_200M_P_DDR2_A12
CK_M_200M_N_DDR2_A12
CK_M_200M_P_DDR3_A12
CK_M_200M_N_DDR3_A12
CK_M_200M_P_DDR4_A12
CK_M_200M_N_DDR4_A12
CK_M_200M_P_DDR5_A12
CK_M_200M_N_DDR5_A12

5

TP15TP15

M_MAA_A0
M_MAA_A1
M_MAA_A2
M_MAA_A3
M_MAA_A4
M_MAA_A5
M_MAA_A6
M_MAA_A7
M_MAA_A8
M_MAA_A9
M_MAA_A10
M_MAA_A11
M_MAA_A12
M_MAA_A13
M_MAA_A14

M_BS_A0
M_BS_A1
M_BS_A2

M_SCKE_A0
M_SCKE_A1
M_SCKE_A2
M_SCKE_A3

M_ODT_A0
M_ODT_A1
M_ODT_A2
M_ODT_A3

TP_MCH_AN21

BB30

DDR_A_MA_0

AY25

DDR_A_MA_1

BA23

DDR_A_MA_2

BB23

DDR_A_MA_3

AY23

DDR_A_MA_4

BB22

DDR_A_MA_5

BA22

DDR_A_MA_6

BB21

DDR_A_MA_7

AW21

DDR_A_MA_8

BA21

DDR_A_MA_9

BB31

DDR_A_MA_10

AY21

DDR_A_MA_11

BC20

DDR_A_MA_12

AY38

DDR_A_MA_13

BA19

DDR_A_MA_14

BA33

DDR_A_WEB

AW35

DDR_A_CASB

AY33

DDR_A_RASB

BA31

DDR_A_BS_0

AY31

DDR_A_BS_1

AY20

DDR_A_BS_2

BA34

DDR_A_CSB_0

AY35

DDR_A_CSB_1

BB33

DDR_A_CSB_2

BB38

DDR_A_CSB_3

AY19

DDR_A_CKE_0

AW18

DDR_A_CKE_1

BB19

DDR_A_CKE_2

BA18

DDR_A_CKE_3

BB35

DDR_A_ODT_0

BA38

DDR_A_ODT_1

BA35

DDR_A_ODT_2

BA39

DDR_A_ODT_3

AR31

DDR_A_CK_0

AU31

DDR_A_CKB_0

AP27

DDR_A_CK_1

AN27

DDR_A_CKB_1

AV33

DDR_A_CK_2

AW33

DDR_A_CKB_2

AP29

DDR_A_CK_3

AP31

DDR_A_CKB_3

AM26

DDR_A_CK_4

AM27

DDR_A_CKB_4

AT33

DDR_A_CK_5

AU33

DDR_A_CKB_5

DDR_A

DDR_A

AN21

RESERVED_1

C335

C335

*

*

0.1uF

0.1uF

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

3 OF 8

3 OF 8

U1MCH

U1MCH

DDR_A_DQS_0

DDR_A_DQSB_0

DDR_A_DQS_1

DDR_A_DQSB_1

DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15

DDR_A_DQS_2

DDR_A_DQSB_2

DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23

DDR_A_DQS_3

DDR_A_DQSB_3

DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31

DDR_A_DQS_4

DDR_A_DQSB_4

DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39

DDR_A_DQS_5

DDR_A_DQSB_5

DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47

DDR_A_DQS_6

DDR_A_DQSB_6

DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55

DDR_A_DQS_7

DDR_A_DQSB_7

DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

Bearlake G33

Bearlake G33

1D8V_STR

4

DDR_A_DM_0
DDR_A_DQ_0

DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7

DDR_A_DM_1
DDR_A_DQ_8

DDR_A_DQ_9

DDR_A_DM_2

DDR_A_DM_3

DDR_A_DM_4

DDR_A_DM_5

DDR_A_DM_6

DDR_A_DM_7

R261

R261
1K

1K

+/-1%

+/-1%

SMRCOMPVOH

R252

R252

3.01K

3.01K

+/-1%

+/-1%

SMRCOMPVOL

R253

R253
1K

1K

+/-1%

+/-1%

4

AP2
AP3
AN2

AM1
AN3
AR2
AR3
AL3
AM2
AR5
AR4

AW2
AW1
AW3

AV4
AV3
BA4
BB3
AU2
AU1
AY2
AY3

AY7
BA6
BB6

BB5
AY6
BA9
BB9
BA5
BB4
BC7
AY9

AT20
AU18
AN18

AT18
AR18
AU21
AT21
AP17
AN17
AP20
AV20

AR41
AR40
AU43

AV42
AU40
AP42
AN39
AV40
AV41
AR42
AP41

AL41
AL40
AM43

AN41
AM39
AK42
AK41
AN40
AN42
AL42
AL39

AG42
AG41
AG40

AJ40
AH43
AF39
AE40
AJ42
AJ41
AF41
AF42

AC42
AC41
AC40

AD40
AD43
AB41
AA40
AE42
AE41
AC39
AB42

C317

C317

12

10nF

10nF

*

*

C0603

C0603

50V, X7R, +/-10%

50V, X7R, +/-10%

M_DQS_A0
M_DQS_AJ0
M_DQM_A0

M_DATA_A0
M_DATA_A1
M_DATA_A2
M_DATA_A3
M_DATA_A4
M_DATA_A5
M_DATA_A6
M_DATA_A7

M_DQS_A1
M_DQS_AJ1
M_DQM_A1

M_DATA_A8
M_DATA_A9
M_DATA_A10
M_DATA_A11
M_DATA_A12
M_DATA_A13
M_DATA_A14
M_DATA_A15

M_DQS_A2
M_DQS_AJ2
M_DQM_A2

M_DATA_A16
M_DATA_A17
M_DATA_A18
M_DATA_A19
M_DATA_A20
M_DATA_A21
M_DATA_A22
M_DATA_A23

M_DQS_A3
M_DQS_AJ3
M_DQM_A3

M_DATA_A24
M_DATA_A25
M_DATA_A26
M_DATA_A27
M_DATA_A28
M_DATA_A29
M_DATA_A30
M_DATA_A31

M_DQS_A4
M_DQS_AJ4
M_DQM_A4

M_DATA_A32
M_DATA_A33
M_DATA_A34
M_DATA_A35
M_DATA_A36
M_DATA_A37
M_DATA_A38
M_DATA_A39

M_DQS_A5
M_DQS_AJ5
M_DQM_A5

M_DATA_A40
M_DATA_A41
M_DATA_A42
M_DATA_A43
M_DATA_A44
M_DATA_A45
M_DATA_A46
M_DATA_A47

M_DQS_A6
M_DQS_AJ6
M_DQM_A6

M_DATA_A48
M_DATA_A49
M_DATA_A50
M_DATA_A51
M_DATA_A52
M_DATA_A53
M_DATA_A54
M_DATA_A55

M_DQS_A7
M_DQS_AJ7
M_DQM_A7

M_DATA_A56
M_DATA_A57
M_DATA_A58
M_DATA_A59
M_DATA_A60
M_DATA_A61
M_DATA_A62
M_DATA_A63

*

*

C323

C323

12

10nF

10nF

C0603

C0603

50V, X7R, +/-10%

50V, X7R, +/-10%

3

M_DQS_A[7..0] 12
M_DQS_AJ[7..0] 12
M_DQM_A[7..0] 12
M_DATA_A[63..0] 12

M_DQS_A[7..0] 12
M_DQS_AJ[7..0] 12
M_DQM_A[7..0] 12
M_DATA_A[63..0] 12

M_DQS_A[7..0] 12
M_DQS_AJ[7..0] 12
M_DQM_A[7..0] 12
M_DATA_A[63..0] 12

M_DQS_A[7..0] 12
M_DQS_AJ[7..0] 12
M_DQM_A[7..0] 12
M_DATA_A[63..0] 12

M_DQS_A[7..0] 12
M_DQS_AJ[7..0] 12
M_DQM_A[7..0] 12
M_DATA_A[63..0] 12

M_DQS_A[7..0] 12
M_DQS_AJ[7..0] 12
M_DQM_A[7..0] 12
M_DATA_A[63..0] 12

M_DQS_A[7..0] 12
M_DQS_AJ[7..0] 12
M_DQM_A[7..0] 12
M_DATA_A[63..0] 12

M_DQS_A[7..0] 12
M_DQS_AJ[7..0] 12
M_DQM_A[7..0] 12
M_DATA_A[63..0] 12

M_MAA_B[14..0]14,15

M_SCKE_B[3..0]14,15

M_ODT_B[3..0]14,15

DDR2 Compensation Group Signals

+/-1%

+/-1%

+/-1%

+/-1%

+/-1%

+/-1%

+/-1%

+/-1%

COMPXPD

COMPXPU

COMPYPD

COMPYPU

R254 19.1 Ohm

R254 19.1 Ohm

1D8V_STR

1D8V_STR

5 mils width, 10 mils spacing, max 500 mils length for breakout region
Place CAP./RES. within 1" of GMCH package.
1D8V_STR: 10 mils width/10 mils spacing.
SMRCOMPVOH: 0.8 *VCCSM
SMRCOMPVOL: 0.2 *VCCSM

C330

C330

*

*

0.1uF

0.1uF

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

C342

C342

*

*

0.1uF

0.1uF

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

R257 19.1 Ohm

R257 19.1 Ohm

R299 19.1 Ohm

R299 19.1 Ohm

R294 19.1 Ohm

R294 19.1 Ohm

3

2

U1MCH

U1MCH

U16D

U16D

M_MAA_B0

AW15

DDR_B_MA_0

M_MAA_B1

BB15

M_MAA_B2

BA15

M_MAA_B3

AY15

M_MAA_B4

BA14

M_MAA_B5

BB14

M_MAA_B6

AW12

M_MAA_B7

BA13

M_MAA_B8

BB13

M_MAA_B9

AY13

M_MAA_B10

BA17

M_MAA_B11

AY12

M_MAA_B12

BA11

M_MAA_B13

AY27

M_MAA_B14

BB11

M_BS_B0
M_BS_B1
M_BS_B2

M_SCKE_B0
M_SCKE_B1
M_SCKE_B2
M_SCKE_B3

M_ODT_B0
M_ODT_B1
M_ODT_B2
M_ODT_B3

R293

R293
1K

1K

+/-1%

+/-1%

R284

R284
1K

1K

+/-1%

+/-1%

2

BB25

AW26

AY24
BB17

AY17
AY11

BA25
BA29
BA26
BA30

AW11

BC12
BA10
BB10

BB27

AW29

BA27
AY29

AW31

AV31
AU27

AT27

AV32

AT32
AR29
AU29
AV29

AW27

AN33
AP32

BA2

AW42

AN32
AM31
AG32

AF32
AP21
AA39

AM21

AM6

AL4

AL2
BB40
BA40

AM8
AM10

DDR_GMCH_VREF

C334

C334

0.1uF

0.1uF

*

*

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

M_WE_BJ14,15
M_CAS_BJ14,15
M_RAS_BJ14,15

M_BS_B[2..0]14,15

M_SCS_B0J14,15
M_SCS_B1J14,15
M_SCS_B2J14,15
M_SCS_B3J14,15

CK_M_200M_P_DDR0_B14
CK_M_200M_N_DDR0_B14
CK_M_200M_P_DDR1_B14
CK_M_200M_N_DDR1_B14
CK_M_200M_P_DDR2_B14
CK_M_200M_N_DDR2_B14
CK_M_200M_P_DDR3_B14
CK_M_200M_N_DDR3_B14
CK_M_200M_P_DDR4_B14
CK_M_200M_N_DDR4_B14
CK_M_200M_P_DDR5_B14
CK_M_200M_N_DDR5_B14

TP_MCH_AP21

TP19TP19

TP_MCH_AA39

TP14TP14

TP_MCH_AM21

TP17TP17

DDR_GMCH_VREF

COMPXPD
COMPXPU
COMPYPD
COMPYPU
SMRCOMPVOL
SMRCOMPVOH

1D8V_STR

width 10 mils, spacing 10 mils
5 mils width/spacing minimum for max. of 300 mils
in GMCH break-out area
Placed close to GMCH pin

DDR_B_MA_1
DDR_B_MA_2
DDR_B_MA_3
DDR_B_MA_4
DDR_B_MA_5
DDR_B_MA_6
DDR_B_MA_7
DDR_B_MA_8
DDR_B_MA_9
DDR_B_MA_10
DDR_B_MA_11
DDR_B_MA_12
DDR_B_MA_13
DDR_B_MA_14

DDR_B_WEB
DDR_B_CASB
DDR_B_RASB

DDR_B_BS_0
DDR_B_BS_1
DDR_B_BS_2

DDR_B_CSB_0
DDR_B_CSB_1
DDR_B_CSB_2
DDR_B_CSB_3

DDR_B_CKE_0
DDR_B_CKE_1
DDR_B_CKE_2
DDR_B_CKE_3

DDR_B_ODT_0
DDR_B_ODT_1
DDR_B_ODT_2
DDR_B_ODT_3

DDR_B_CK_0
DDR_B_CKB_0
DDR_B_CK_1
DDR_B_CKB_1
DDR_B_CK_2
DDR_B_CKB_2
DDR_B_CK_3
DDR_B_CKB_3
DDR_B_CK_4
DDR_B_CKB_4
DDR_B_CK_5
DDR_B_CKB_5

RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5
RESERVED_6
RESERVED_7
RESERVED_8
RESERVED_9

DDR_B

DDR_B

RESERVED_10
DDR_VREF

DDR_RCOMPXPD
DDR_RCOMPXPU
DDR_RCOMPYPD
DDR_RCOMPYPU
DDR_RCOMPVOL
DDR_RCOMPVOH

Bearlake G33

Bearlake G33

DDR_B_DQS_0

DDR_B_DQSB_0

DDR_B_DM_0
DDR_B_DQ_0

DDR_B_DQ_1
DDR_B_DQ_2
DDR_B_DQ_3
DDR_B_DQ_4
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_7

DDR_B_DQS_1

DDR_B_DQSB_1

DDR_B_DM_1
DDR_B_DQ_8

DDR_B_DQ_9
DDR_B_DQ_10
DDR_B_DQ_11
DDR_B_DQ_12
DDR_B_DQ_13
DDR_B_DQ_14
DDR_B_DQ_15

DDR_B_DQS_2

DDR_B_DQSB_2

DDR_B_DM_2
DDR_B_DQ_16

DDR_B_DQ_17
DDR_B_DQ_18
DDR_B_DQ_19
DDR_B_DQ_20
DDR_B_DQ_21
DDR_B_DQ_22
DDR_B_DQ_23

DDR_B_DQS_3

DDR_B_DQSB_3

DDR_B_DM_3
DDR_B_DQ_24

DDR_B_DQ_25
DDR_B_DQ_26
DDR_B_DQ_27
DDR_B_DQ_28
DDR_B_DQ_29
DDR_B_DQ_30
DDR_B_DQ_31

DDR_B_DQS_4

DDR_B_DQSB_4

DDR_B_DM_4
DDR_B_DQ_32

DDR_B_DQ_33
DDR_B_DQ_34
DDR_B_DQ_35
DDR_B_DQ_36
DDR_B_DQ_37
DDR_B_DQ_38
DDR_B_DQ_39

DDR_B_DQS_5

DDR_B_DQSB_5

DDR_B_DM_5
DDR_B_DQ_40

DDR_B_DQ_41
DDR_B_DQ_42
DDR_B_DQ_43
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_46
DDR_B_DQ_47

DDR_B_DQS_6

DDR_B_DQSB_6

DDR_B_DM_6
DDR_B_DQ_48

DDR_B_DQ_49
DDR_B_DQ_50
DDR_B_DQ_51
DDR_B_DQ_52
DDR_B_DQ_53
DDR_B_DQ_54
DDR_B_DQ_55

DDR_B_DQS_7

DDR_B_DQSB_7

DDR_B_DM_7
DDR_B_DQ_56

DDR_B_DQ_57
DDR_B_DQ_58
DDR_B_DQ_59
DDR_B_DQ_60
DDR_B_DQ_61
DDR_B_DQ_62
DDR_B_DQ_63

4 OF 8

4 OF 8

M_DQS_B0

AV6

M_DQS_BJ0

AU5

M_DQM_B0

AR7

M_DATA_B0

AN7

M_DATA_B1

AN8

M_DATA_B2

AW5

M_DATA_B3

AW7

M_DATA_B4

AN5

M_DATA_B5

AN6

M_DATA_B6

AN9

M_DATA_B7

AU7

M_DQS_B1

AR12

M_DQS_BJ1

AP12

M_DQM_B1

AW9

M_DATA_B8

AT11

M_DATA_B9

AU11

M_DATA_B10

AP13

M_DATA_B11

AR13

M_DATA_B12

AR11

M_DATA_B13

AU9

M_DATA_B14

AV12

M_DATA_B15

AU12

M_DQS_B2

AP15

M_DQS_BJ2

AR15

M_DQM_B2

AW13

M_DATA_B16

AU15

M_DATA_B17

AV13

M_DATA_B18

AU17

M_DATA_B19

AT17

M_DATA_B20

AU13

M_DATA_B21

AM13

M_DATA_B22

AV15

M_DATA_B23

AW17

M_DQS_B3

AT24

M_DQS_BJ3

AU26

M_DQM_B3

AP23

M_DATA_B24

AV24

M_DATA_B25

AT23

M_DATA_B26

AT26

M_DATA_B27

AP26

M_DATA_B28

AU23

M_DATA_B29

AW23

M_DATA_B30

AR24

M_DATA_B31

AN26

M_DQS_B4

AW39

M_DQS_BJ4

AU39

M_DQM_B4

AU37

M_DATA_B32

AW37

M_DATA_B33

AV38

M_DATA_B34

AN36

M_DATA_B35

AN37

M_DATA_B36

AU35

M_DATA_B37

AR35

M_DATA_B38

AN35

M_DATA_B39

AR37

M_DQS_B5

AL35

M_DQS_BJ5

AL34

M_DQM_B5

AM37

M_DATA_B40

AM35

M_DATA_B41

AM38

M_DATA_B42

AJ34

M_DATA_B43

AL38

M_DATA_B44

AR39

M_DATA_B45

AM34

M_DATA_B46

AL37

M_DATA_B47

AL32

M_DQS_B6

AG35

M_DQS_BJ6

AG36

M_DQM_B6

AG39

M_DATA_B48

AG38

M_DATA_B49

AJ38

M_DATA_B50

AF35

M_DATA_B51

AF33

M_DATA_B52

AJ37

M_DATA_B53

AJ35

M_DATA_B54

AG33

M_DATA_B55

AF34

M_DQS_B7

AC36

M_DQS_BJ7

AC37

M_DQM_B7

AD38

M_DATA_B56

AD36

M_DATA_B57

AC33

M_DATA_B58

AA34

M_DATA_B59

AA36

M_DATA_B60

AD34

M_DATA_B61

AF38

M_DATA_B62

AC34

M_DATA_B63

AA33

Title

Title

Title

Bearlake GMCH -2

Bearlake GMCH -2

Bearlake GMCH -2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

1

M_DQS_B[7..0] 14
M_DQS_BJ[7..0] 14
M_DQM_B[7..0] 14
M_DATA_B[63..0] 14

M_DQS_B[7..0] 14
M_DQS_BJ[7..0] 14
M_DQM_B[7..0] 14
M_DATA_B[63..0] 14

M_DQS_B[7..0] 14
M_DQS_BJ[7..0] 14
M_DQM_B[7..0] 14
M_DATA_B[63..0] 14

M_DQS_B[7..0] 14
M_DQS_BJ[7..0] 14
M_DQM_B[7..0] 14
M_DATA_B[63..0] 14

M_DQS_B[7..0] 14
M_DQS_BJ[7..0] 14
M_DQM_B[7..0] 14
M_DATA_B[63..0] 14

M_DQS_B[7..0] 14
M_DQS_BJ[7..0] 14
M_DQM_B[7..0] 14
M_DATA_B[63..0] 14

M_DQS_B[7..0] 14
M_DQS_BJ[7..0] 14
M_DQM_B[7..0] 14
M_DATA_B[63..0] 14

M_DQS_B[7..0] 14
M_DQS_BJ[7..0] 14
M_DQM_B[7..0] 14
M_DATA_B[63..0] 14

FOXCONN PCEG

FOXCONN PCEG

FOXCONN PCEG

G33M03

G33M03

G33M03

1

937Thursday, April 26, 2007

937Thursday, April 26, 2007

937Thursday, April 26, 2007

CC

CC

CC

of

of

of

5

4

3

2

1

VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98

VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
VCC_162
VCC_163
VCC_164
VCC_165
VCC_166
VCC_167
VCC_168
VCC_169
VCC_170
VCC_171

AG7
AG8
AG9
AH1
AH2
AH4
AJ10
AJ11
AJ12
AJ5
AJ6
AJ7
AJ8
AJ9
C13
C9
D4
F11
F9
G2
J2
J3
J6
L12
L6
N11
N12
N3
N6
N8
N9
P14
P15
P20
R14
R15
R17
R18
U10
U13
U14
U15
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U3
U6
U9
V10
V12
V13
V14
V15
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V9
W17
W18
W19
W21
W23
W25
W26
W27
Y11
Y13
Y14
Y15
Y17
Y18
Y20
Y22
Y24
Y26
Y27
Y6

R27
R26
R24
R23
P29
P27
P26
P24
P23
N29
N26
N24
N23
M29
M24
M23
L24
L23
K24

AY42
BA42
BA43
BB41
BB42

1D25V_MCH

FSB_VTT

*

*

12

C327

C327

0.1uF

0.1uF

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

3D3V_SYS

*

*

1D8V_STR

L24

L24
L0805 1uH

L0805 1uH

0805h11

0805h11
+/-10%

+/-10%

R2831R283

R2861R286

1

1

12

C338

C338

*

*

10uF

10uF

C0805

C0805

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

FB21

FB21
FB L0603 600 Ohm

FB L0603 600 Ohm

0603

0603

1 2

R197 1R197 1

R198 1R198 1

12

C2251uFC0603

C2251uFC0603

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

VCCA_EXP

VCCA_DAC

U16F

1D5V_ICH

FB20

FB20

*

*

FB L0603 600 Ohm

FB L0603 600 Ohm

0603

0603

D D

1D5V_ICH

C217

C217

4.7uF

4.7uF

*

*

C0805

C0805

6.3V, X5R, +/-10%

6.3V, X5R, +/-10%

C C

1D25V_MCH

B B

A A

1D25V_MCH

L19

L19

L17 2.2uH

L17 2.2uH

L0805 1uH

L0805 1uH

1 2

0805h11+/-10%

0805h11+/-10%

L16

L16

1 2

0805h14+/-20%

0805h14+/-20%

L18

L18

1 2

0805h14+/-20%

0805h14+/-20%

L20 270nH

L20 270nH

*

*

0805h11 +/-20%

0805h11 +/-20%

*

*

1206h13+/-20%

1206h13+/-20%

R188 1R188 1

R187 1R187 1

L0805 10uH

L0805 10uH

L0805 10uH

L0805 10uH

R180 1R180 1

R179 1R179 1

EC18

EC18

220uF

220uF

*

*

6.3V, +/-20%

6.3V, +/-20%

EC19

EC19

220uF

220uF

*

*

6.3V, +/-20%

6.3V, +/-20%

12

*

*

VCCA_HPLL

C228

C228

12

2.2uF

2.2uF

*

*

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

C0603

C0603

VCCA_MPLL

C234

C234

12

10uF

10uF

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

C0805

C0805

C239

C239

12

0.1uF

0.1uF

*

*

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

C233

C233

12

0.1uF

0.1uF

*

*

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

R193 1R193 1

C227

C227

1uF

1uF

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

C0603

C0603

*

*

C210

C210

12

10uF

10uF

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

C0805

C0805

VCCA_EXPPLL

VCCA_DPLLA

VCCA_DPLLB

C226

C226

12

0.1uF

0.1uF

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

C236

C236

12

0.1uF

0.1uF

*

*

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

VCCDQ_CRT

VCCD_CRT

3D3V_SYS

12

C230

C230

*

*

0.1uF

0.1uF

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

VCCDQ_CRT
VCCD_CRT
VCCA_EXPPLL
VCCA_MPLL
VCCA_HPLL
VCCA_EXP

FSB_VTT

VCCA_DPLLB
VCCA_DPLLA
VCCA_DAC

1D25V_MCH

AA13
AA14
AA15
AA17
AA19
AA21
AA23
AA25
AA26
AA27

AB17
AB18
AB20
AB22
AB24
AB26
AB27
AC13
AC14
AC15
AC17
AC19
AC21
AC23
AC25
AC26
AC27

AD14
AD15
AD17
AD18
AD20
AD22
AD24
AD26
AD27
AE17
AE19
AE21
AE23
AE25
AE26
AE27

AF11
AF12
AF13
AF14
AF15
AF17
AF18

AF20
AF22
AF24
AF25
AF26

AG10
AG11
AG12
AG13
AG14
AG15
AG17
AG18
AG19

AG20
AG21
AG22
AG23
AG24

AA3

AC6

AF1

AF2

AF3

AG2

AG3
AG4
AG5
AG6

B21
C21
B15
A24
C23
A16

B17
A28

A30
B27
B28
B29
B30
C27
C29
C30
D27
D28
D29
E23
E26
E27
E29
F23
F24
F26
G23
G24
G26
H23
H24
J23
J24
K23

C22
A22
B16
C17

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79

VCCDQ_CRT
VCCD_CRT
VCCAPLL_EXP
VCCA_MPLL
VCCA_HPLL
VCCA_EXP

VCC3_3
VTT_FSB_1

VTT_FSB_2
VTT_FSB_3
VTT_FSB_4
VTT_FSB_5
VTT_FSB_6
VTT_FSB_7
VTT_FSB_8
VTT_FSB_9
VTT_FSB_10
VTT_FSB_11
VTT_FSB_12
VTT_FSB_13
VTT_FSB_14
VTT_FSB_15
VTT_FSB_16
VTT_FSB_17
VTT_FSB_18
VTT_FSB_19
VTT_FSB_20
VTT_FSB_21
VTT_FSB_22
VTT_FSB_23
VTT_FSB_24
VTT_FSB_25
VTT_FSB_26
VTT_FSB_27

VCCA_DPLLB
VCCA_DPLLA
VCCA_DAC_1
VCCA_DAC_2

U16F

POWER

POWER

VCC_CKDDR_1
VCC_CKDDR_2
VCC_CKDDR_3
VCC_CKDDR_4
VCC_CKDDR_5

VTT_FSB_46
VTT_FSB_45
VTT_FSB_44
VTT_FSB_43
VTT_FSB_42
VTT_FSB_41
VTT_FSB_40
VTT_FSB_39
VTT_FSB_38
VTT_FSB_37
VTT_FSB_36
VTT_FSB_35
VTT_FSB_34
VTT_FSB_33
VTT_FSB_32
VTT_FSB_31
VTT_FSB_30
VTT_FSB_29
VTT_FSB_28

6 OF 8

6 OF 8

Bearlake G33

Bearlake G33

FOXCONN PCEG

FOXCONN PCEG

Title

Title

Title

Bearlake GMCH -3

Bearlake GMCH -3

Bearlake GMCH -3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet of

FOXCONN PCEG

G33M03

G33M03

G33M03

1

10 37Thursday, April 26, 2007

10 37Thursday, April 26, 2007

10 37Thursday, April 26, 2007

CC

CC

CC

of

of

5

A39

VSS_13 AA24

VSS_161C5

VSS_11 AA20

VSS_12 AA22

C6 VSS_162

D15 VSS_163

VSS_10 AA18

VSS_164D16

VSS_8 A5

VSS_9 A7

D17 VSS_165

D21 VSS_166

A41

VSS_6

VSS_7

B22 VSS_140

B23 VSS_141

VSS_4 A3

VSS_5 A34

GND

GND

B26 VSS_142

B31 VSS_143

VSS_2 A18

VSS_3 A26

B32 VSS_144

B37 VSS_145

VSS_1 A12

VSS_181 F27

VSS_182 F3

BA1 VSS_146

BB7 VSS_147

BC10 VSS_148

VSS_183 F35

VSS_184 F37

BC24 VSS_149

BC37 VSS_153

VSS_185 G1

VSS_186 G11

VSS_187 G12

C1 VSS_156

BC5 VSS_155

BC41 VSS_154

VSS_188 G13

VSS_189 G21

VSS_190 G32

C11 VSS_157

C26 VSS_158

C4 VSS_159

U16G

U16G

VSS_14 AA35

VSS_15 AA38

VSS_16 AA5

VSS_17 AA8

VSS_18 AB1

VSS_19 AB19

VSS_20 AB2

VSS_21 AB21

AB23

VSS_22

AB25

VSS_23

AB43

VSS_24

AC10

VSS_25

AC18

VSS_26

AC20

VSS_27

D D

C C

B B

A A

AC22
AC24
AC35
AC38

AD19
AD21
AD23
AD25
AD33
AD35
AD37
AD39
AD42
AE18

AE20
AE22
AE24

AF10
AF19
AF21
AF23
AF36
AF37
AF43

AG34
AG37
AH42

AK43

AM11
AM20
AM23
AM24
AM29
AM33
AM36

AM40
AM42

AN11
AN12
AN13
AN20
AN23
AN24
AN29
AN31
AN38

AP18
AP24
AP43
AR17
AR20
AR21
AR23
AR26
AR27
AR32
AR33
AR38

AT12
AT13
AT15
AT29
AT31
AU20
AU24
AU32
AU38

AU42
AV11

AV17
AV21

AV23
AV27
AV35
AV37

AW41
AW43

AJ32
AJ33
AJ36
AJ39

AL31
AL33
AL36

VSS_28
VSS_29
VSS_30
VSS_31

AC5

VSS_32

AC7

VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43

AE2

VSS_44
VSS_45
VSS_46
VSS_47

AE3

VSS_48

AE4

VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56

AF5

VSS_57

AF6

VSS_58

AF7

VSS_59

AF8

VSS_60

AF9

VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79

AM4

VSS_80
VSS_81
VSS_82

AM7

VSS_83

AM9

VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93

AN4

VSS_94

AP1

VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107

AR6

VSS_108

AR9

VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118

AU4

VSS_119
VSS_120

AU6

VSS_121
VSS_122
VSS_123

AV2

VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129

AV7

VSS_130

AV9

VSS_131
VSS_132
VSS_133

AY4

VSS_134

B10 VSS_137

B14 VSS_138

B19 VSS_139

AY40 VSS_135

AY41 VSS_136

Bearlake G33

Bearlake G33

7 OF 8

7 OF 8

5

VSS_191 G38

VSS_192 G42

C43 VSS_160

BC28 VSS_150

VSS_193 G7

VSS_194 G9

BC3 VSS_151

BC32 VSS_152

4

H20

VSS_198

H21

VSS_199

H29

VSS_200

H31

VSS_201

VSS_195 H13

VSS_196 H15

VSS_197 H17

J21

VSS_202

J27

VSS_203

J32

VSS_204

J35

VSS_205

J38

VSS_206

J5

VSS_207

J7

VSS_208

J9

VSS_209

K12

VSS_210

K13

VSS_211

K18

VSS_212

K2

VSS_213

K21

VSS_214

K26

VSS_215

K43

VSS_216

L11

VSS_217

L20

VSS_218

L21

VSS_219

L29

VSS_220

L3

VSS_221

L31

VSS_222

L32

VSS_223

L33

VSS_224

L40

VSS_225

L5

VSS_226

L7

VSS_227

M1

VSS_228

M10

VSS_229

M15

VSS_231

M17

VSS_232

M20

VSS_233

M21

VSS_234

M27

VSS_235

M33

VSS_236

M35

VSS_237

M37

VSS_238

M7

VSS_239

N10

VSS_240

N13

VSS_241

N21

VSS_242

N27

VSS_243

N31

VSS_244

N33

VSS_245

N36

VSS_246

N5

VSS_247

N7

VSS_248

P17

VSS_249

P18

VSS_250

P2

VSS_251

P21

VSS_252

P30

VSS_253

P43

VSS_254

R11

VSS_255

R21

VSS_256

R3

VSS_257

R31

VSS_258

R33

VSS_259

R36

VSS_260

R5

VSS_261

R8

VSS_262

T1

VSS_263

T42

VSS_264

U27

VSS_265

U29

VSS_266

U35

VSS_267

U38

VSS_268

U5

VSS_269

U7

VSS_270

U8

VSS_271

V11

VSS_272

V2

VSS_273

V29

VSS_274

V32

VSS_275

V34

VSS_276

V37

VSS_277

V39

VSS_278

V43

VSS_279

V5

VSS_280

V8

VSS_281

W20

VSS_282

W22

VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_180
VSS_179
VSS_178
VSS_177
VSS_176
VSS_175
VSS_174
VSS_173
VSS_172
VSS_171
VSS_170
VSS_169
VSS_168
VSS_167

4

W24
W3
Y1
Y10
Y19
Y21
Y23
Y25
Y33
Y35
Y37
Y42
Y5
Y7
F21
F18
F15
E9
E43
E32
E3
E24
E21
E11
E1
D40
D31
D3

1D25V_MCH

12

*

*

*

*

1D25V_MCH

12

12

12

C59710uFC0805

C59710uFC0805

C30010uFC0805

C30010uFC0805

*

*

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

12

C2802.2uFC0603

C2802.2uFC0603

12

C2502.2uFC0603

C2502.2uFC0603

*

*

*

*

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

1D8V_STR

12

C29010uFC0805

C29010uFC0805

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

C2672.2uFC0603

C2672.2uFC0603

*

*

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

3

U16H

C60110uFC0805

C60110uFC0805

12

VCC_CL_PLL
VCC_CL_1
VCC_CL_2
VCC_CL_3
VCC_CL_4
VCC_CL_5
VCC_CL_6
VCC_CL_7
VCC_CL_8
VCC_CL_9
VCC_CL_10
VCC_CL_11
VCC_CL_12
VCC_CL_13
VCC_CL_14
VCC_CL_15
VCC_CL_16
VCC_CL_17
VCC_CL_18
VCC_CL_19
VCC_CL_20
VCC_CL_21
VCC_CL_22
VCC_CL_23
VCC_CL_24
VCC_CL_25
VCC_CL_26
VCC_CL_27
VCC_CL_28
VCC_CL_29
VCC_CL_30
VCC_CL_31
VCC_CL_32
VCC_CL_33
VCC_CL_34
VCC_CL_35
VCC_CL_36
VCC_CL_37
VCC_CL_38
VCC_CL_39
VCC_CL_40
VCC_CL_41
VCC_CL_42
VCC_CL_43
VCC_CL_44
VCC_CL_45
VCC_CL_46
VCC_CL_47
VCC_CL_48
VCC_CL_49

VCC_DDR_1
VCC_DDR_2
VCC_DDR_3
VCC_DDR_4
VCC_DDR_5
VCC_DDR_6
VCC_DDR_7
VCC_DDR_8
VCC_DDR_9
VCC_DDR_10
VCC_DDR_11
VCC_DDR_12
VCC_DDR_13
VCC_DDR_14
VCC_DDR_15
VCC_DDR_16
VCC_DDR_17
VCC_DDR_18
VCC_DDR_19

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

12

C2381uFC0603

C2381uFC0603

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

U16H

12

*

*

12

C25710uFC0805

C25710uFC0805

C28710uFC0805

C28710uFC0805

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

Y32
AA29
AA30
AA31
AA32
AC29
AC30
AC31
AC32
AD29
AD30
AD31
AD32

AF27
AF29
AF30

AF31
AG25
AG26
AG27
AG29
AG30
AG31

AJ13

AJ14

AJ15

AJ17

AJ18

AJ2
AJ20
AJ21
AJ23
AJ24
AJ26
AJ27
AJ29

AJ3
AJ30
AJ31

AJ4

AK1

AK14
AK15
AK17
AK18

AK2

AK20
AK21
AK23
AK24

AV18

AV26
AW20
AW24

AY32

BB12

BB16

BB18

BB20

BB24

BB26

BB28

BB32

BB37

BB39

BC14

BC18

BC22

BC26

12

12

C27410uFC0805

C27410uFC0805

C59910uFC0805

C59910uFC0805

*

*

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

Place in 1D25V_MCH plane as close to GMCH as possible

12

12

C2411uFC0603

C2411uFC0603

C2961uFC0603

C2961uFC0603

*

*

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

3

8 OF 8

8 OF 8

C5981uFC0603

C5981uFC0603

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

12

DDR3_DRAMRST

DDR3_DRAM_PWROK

DDR3

DDR3

12

C5941uFC0603

C5941uFC0603

C5961uFC0603

C5961uFC0603

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

DDR3_A_CSB1

DDR3_A_MA0

DDR3_A_WEB

DDR3_B_ODT3

RESERVED_39
RESERVED_40
RESERVED_41

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC

NC

NC_9

VCC_CL_77
VCC_CL_76
VCC_CL_75

VCC_CL_73
VCC_CL_72
VCC_CL_71
VCC_CL_70
VCC_CL_69
VCC_CL_68
VCC_CL_67
VCC_CL_66
VCC_CL_65
VCC_CL_64
VCC_CL_63
VCC_CL_62
VCC_CL_61
VCC_CL_60
VCC_CL_59
VCC_CL_58
VCC_CL_57
VCC_CL_56
VCC_CL_55
VCC_CL_54
VCC_CL_53
VCC_CL_52
VCC_CL_51
VCC_CL_50

VCC_EXP_13
VCC_EXP_12
VCC_EXP_11
VCC_EXP_10

VCC_EXP_9
VCC_EXP_8
VCC_EXP_7
VCC_EXP_6
VCC_EXP_5
VCC_EXP_4
VCC_EXP_3
VCC_EXP_2

VCC_EXP_1
VCC_DDR_22
VCC_DDR_21
VCC_DDR_20

12

C3011uFC0603

C3011uFC0603

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

2

1D25V_MCH

BC16
AN15

R2510R251

R295

12

0

C59510uFC0805

C59510uFC0805

2

1D25V_MCH

1D25V_MCH

1D8V_STR

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

R295
0

0

dummy

dummy

TP22TP22
TP23TP23
TP2TP2

Place in FSB_VTT plane as close to the GMCH as possible
(less than 100 mils from the package)

1D8V_STR

12

*

*

12

*

*

C29710uFC0805

C29710uFC0805

12

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

12

*

*

Place in the PCI-E power plane
(less than 100 mils from the package)

FSB_VTT

12

C2162.2uFC0603

C2162.2uFC0603

*

*

*

*

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

Connect ground sides of caps with traces to GND balls
(less than 100 mils from the package)

12

12

C3412.2uF

C3412.2uF

C3482.2uF

C3482.2uF

*

*

*

*

C0603

C0603

C0603

C0603

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

12

12

C3472.2uF

C3472.2uF

C3462.2uF

C3462.2uF

*

*

*

*

C0603

C0603

C0603

C0603

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

1D25V_MCH

12

*

*

Place in 1D25V_MCH_CL plane
(less than 100 mils from the package)

Title

Title

Title

Bearlake GMCH -4

Bearlake GMCH -4

Bearlake GMCH -4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

AY37
BB29
BB34
AW32

BC43
BC1
A43

N20
B2
B42
B43
BB1
BB2
BB43
BC2
BC42

Y31
Y30
Y29

AL9
AL8
AL7
AL6
AL5
AL29
AL27
AL26
AL24
AL23
AL21
AL20
AL18
AL17
AL15
AL13
AL12
AL11
AL10
AK30
AK3
AK29
AK27
AK26

AD9
AD8
AD7
AD6
AD5
AD4
AD2
AD11
AD10
AD1
AC4
AC3
AC2
BC39
BC34
BC30

V30

VSS

1D25V_MCH1D25V_MCH1D25V_MCH

*

*

1

12

C60010uFC0805

C60010uFC0805

C24010uFC0805

C24010uFC0805

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

12

12

C2092.2uFC0603

C2092.2uFC0603

C2032.2uFC0603

C2032.2uFC0603

*

*

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

C3452.2uF

C3452.2uF

C0603

C0603

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

C3442.2uF

C3442.2uF

GMCH Memory Decoupling

C0603

C0603

6.3V, Y5V, +80%/-20%

6.3V, Y5V, +80%/-20%

12

C31410uFC0805

C31410uFC0805

C31310uFC0805

C31310uFC0805

*

*

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

10V, Y5V, +80%/-20%

FOXCONN PCEG

FOXCONN PCEG

FOXCONN PCEG

G33M03

G33M03

G33M03

1

CC

CC

CC

of

of

of

11 37Thursday, April 26, 2007

11 37Thursday, April 26, 2007

11 37Thursday, April 26, 2007

5

1D8V_STR

EC34

*

*

*

*

EC34

470uF

470uF

16V, +/-20%

16V, +/-20%

ce35d80h125

ce35d80h125

EC43

EC43

470uF

470uF

16V, +/-20%

16V, +/-20%

ce35d80h125

ce35d80h125

EC42

EC42

470uF

470uF

*

*

16V, +/-20%

16V, +/-20%

ce35d80h125

ce35d80h125

D D

1D8V_STR

EC32

EC32

470uF

470uF

*

*

16V, +/-20%

16V, +/-20%

ce35d80h125

ce35d80h125

Place between Ch A DIMM II
and Ch B DIMM 1

1D8V_STR

EC27

EC27

470uF

470uF

*

*

16V, +/-20%

16V, +/-20%

ce35d80h125

ce35d80h125

*

*

EC33

EC33

470uF

470uF

16V, +/-20%

16V, +/-20%

ce35d80h125

ce35d80h125

Place between GMCH and DIMM

C C

B B

A A

1D8V_STR

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

C412 1uF

C412 1uF

*

*

10V, Y5V, +80%/-20%C0603

10V, Y5V, +80%/-20%C0603

Channel A DIMM 1 1.8V high-frequency decoupling caps.
place as close to DIMM power pins as possible

M_BS_A[2..0]9,13

M_SCKE_A[3..0]9,13

CK_M_200M_N_DDR2_A9
CK_M_200M_P_DDR2_A9 CK_M_200M_P_DDR5_A9
CK_M_200M_N_DDR1_A9
CK_M_200M_P_DDR1_A9
CK_M_200M_N_DDR0_A9
CK_M_200M_P_DDR0_A9

M_BS_A[2..0]9,13

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

*

*

10V, Y5V, +80%/-20%C0603

10V, Y5V, +80%/-20%C0603

SMB_CLK_RESUME14,16,17,19,25,26,27,29

SMB_DATA_RESUME14,16,17,19,25,26,27,29

M_MAA_A[14..0]9,13

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

C410 1uF

C410 1uF

C411 1uF

C409 1uF

C409 1uF

C411 1uF

*

*

*

*

10V, Y5V, +80%/-20%C0603

10V, Y5V, +80%/-20%C0603

10V, Y5V, +80%/-20%C0603

10V, Y5V, +80%/-20%C0603

SMVREF_A

M_BS_A1
M_BS_A0

M_SCS_A1J9,15
M_SCS_A0J9,15

M_BS_A2

M_CAS_AJ9,13
M_RAS_AJ9,13
M_WE_AJ9,13

5

1D8V_STR 1D8V_STR

3D3V_SYS 3D3V_SYS

SA2 SA1 SA0
0 0 0

M_SCKE_A1
M_SCKE_A0

M_MAA_A0
M_MAA_A1
M_MAA_A2
M_MAA_A3
M_MAA_A4
M_MAA_A5
M_MAA_A6
M_MAA_A7
M_MAA_A8
M_MAA_A9
M_MAA_A10
M_MAA_A11
M_MAA_A12
M_MAA_A13
M_MAA_A14

DIMM1

DIMM1

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

50

VSS

65

VSS

66

VSS

79

VSS

82

VSS

85

VSS

88

VSS

91

VSS

94

VSS

97

VSS

100

VSS

103

VSS

106

VSS

109

VSS

112

VSS

115

VSS

118

VSS

121

VSS

124

VSS

127

VSS

130

VSS

133

VSS

136

VSS

139

VSS

142

VSS

145

VSS

148

VSS

151

VSS

154

VSS

157

VSS

160

VSS

163

VSS

166

VSS

169

VSS

198

VSS

201

VSS

204

VSS

207

VSS

210

VSS

213

VSS

216

VSS

219

VSS

222

VSS

225

VSS

228

VSS

231

VSS

234

VSS

237

VSS

51

VDDQ

56

VDDQ

62

VDDQ

72

VDDQ

75

VDDQ

78

VDDQ

191

VDDQ

194

VDDQ

181

VDDQ

175

VDDQ

170

VDDQ

53

VDD

59

VDD

64

VDD

197

VDD

69

VDD

172

VDD

187

VDD

184

VDD

178

VDD

189

VDD

67

VDD

18

RC1

55

RC0

238

VDDSPD

1

VREF

120

SCL

119

SDA

101

SA2

240

SA1

239

SA0

190

BA1

71

BA0

171

CKE1

52

CKE0

76

S1#

193

S0#

221

CK2#/RFU

220

CK2/RFU

138

CK1#/RFU

137

CK1/RFU

186

CK0#

185

CK0

188

A0

183

A1

63

A2

182

A3

61

A4

60

A5

180

A6

58

A7

179

A8

177

A9

70

A10/AP

57

A11

176

A12

196

A13

174

A14

173

A15

54

A16/BA2

74

CAS#

192

RAS#

73

WE#

DDR2_DIMM

DDR2_DIMM

CONN,DIMM,DDR II,1.8V,V/T,Blu,G/F,G,DIP-240

CONN,DIMM,DDR II,1.8V,V/T,Blu,G/F,G,DIP-240
DDR240H260

DDR240H260

4

NC_1

NC/TEST

NC_2

ODT1
ODT0

CB<0>
CB<1>
CB<2>
CB<3>
CB<4>
CB<5>
CB<6>
CB<7>

DQS<0>

DQS#<0>

DQS<1>

DQS#<1>

DQS<2>

DQS#<2>

DQS<3>

DQS#<3>

DQS<4>

DQS#<4>

DQS<5>

DQS#<5>

DQS<6>

DQS#<6>

DQS<7>

DQS#<7>

DQS<8>

DQS#<8>

DM0/DQS9

NC/DQS9#

DM1/DQS10
NC/DQS10#

DM2/DQS11
NC/DQS11#

DM3/DQS12
NC/DQS12#

DM4/DQS13
NC/DQS13#

DM5/DQS14
NC/DQS14#

DM6/DQS15
NC/DQS15#

DM7/DQS16
NC/DQS16#

DM8/DQS17
NC/DQS17#

DQ<0>
DQ<1>
DQ<2>
DQ<3>
DQ<4>
DQ<5>
DQ<6>
DQ<7>
DQ<8>

DQ<9>
DQ<10>
DQ<11>
DQ<12>
DQ<13>
DQ<14>
DQ<15>
DQ<16>
DQ<17>
DQ<18>
DQ<19>
DQ<20>
DQ<21>
DQ<22>
DQ<23>
DQ<24>
DQ<25>
DQ<26>
DQ<27>
DQ<28>
DQ<29>
DQ<30>
DQ<31>
DQ<32>
DQ<33>
DQ<34>
DQ<35>
DQ<36>
DQ<37>
DQ<38>
DQ<39>
DQ<40>
DQ<41>
DQ<42>
DQ<43>
DQ<44>
DQ<45>
DQ<46>
DQ<47>
DQ<48>
DQ<49>
DQ<50>
DQ<51>
DQ<52>
DQ<53>
DQ<54>
DQ<55>
DQ<56>
DQ<57>
DQ<58>
DQ<59>
DQ<60>
DQ<61>
DQ<62>
DQ<63>

4

3

68
102
19

M_ODT_A1

77

M_ODT_A0

195

42
43
48
49
161
162
167
168

7
6

M_DQS_AJ0

16
15

M_DQS_AJ1

28
27

M_DQS_AJ2

37
36

M_DQS_AJ3

84
83

M_DQS_AJ4

93
92

M_DQS_AJ5

105
104

M_DQS_AJ6

114
113

M_DQS_AJ7

46
45

M_DQM_A0

125
126

M_DQM_A1

134
135

M_DQM_A2

146
147

M_DQM_A3

155
156

M_DQM_A4

202
203

M_DQM_A5

211
212

M_DQM_A6

223
224

M_DQM_A7

232
233

164
165

M_DATA_A0

3

M_DATA_A1

4

M_DATA_A2

9

M_DATA_A3

10

M_DATA_A4

122

M_DATA_A5

123
128

M_DATA_A7

129

M_DATA_A8

12

M_DATA_A9

13

M_DATA_A10

21

M_DATA_A11

22

M_DATA_A12

131

M_DATA_A13

132

M_DATA_A14

140

M_DATA_A15

141

M_DATA_A16

24

M_DATA_A17

25

M_DATA_A18

30

M_DATA_A19

31

M_DATA_A20

143

M_DATA_A21

144

M_DATA_A22

149
150

M_DATA_A24

33

M_DATA_A25

34

M_DATA_A26

39

M_DATA_A27

40

M_DATA_A28

152

M_DATA_A29

153

M_DATA_A30

158

M_DATA_A31

159

M_DATA_A32

80

M_DATA_A33

81

M_DATA_A34

86

M_DATA_A35

87

M_DATA_A36

199

M_DATA_A37

200

M_DATA_A38

205

M_DATA_A39

206

M_DATA_A40

89

M_DATA_A41

90

M_DATA_A42

95

M_DATA_A43

96

M_DATA_A44

208

M_DATA_A45

209

M_DATA_A46

214

M_DATA_A47

215

M_DATA_A48

98

M_DATA_A49

99

M_DATA_A50

107

M_DATA_A51

108

M_DATA_A52

217

M_DATA_A53

218

M_DATA_A54

226

M_DATA_A55

227

M_DATA_A56

110

M_DATA_A57

111

M_DATA_A58

116

M_DATA_A59

117

M_DATA_A60

229

M_DATA_A61

230

M_DATA_A62

235

M_DATA_A63

236

M_DQS_A0

M_DQS_A1

M_DQS_A2

M_DQS_A3

M_DQS_A4

M_DQS_A5

M_DQS_A6

M_DQS_A7

M_ODT_A[3..0] 9,13,15

M_DATA_A[63..0] 9

M_BS_A[2..0]9,13

M_BS_A[2..0]9,13

M_SCKE_A[3..0]9,13

CK_M_200M_N_DDR5_A9
CK_M_200M_N_DDR4_A9

CK_M_200M_P_DDR4_A9
CK_M_200M_N_DDR3_A9
CK_M_200M_P_DDR3_A9

M_DQS_AJ[7..0] 9

M_DQS_A[7..0] 9

M_DQM_A[7..0] 9

M_MAA_A[14..0]9,13

SMB_CLK_RESUME
SMB_DATA_RESUME

3

SMVREF_A

M_BS_A1
M_BS_A0

M_SCS_A3J9,13
M_SCS_A2J9,15

M_BS_A2

M_CAS_AJ9,13
M_RAS_AJ9,13
M_WE_AJ9,13

SA2 SA1 SA0
0 0 1

M_SCKE_A3
M_SCKE_A2

M_MAA_A0
M_MAA_A1
M_MAA_A2
M_MAA_A3
M_MAA_A4
M_MAA_A5
M_MAA_A6
M_MAA_A7
M_MAA_A8
M_MAA_A9
M_MAA_A10
M_MAA_A11
M_MAA_A12
M_MAA_A13
M_MAA_A14

DIMM2

DIMM2

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

50

VSS

65

VSS

66

VSS

79

VSS

82

VSS

85

VSS

88

VSS

91

VSS

94

VSS

97

VSS

100

VSS

103

VSS

106

VSS

109

VSS

112

VSS

115

VSS

118

VSS

121

VSS

124

VSS

127

VSS

130

VSS

133

VSS

136

VSS

139

VSS

142

VSS

145

VSS

148

VSS

151

VSS

154

VSS

157

VSS

160

VSS

163

VSS

166

VSS

169

VSS

198

VSS

201

VSS

204

VSS

207

VSS

210

VSS

213

VSS

216

VSS

219

VSS

222

VSS

225

VSS

228

VSS

231

VSS

234

VSS

237

VSS

51

VDDQ

56

VDDQ

62

VDDQ

72

VDDQ

75

VDDQ

78

VDDQ

191

VDDQ

194

VDDQ

181

VDDQ

175

VDDQ

170

VDDQ

53

VDD

59

VDD

64

VDD

197

VDD

69

VDD

172

VDD

187

VDD

184

VDD

178

VDD

189

VDD

67

VDD

18

RC1

55

RC0

238

VDDSPD

1

VREF

120

SCL

119

SDA

101

SA2

240

SA1

239

SA0

190

BA1

71

BA0

171

CKE1

52

CKE0

76

S1#

193

S0#

221

CK2#/RFU

220

CK2/RFU

138

CK1#/RFU

137

CK1/RFU

186

CK0#

185

CK0

188

A0

183

A1

63

A2

182

A3

61

A4

60

A5

180

A6

58

A7

179

A8

177

A9

70

A10/AP

57

A11

176

A12

196

A13

174

A14

173

A15

54

A16/BA2

74

CAS#

192

RAS#

73

WE#

DDRII

DDRII

CONN,DIMM,DDRII,1.8V,1mm,V/T,Yel,G/F,G,DIP-240

CONN,DIMM,DDRII,1.8V,1mm,V/T,Yel,G/F,G,DIP-240
ddr240h260

ddr240h260

2

NC_1

NC/TEST

NC_2

ODT1
ODT0

CB<0>
CB<1>
CB<2>
CB<3>
CB<4>
CB<5>
CB<6>
CB<7>

DQS<0>

DQS#<0>

DQS<1>

DQS#<1>

DQS<2>

DQS#<2>

DQS<3>

DQS#<3>

DQS<4>

DQS#<4>

DQS<5>

DQS#<5>

DQS<6>

DQS#<6>

DQS<7>

DQS#<7>

DQS<8>

DQS#<8>

DM0/DQS9
NC/DQS9#

DM1/DQS10

NC/DQS10#

DM2/DQS11

NC/DQS11#

DM3/DQS12

NC/DQS12#

DM4/DQS13

NC/DQS13#

DM5/DQS14

NC/DQS14#

DM6/DQS15

NC/DQS15#

DM7/DQS16

NC/DQS16#

DM8/DQS17

NC/DQS17#

DQ<0>
DQ<1>
DQ<2>
DQ<3>
DQ<4>
DQ<5>
DQ<6>
DQ<7>
DQ<8>

DQ<9>
DQ<10>
DQ<11>
DQ<12>
DQ<13>
DQ<14>
DQ<15>
DQ<16>
DQ<17>
DQ<18>
DQ<19>
DQ<20>
DQ<21>
DQ<22>
DQ<23>
DQ<24>
DQ<25>
DQ<26>
DQ<27>
DQ<28>
DQ<29>
DQ<30>
DQ<31>
DQ<32>
DQ<33>
DQ<34>
DQ<35>
DQ<36>
DQ<37>
DQ<38>
DQ<39>
DQ<40>
DQ<41>
DQ<42>
DQ<43>
DQ<44>
DQ<45>
DQ<46>
DQ<47>
DQ<48>
DQ<49>
DQ<50>
DQ<51>
DQ<52>
DQ<53>
DQ<54>
DQ<55>
DQ<56>
DQ<57>
DQ<58>
DQ<59>
DQ<60>
DQ<61>
DQ<62>
DQ<63>

2

1

68
102
19

M_ODT_A3

77

M_ODT_A2

195

42
43
48
49
161
162
167
168

M_DQS_A0

7

M_DQS_AJ0

6

M_DQS_A1

16

M_DQS_AJ1

15

M_DQS_A2

28

M_DQS_AJ2

27

M_DQS_A3

37

M_DQS_AJ3

36

M_DQS_A4

84

M_DQS_AJ4

83

M_DQS_A5

93

M_DQS_AJ5

92

M_DQS_A6

105

M_DQS_AJ6

104

M_DQS_A7

114

M_DQS_AJ7

113
46

45

M_DQM_A0

125
126

M_DQM_A1

134
135

M_DQM_A2

146
147

M_DQM_A3

155
156

M_DQM_A4

202
203

M_DQM_A5

211
212

M_DQM_A6

223
224

M_DQM_A7

232
233

164
165

M_DATA_A0

3

M_DATA_A1

4

M_DATA_A2

9

M_DATA_A3

10

M_DATA_A4

122

M_DATA_A5

123

M_DATA_A6M_DATA_A6

128

M_DATA_A7

129

M_DATA_A8

12

M_DATA_A9

13

M_DATA_A10

21

M_DATA_A11

22

M_DATA_A12

131

M_DATA_A13

132

M_DATA_A14

140

M_DATA_A15

141

M_DATA_A16

24

M_DATA_A17

25

M_DATA_A18

30

M_DATA_A19

31

M_DATA_A20

143

M_DATA_A21

144

M_DATA_A22

149

M_DATA_A23M_DATA_A23

150

M_DATA_A24

33

M_DATA_A25

34

M_DATA_A26

39

M_DATA_A27

40

M_DATA_A28

152

M_DATA_A29

153

M_DATA_A30

158

M_DATA_A31

159

M_DATA_A32

80

M_DATA_A33

81

M_DATA_A34

86

M_DATA_A35

87

M_DATA_A36

199

M_DATA_A37

200

M_DATA_A38

205

M_DATA_A39

206

M_DATA_A40

89

M_DATA_A41

90

M_DATA_A42

95

M_DATA_A43

96

M_DATA_A44

208

M_DATA_A45

209

M_DATA_A46

214

M_DATA_A47

215

M_DATA_A48

98

M_DATA_A49

99

M_DATA_A50

107

M_DATA_A51

108

M_DATA_A52

217

M_DATA_A53

218

M_DATA_A54

226

M_DATA_A55

227

M_DATA_A56

110

M_DATA_A57

111

M_DATA_A58

116

M_DATA_A59

117

M_DATA_A60

229

M_DATA_A61

230

M_DATA_A62

235

M_DATA_A63

236

M_ODT_A[3..0] 9,13,15

1D8V_STR

R410

R410

1K

1K

+/-1%

+/-1%

SMVREF_A

R411

R411

C428

C428

1K

1K

0.1uF

0.1uF

*

*

+/-1%

+/-1%

25V, Y5V, +80%/-20%

25V, Y5V, +80%/-20%

C0603

C0603

close to DIMM pin
Width 10 mils minimum, Spacing 10 mils minimum.

1D8V_STR

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

CAP,1uF,+80%/-20%,Y5V,10V,G,SMD0603

10V, Y5V, +80%/-20%C0603

10V, Y5V, +80%/-20%C0603

Channel A DIMM II 1.8V high-frequency decoupling caps.
place as close to DIMM power pins as possible

Title

Title

Title

DDR2 Channel A DIMM 1, 2

DDR2 Channel A DIMM 1, 2

DDR2 Channel A DIMM 1, 2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

*

*

C452 1uF

C452 1uF

*

*

10V, Y5V, +80%/-20%C0603

10V, Y5V, +80%/-20%C0603

G33M03

G33M03

G33M03

C432 1uF

C432 1uF

10V, Y5V, +80%/-20%C0603

10V, Y5V, +80%/-20%C0603

FOXCONN PCEG

FOXCONN PCEG

FOXCONN PCEG

1

C431 1uF

C431 1uF

C427 1uF

C427 1uF

*

*

*

*

10V, Y5V, +80%/-20%C0603

10V, Y5V, +80%/-20%C0603

of

of

of

12 37Thursday, April 26, 2007

12 37Thursday, April 26, 2007

12 37Thursday, April 26, 2007

CC

CC

CC