Fluke 9000A-Z80QT Instruction Manual

9000A-Z8OQT

INTERFACE

POD

N

P/ March

All

rights

859447

1989

John

reserved.

Fluke

Mfg.

Litho

Co..

in

Inc.

U.S.A.

Instruction

Manual

LU

F

K

E

COVERAGE

WARRANTY

Fluke

warrants under This

warranty

product

of

operation.

Fluke’s

product provided

failure

if

the

warranty

repair

normal

has

cost.

this

use

extends

that

has been

obligations

is

that

returned

thatwedetermine

been caused

period

SERVICE

If

failure

a

with

will

occurs,

a description

be

returned,

transportation prepaid.

DISCLAIMER

THE FOREGOING WARRANTIES,

IMPLIED PARTICULAR SPECIAL,

OR OTHERWISE.

TORT,

GETTING

EXPRESS

WARRANTY

PURPOSE

INCIDENTAL,

ANSWERS

from

interface

and service

only

misused,

under

to

an

misuse, alteration,

by

has

expired, we

send

the

of

the

difficulty.

pod

to

this

that

product,

free

to

be

for

a periodofone

the

original purchaser

altered,

warranty

has been

or

are

authorized Service Center

the

product

will

repair

postage

will

Repairs

Fluke

WARRANTYISEXCLUSIVE

OR

OF

IMPLIED,

MERCHANTABILITY,FITNESS,

OR

OR CONSEQUENTIAL

USE. FLUKE

AND

INCLUDING BUT

ADVICE

in

defects

limited

is

defective.

abnormal conditions

or

the

prepaid,

be made

assumes

SHALL

DAMAGES,

material

from

(1)

year

and

does

subjected

ANDINLIEU

to

repairorreplacementofa

within

If

we

bill

and

pod

the

to

closest

the

or

product

NO

risk for

NOT

OR ADEQUACY

NOT

BE

WHETHER

and

workmanship

of

date

the

not

shipment.

apply

to

any

abnormal conditions

the

warranty

determine

you

damage

OF

LIMITEDTOANY

LIABLE

that

of

operation,or

for

reasonable

Service

replaced,

in

ALL

OTHER

FOR

IN

CONTRACT,

period,

Center

and

transit.

ANY ANY

the

it

To

enhance

its

applications

INC.,

P.O.

JOHN

FLUKE

your

BOX

use

and

09090,

MFG.

of

this

Address

use.

EVERETT,

INC.,

CO.,

Fluke

pod,

all

WASHINGTON,

PO.

will

be

happy

correspondence

BOX

09090,

to

answer

to:

98206,

EVERETT,

questions

your

JOHN FLUKE

ATTN:

Sales

WASHINGTON

about

MFG.

CO.,

Department.

98206

ZBOQT

SECTION

1

2

3

TITLE

INTRODUCTION

1-1.

PURPOSEOFINTERFACEPOD

1-2,

DESCRIPTIONOFINTERFACE

1-3.

SPECIFICATIONS

INSTALLATION

INSTALLING

2-1.

(9100 MAKING CONNECTIONS

2-2. 2-3.

POWER

SIGNALS

POD

3-1.

INTRODUCTION

3-2.

280 SIGNALS

3-3.

STATUS/CONTROL SPACE

3—4.

3-5. 3-6. 3-7. 3-8. 3-9. 3-10. 3-11.

3—12.‘

3-13.

34—14.

3—l5.

3-16.

347.

Introduction

Bit User-Writable

Bit

Address

FORCING

LINES ENABLED NON—DETECTABLE QUICK-LOOPING

Using Read and

QUICK

Quick Quick

...................................

.....................................

SERIES

THE

ONLY)

CONNECTIONS

AND

FUNCTIONS

................................

ASSIGNMENT

................................

Assignment

the 9000

the 9100 Series for

MEMORY

RAM ROM

—

Control

A

Assignment

Space

AND

INTERRUPT

Series

Write

..............................

Write

..............................

Test Test

Table

of

Contents

................

POD

............

............................

DATABASE

Z80QT

..........................

......................

.......................

......................

.............................

LINES AND

ADDRESS

........................

Lines

Status

Lines

Control

DURING MAINFRAME

280

READ

for

TESTS Description Description

1'

..................

....................

Lines

.................

.....................

LINES

.............

SIGNALS

AND

WRITE

Quick-Looping

SETUP

...............

FUNCTIONS

......................

...................

(vomimzed

PAGE

1-1

1-2

2-1

2-1 2-1

2-2

3-1

3—4

3-4 3-4

3—4

3-5

3—5

3-6

3-7

.

3-7

3—7

3-8

3-8 3-9 3-9 3-10

on

ii)

page

Z8OQT

TABLE

OF

CONTENTS,

(continued)

SECTION

TITLE

3-18. 3-19.

3—20.

3—21.

3—22.

3—23.

3-24. 3-25.

3—26

3-27.

3—28.

3—29.

3-30. Clock

3-31.

3-32.

THEORY OF OPERATION

4-].

4-2.

4—3.

4-3. 4-4. UUT Interface 4-5.

4-6. 4-7.

DETAILED

4—8.

4—9.

4-10. UUT 4-11. UUT Interface 4-12. UUT 4-13.

MAINTENANCE

5—1.

INTRODUCTION

5—2.

SELF TEST

5-3.

REPAIR

5—4.

TROUBLESHOOTING

5-5.

5—6.

5—7.

5—8.

5-13.

5-l4.

DISASSEMBLY

the

Using Using Using Using

QUICK

Using Using

MARGINAL

Introduction

UUT UUT Bus

POD DRIVE POWER

INTRODUCTION GENERAL

Processor Section Processor Section

Timing UUT Power

Processor

UUT Interface Section

Timing

9000 Series the 9000 the 9100 the 9100 Series for

AND VERIFY

FILL

the 9000 the

9100

OUT

................................

Operating Noise

Levels

Loading

Interface Section

................................

Loading

CAPABILITY

FAILURE DETECTION

POD OPERATION

Section

Sensing

BLOCK

Section

Interface

Section

....................................

..................................

PRECAUTIONS

Introduction

Defective

Pod Selecting Troubleshooting TroubleshootinganInoperative

................................

or

UUT

a

for

Series for

for

Series

for

Series for

PROBLEMS

and

Speed

RAM ROM RAM ROM

Fill Fill

and and

Testing

Testing Testing Testing

Verify Verify

Quick Quick Quick Quick

.....................

Quick Quick

..................

Memory

Access

........

.......

......

............................

..............................

.....................

LIMITS

.........

............................

.............................

...................

............................

Section

........................

..............................

..........................

DIAGRAM DESCRIPTION

............................

General Section Section

7 7

—

7

Data

Address

Status

................

Lines

.............

Lines

...........

and Control

Lines

..............................

.............................

......................

.........................

Inoperative?

for

Pod

Defective

a

...................

Testing

.................

Pod

.................

Pod

..............

..............................

. . . .

.

PAGE

3-10

3—13

3-15

3-15 3-16

3-16 3-17

3-19

3—19

3-19

3—19

3-19

3-20 3-20

3—20

4-1

4-1 4-1 4-1 4-1

4-4 4-4

4-5

4—8

4—9

4-12

4—12

.

4-13

5—1

5—l

5-1

5—4

5-4

5—4

5—5

5-7

5—8

5-14

5-19

ii

(continued

on

iii)

page

Z8OQT

TABLE

SECTION

6

7

APPENDIX

OF

CONTENTS,

LIST

6-1. 6-2.

SCHEMATIC

(continued)

REPLACEABLE

OF

INTRODUCTION

HOW TO

DIAGRAMS

A

THE

USING

TITLE

OBTAIN

Z8OQT

PARTS

.......................

.............................

PARTS

......................

.............................

POD FROM

PROGRAMS

TL/l

PAGE

6-1

6—1

7-1

A-1

iii

/iv

List

of

Tables

ZSOQT

TABLE

1.[_

3-l.

3-2_

3-3. 3-4, 3-5. 3-6,

5-l.

5-2.

5-3.

5-4.

5—5l

Interface

Z80QT Z80

Signals

Status

Quick—Looping Quick Quick Quick

Test

Self Required

Recreating

ZSOQT

............................................

Control

and

Test Addresses

RAM

Test Addresses

ROM

Fill

and

Failure

Test

Self Test Pod‘Memory Interface

Pod

Specifications

Lines Bit

and Write

Read

Addresses

Verify

Codes

Equipment

Routines

and

Pod

Quick

TITLE

.......................

Assignments

Test

and

Status

and

Status

and Status

..................

Addresses

Codes

...............

Codes

...............

Code

..............

............

...................................

................................

..........................

O Addresses

1/

ROM

...................

Checksum

.............

PAGE

1-4 3-1

3-6 3-8 3-12

3-14

3-18 5-3

5-5

5-9

5-l7

5—17

Z8OQT

List

of

Illustrations

FIGURE

1—1.

2—1.

2-2. 2-3. 3-1.

4—1.

c2.

4—3.

44.

5—1.

5-2.

5-3.

TITLE

Relationship Connection of Interface Connection of Interface

ConnectionofInterface Pod 280 Pin

General

Detailed

Handshaking

UUT ON

Interface

Troubleshooting

of Interface Pod

Assignments

Block

Diagram

Block

Diagram

Signals

and Latch

Signal

PCB,

Non—Component

a

an

Pod

Podto9100

.....................................

Defective Pod

Inoperative

.............................

Series

9000

to

UUT

to

................

Series

................

.......................

..................................

Times

.........................

Side

......................

..........................

Pod

.......................

PAGE

1-3 2-3 2-3

2-4 3-3

4-2 4-6 4-10

4-11

5-6

5-”

5—16

vi

ZBOQT

PURPOSE

1-1. The

9000A-280QT

9000

any

of

piece

9000

The

designed

are

that

use

purpose

processor specific handling,

Appendix

Test

Systems

Series

or

equipment

Series

Digital

to

test

bus-oriented architecture

family.

functions

timing,

A

contains

in

TL/l

INTERFACE

OF

Interface

9100

that

and

of

The

such

size

Pod

Series

tester

a

uses

Troubleshooters

service

microprocessors.

mainframe

the

interface

pin layout,

as

of

memory space,

informationabout

programs.

POD

(hereafter

Z80

microprocessor.

circuit

printed

pod adapts

referred

9100 Series

and

boards,instruments,

The interface

to

specific

a

the

status/

and

using

mainframe

control

size

of

this

pod

microprocessor

I/

Section

Introduction

to

pod

0

with

as as

space.

the

Digital

adapts

to

functions,

9100

interfaces

pod)

mainframe)

Test

Systems

and

systems

the

general

micro-

or

microprocessor-

interrupt

Series

Digital

1

to

a

DESCRIPTION

1-2.

pod

consists

The

break-resistant

the

to

boards

unit

the

Figure

Connection connector.

directly the

cate

under

1—1

shows

Connection

into

mainframe

the

with

from

the

OF

a

pair

A

hereafter

the

relationship

the

pod

access

of

shielded

a

the

to

of

case.

mainframe;

test,

microprocessor

direct

microprocessor.

INTERFACE POD

circuit

printed

24-conductor

ribbon

referred

of the

the mainframe

to

UUT

socket. The UUT

all

to

system components

board

cable and

to

as

pod

is

made

the UUT.

assemblies

cable

connects

connector

mainframe

the

to

is

via

plugging

by

microprocessor

which

mounted

the

printed

the

ribbon

normally

connection

and

provide

front-mounted

a

in

a

circuit

the UUT.

to

25—pin

cable

socket

communi-

small

to

plug

gives

1-1

ZBOQT

The software

pod

contains

required

Perform

Receive

Report

Emulate

The Using designed

Logic circuits

any line).

Over-voltage These

O

is

pod

the

operating

level

allow

drive

bus

circuits

Incorrectly

socket.

UUT faults

microprocessor

The

over-voltage

pin. Multiple

one

handshaking

and

UUT

the

powered

UUT

clock

detection

detection of

conﬂict

protection

guard

protection

280

a

microprocessor

do the

to

execute

status

UUT

microprocessor

the

by

signal

speed

circuits

(two

against pod

inserting

that

place

socket.

faults,

especially

following:

with the mainframe

commands from

the

mainframe

to

mainframe,

allows the

the UUT.

of

are

or

the

provided

shorts,

more

are

damage

ribbon

drivers

also

bus

circuits

potentially

circuits

guard

of

long

and

supporting

mainframe

the

is

clocked

but

mainframe

each

on

stuck-high

or

attempting

provided on

which could

cable

plug

damaging voltages

against voltages

duration,

by

and

line

stuck-low

result from:

in

the UUT

may

each

hardware

the UUT clock

pod

to

of

cause pod

and

to

operate

UUT.

the

conditions,

drive

the

line

to

microprocessor

on

+12

-7V

to

the UUT.

the

damage.

control

same

on

signal.

the

at

These

and

bus

UUT

any

A

power level,

A self

level

power

supply (+5V).

the

test

pod

operation.

The

ribbon

operation.

the

1-3.

Specifications

1-2

is

not

pod

SPECIFICATIONS

sensing

notifies

socket The self

cable

The

ribbon

in

for

circuit

UUT

If

the

provided

test

must

plug

cable

to

provide

use

the

9000A-Z80QT

constantly

rises

power

mainframeofthe

the

on

pod

is

socket

a 40-pin

be

connected

should

plug

protection

Interface

power

the

for

the

drops

or

fail condition.

the

self

test

the

plug.

Pod

are

monitors

above

enables

zero-insertion

to

alsobeinserted

voltage

mainframetocheck

levelofthe UUT

below

force

type

socket

into

this

in

listed

acceptable

an

connector.

during

socket

Table

self

1-1.

pod

test

when

ZBOQT

2<m

5.0m

Fwy—00m

mOmmwOOmaOm—QE

m0<umwkz_

O:

m0<mmm._.2_

O\_

mmOmn.

Flgure

1-1.

Relationship

005

w§<mu2_<_2

mXDJE

m0

Doom

memw

of Interface Pod

1-3

ZSOQT

Table 1-1.

ELECTRICAL

Power

Electrical

MICROPROCESSOR

Clock

Input

Output

Output High

Trlstate Current

High

Low

BUSRQ,

ALL OTHER INPUT

PERFORMANCE

Dissipation

Protection

Low

Input

Input High

Low

Voltage

High Voltage

Low

Voltage

Leakage

Output

....................

Level

Input

WAIT,

Current

Current—

RESET,

ZSOQT

..........

........

SIGNALS

............

...........

..........

.........

........

NMI

LINES.

Intertace

Pod

3.0 watts

+12V

-7 to

and

any uouslyaslong mainframe.

0V

min.,

+4.4V

0V

min.,

+2.0V

min.,

+0.4V

max.

min.

+2.4V

,uA

$20

20

,uA

typ.

—400

pA

—20

#A

typ.

Specifications

maximum

be

may

ribbon

single

as

+0.45V

+5.0V

+0.8V

max.

+5.0V

with

Ioh

with

Vih

with

max.

Vil

with

applied

the

max.

lol

Vil

:

=

2

cable

pod

1.8

—250

+2.7V

:

+0.4v

between

plug pin

is

powered

mA

pA

+0.4V

ground

contin—

the

by

TIMING

UUT

CHARACTERISTICS

Maximum

Added

LOW-TO-HIGH

TRANSITIONS

HIGH—TO—LOW

TRANSITIONS

Detection

Clock

Delays

POWER DETECTION

of Low

of

Frequency

to

High

280

Signals

...........

Vcc

Fault

Vcc Fault.

MHz

8.0

.

20

24

Vcc

..

Vcc

.

typ.

ns

typ.

ns

typ.

+4.5V detected

<

+5.5V detected

>

ZBOQT

Table

GENERAL

Size

........................

Weight

.....................

Environmenl

STORAGE

OPERATlNG

Protecllon

Class

ZBOQT

1-1.

Interface

................

..............

3

...........

Pod

3.3

cm

Highx10.2

in

(1.3

0.68

kg (1.5

—40°

to

0°

to

+25°C,

+25°

to +40°C,

+40°

to

Relates properties

Specifications

4.0

x

High

lbs)

RH

+70°C,

RH

+50°C,

solely

RH

to insulation

defined

(cont)

Widex18.550m

cm

in

Wide

95%

<

95%

<

75%

<

45%

<

in

348.

IE0

x

7.4

or

Deep

in

Deep)

grounding

1-5/1-6

ZBOQT

INSTALLING

2-1. The

Z80QT

disk

ﬂoppy

To

install

the mainframe KEYS, The the

To

database

the

then

database

mainframe,

the

use

disk

original

USERDISK.

disk. Place

ﬂoppy

MAKING

2-2. Before test means

and next.

9000 Series

a

isolate

or

of the

ribbon-type.

one

THE

database

supplied

for the

with

database

drive.

ﬂoppy

COPY

select

needs

only

the

place

database

pod,

on

backup

a

to

the

from

time

Each

the

CONNECTIONS

or

it

fault,

a

which

Procedures

ZBOOT DATABASE

9100—Series

the

9000A-Z80QT

mainframe

a

on

Press

DISK

be

to

original

mainframe with

a

disk

floppy

mainframe

the

original floppy

9100

Series

be connectedtothe UUT.

must

is

equipped

MAIN

FROM DRl

installed

ﬂoppy

the

using

drive

disk in

tester

with

for

installing

with

and

(9100

mainframe

Pod.

hard

a

MENU

TO

Once the

once.

disk in

a

two

mainframe

insert

is

reset,

safe

a

(mainframe)

cable

two

and

Installation

SERIES

is

contained

insert

drive,

the

on

keypad,

HDR.

database

safe

place

drives,

ﬂoppy

COPqunction.

the

copy

the

database

in

place

be used

can

Connection

assemblies,

connecting

and

in

case

ONLY)

on

the

press

case

into

is

one

the

Section

3.5-inch

one

into the

disk

SOFT

press

ENTER.

is

installed

is

it

needed.

first

copy

Remove

the

system

from

read

itisneeded.

perform a

to

is

made

shielded-type

given

pod

are

2

on

the

by

Before

making

PREVENT

TO

THE

TO THERMAL ELEMENTS, MOTORS, WHICH PROCESSOR

connectionstothe

any

POSSIBLE DISCONNECT

UUT,

CONTROLLEDORPROGRAMMED

ARE

BEFORE

read the

UUT,

WARNING

HAZARDS

CONNECTING POD.

TO THE

ALL

HIGH-VOLTAGE

OR

MECHANICAL

following

OPERATOR

POWER

BY

THE UUT MICRO-

precautions:

OR DAMAGE

SUPPLIES,

ACTUATORS

ZBOQT

Be

processor

The self

not

into this

Connect the

1.

2.

shown Secure the

3.

4.

5.

6.

from

7.

that

socket. Insert the

to

sure

test

insert

socket.

pod

Remove

Using

in

Apply

Perform

With

the

On

the

self

Align

the

notched

install

the

socket.

is

socket

microprocessor

any

between

power

the

round

2-1

Figure

connector

to

power

self—test

a

UUT

power

turn

pod,

socket.

test

the

ribbon-cable

corner

plug

ribbon

intended

mainframe

the

from

shielded

(for

using

mainframe.

the

of

off,

the self

ofthe

into

cable

for

removed

the

UUT.

cable,

9000

Series)orFigure

the

sliding

the

pod as

unplug

test

with the

ribbon

socketasshown

the

correctly

plug

the

with

use

from

UUT

the

and

Remove

connect

described

the

socket

microprocessor

the

collar.

microprocessor

thumbwheel

cable

plug

ribbon

UUT,

a

power

pod

in

Section

in

follows:

as

from

to

2-2

socket

aligns

Figure

the UUT

cable or

any

the

(for

5

ofthis

from

release the

to

on

with

micro-

plug only.

other

mainframe.

mainframe

9100

Series).

manual.

the

UUT.

the UUT

1

2-3.

Do

device

plug

so

the

of

as

2-3. The external

2—2

8.

Make

in

order

9.

POWER

pod

power

Electrically

mainframe

sure

to

activate

Apply

power

CONNECTIONS

receives

connections

reassemble

pod

the

to

+5

volts,-5volts,

the

CAUTION

power

protection

mainframe

required.

are

UUT. Use

is

before

on

and

+12

extender

turning

circuits.

the UUT.

volts from the

boards

UUT

power

mainframe. No

if

necessary.

on

Z8OQT

POD

Figure

CONNECTS

2-2.

Figure

2-1.

Conneclion oi Interface Pod

HERE

Connectionoilnterlace Pod

9000

to

Series

9100

to

Series

ZBOQT

Figure

2-3.

Connection

0!

Interface

Pod

UUT

to

ZBOQT

INTRODUCTION

3-1.

section

This

information.

explanations

pod

other

3-2.

For

description

have

may

characteristics.

pod

Z80

reference,

SIGNAL

Address Lines

A15

A0

-

lines

Data

DO

D7

-

is

reference

a

Information

of

status/control

normal

on

SIGNALS

Table

of each.

NAME

Pod

source

in

this

UUT

3-1

lists

3-1

Figure

Table

16

The

address lines

The logic impedance the

high

280tocontrol

the

(Direct

8

The

lines

data placed

operations.

W

The

instruction-fetch

low

during

280

the

lORQ

Signals

for

section

lines

operation,

all

shows the

3-1.

address

high,

impedance

Memory

data

in

line is

acknowledges an interrupt,

are

pod—specific

Z80QT

includes

and address

pod

of

the

Z80

280

Slgnals

DESCRIPTION

lines

are

low,

logic

The

state.

Access)

lines

are

tri-state bi-directional

are

the

high

BUSRQ.

See

control

a

cycle.

instruction-fetch

the

low.

driven

and

descriptions

space

capabilities

signals

assignment

designated

are

tri-state

floated

or

Z80

places

allow

to

state

address

the

operations.

designated

impedance

line

which

The

Functions

and 280

assignment,

and

of

Z80

A0

outputs

the

by

the

address

devices

bus

See

DO

through

lines,

state

identifies

280

places

cycle.

Section

microprocessor

of

Z80

signals,

effects

limitations,

provides

throughA15.

and

Z80

during

bothWand

signals.

may

to

a

lines

otherthan

DMA

BUSRQ.

D7.

which

DMA

the

W

at

logic

when

Also,

a

high

The

are

Z80

3

the

and

brief

be

in

3—1

ZBOQT

SIGNAL

NAME

Table

3-1.

280

Signals

(cont)

DESCRIPTION

MREQ Line

W—Fl

Line

RFSH

HALT Line

AIT Line

WT

and

N

Lines

3

MREQ

The operation

low

logic addition, during

The progress.

contain used

during

MREQ

DMA

IOFlQ

When

valid

a

in

conjunction

acknowledge.

lines

both

rupt, low.

725

The

or

is

ready

memory

IORQ line.

output

to or an

impedance

BUSRQ.

The

is

memory or

output

W

to

ready

or an

IORQ line.

impedance

BUSRQ.

RFSH

The

in

used dynamic

MREQ

refresh

The execution the order

The logic During

extend logic

The

interrupt

disabled The which

conjunction

memories.

signal

dynamic

HALT

280

continuously

maintain

to

WAlT

low

level,

the

selecting

W

of

and the

W

cannot

of

line

output

in

progress.

any memory

is

operations.

output

lORQ is

l/O

When the 280

are

is

pulled

read

data

l/O

device,

In

addition,

state

is

pulled

data

write

l/O

device,

ln

addition,

state

output

and address

memories.

output

halt

a

memory

is

line

an input

causes

wait

state,

time

cycle

the

is

an

280

the

BUSRQ line

is

line

a

disabled.

be

identifies

The 280

in

placed

See

identifies

low,

address.

port

with

the

low.

driven

low

via

the data as

Fl_D

low

via

asﬂantified

control

a

DMA'

the data

WR is DMA

during

is

with the

RFSH is

When

lines

is

pulled

instruction.

executes

refresh

which,

Z80

the

280

the

required

as

wait

state.

which

input

as

long

non-maskable

a

memory

places

operation.

access

impedance

high

a

BUSRQ.

l/O

The

line

operation

lines A0

IORQ

as

an

any

address

W

acknowledges

to

indicatethat

lines

is

by

placed

from

the

identified

operations.

indicate

to

that

linestoeither

the

by

placedina

operations.

which

signal

MREQ

line

pulled

A7

A0

-

may

low

following

the halt

During

NOP

instruction

a

activity.

when

placed

to enter

inserts

as interrupts are

is

wait

a

clock

the

by

permits

at

not

a

interrupt input

access

MREQ

is

line

interrupt

an

the

either

MREQ

in

a high

the

MREQ

may

refresh

to

low

used

be

pulses

external

logic

state

A15

-

also

inter-

280

See

280

high

See

the

state,

at

state.

not

low.

at

In

in

be

to

in

a

to

SIGNAL

RESET

BUSRQ

BUSAK

NAME

Line

A11

A12

A13

A14

A15

D4

DS

3-1.

Table

280

Slgnals

DESCRIPTION

RESET line

The

low

logic registers

line,

W

impedance

high

BUSRQ line

The

low

logic

the

of

system

is

level,

resets

to

zero,

and floats

level,

causes

bus

an

disables

state.

is

an input

by

associated control lines

BUSAK

The

acknowledges

meO11>OJM—l

CO

20

10

11

12

13

14

15

16

17

18

19

outputispulled

BUSRQ

a

(cont)

input

the

program

all

tri-state

the

floating

to

input.

which,

interrupt

which,

280

to

the

a high

low

See

when

placed

counter

requests

bus

signals

when

placed

relinquish

address,

impedance

when

BUSRQ.

and

other

by

to

control

data

state.

the 280

ZBOQT

at

a

the the

at

a

and

Figure

3-1.

280

Assignments

Z8OQT

3-3. STATUS/CONTROL 3-4.

Introduction

9000

The processors

control

the mainframe of this microprocessor following:

0

0 Bit

0

0 Pin

These for convenience

3-5. Whenaread

binary low

specific

bit

a while bit

Series having

lines.

The

interface

Bit

number

User-writable

number

Address

assignments

Bit

Assignment

status

where

form,

line.Todetermine

status

number.

number

and 9100

to

up

provides

pod

and the

specific requirements

task,

lines

and

assignment

control

assignment

space

described

are

the

pod

on

-

operation

1

indicates

a

refertoTable

lines,

Bit

number

7

(POWER FAIL)

Status

LINES AND ADDRESS SPACE ASSIGNMENT

Series mainframes

32

address

the

lines

decal.

interface

an

makes

pod

mainframe.

of

Z80

of

control

in

the

lines,

status

lines

following paragraphs

accommodate bus-oriented

32

data

between the

ofthe

specific assignments

These

lines

16

lines,

general

Z80

microprocessor.

assignments

and

status

lines,

architecture

between the

include

summarized

are

Lines

is

performed.

logic high

a

which characters of the

3—2.

zero (WAIT)

This

table

appears

the mainframe

line

shows

the

at

the

and

that

far

far left

status

at

displays

a

display

each

right

side.

0

indicates

correspond

line

of

the

is

the

and

As

part

the

result

logic

a

assigned

display,

8

of

in

to

For

example,

low,

are

READ

to

zero

high. represented by

3-6. The

280

bus

acknowledge (BUSAK)

lines,

a

that

writing

approximately

3-4

inhem

and

all

other

=

0001

STS

@

indicate

Bits

User-WritableControl

control

has

5

and

two

to

a

zeros

function

a

20

number

(bit

lines

status

1011

OK. Bit

while

low,

logic

which

in

have

mainframe

the

lines

and

is

used

line

Lines

which the

to

halt

as only

6,

control

control microseconds,just

and

2)

high,

are

numbers

other

meaningful

meaning

no

display

(HALT).

described in

the

sets

enough

long

POWER

9000 Series

a

2

(W)

bits

Z80

as

message.

mainframe

To

write

the

paragraphs

line

to

FAIL(bit

mainframe

7

and

(POWER

ones

are status lines,

write.

can

either

to

the

high

that

verify

number

indicate

to

These

both

or

follow. Note

that

low

or

it

can

would

FAIL)

are

lines

of these

state

be

lines

7)

read

are

logic

always

are

for

driven.

ZBOQT

Bit

3-7. There to toggle

When

prompted

BUSAKorHALT. Table and

any the

If

with the

that

HALT mainframe line

in

When 9000

x

represents

A

inability numbers.

Assignment

two

troubleshooting

are

identify

any

English

binary

user—writable

control.

performingorprogramming

for

binary

a

1

respectively.Toperform

of the

following

lines,

status

00

01

10

11

control

message

line

cannot

line

displays

is

represented by

that

performing

Series mainframe

a

0

represents

drivealine. Table

to

four bit

bit

number

writes

both

writes

m

writes

BUSAK low

writes

both

line

cannotbedriven,

CTRL

be

driven.

be

can

control

a

binary

driven,

the

bit number

BUS TEST

a

number

Control

-

control

number

3—2

lines

ERR

message

line

message

the

ability

Lines

functions which

lines.

These

either

to

identify

shows

a

configurations

is

0

low

high

@

For

but

cannot

that

3-2

these

that

write

control

the far

at

and

m

H—ALT

and

the 9000

xxxxxxxx

example,

BUSAK

the

CTRL

ERR

0.

9100 series mainframe

(A

be

driven.)

various

and

CTL ERR

identifies which lines

drive

to

lists

all control

the

require

functions

of

the lines

operation

in

right

LOOP?,

if in

@

are

these

two

control

assigned

are

on

response

of the

display.

low

high

Series

mainframe

where

write

the

line

cannot,

00000001 LOOP?. The BUSAK

mainframe

other

xxxxxxxx-LOOP?

can

while

a

line,

lines

binary

a

and

entry

write

control and

functions,

1ine(s)

to

these

the

to

prompt.

x equals

control

the

displays

can

cannot

or

1

their

of

two

operations,

binary digits

the

user

be

written,

to

bit

numbers

lines,

As

responds

abinary

operation,

9000

a

message

occur,

be

driven.

represents

respective

data

enter

with

I

the

Series

the

where

the

bit

is

0

if

Address

3-8.

order

is

0

I/

memory

to

The 280 65,536

multiple

In

hexadecimal

locations,

0

l/

lFFFF.

For

decal

Space

capable

locations.

and

access one

address

the

user

convenience,

Assignment

of

addressing

mainframe

The

locations.

[/0

the

of

in

the

range

provides a

these

to

up

uses a

65,536

memory

of

0000

hexadecimal

assignments

65,536

memory

consistent

locations,

FFFF.Inorder

to

addressinthe

also

are

locations

techniqueofaddressing

the

to

summarized

and

provides

user

access one

of

range

on

up

of

10000

the

pod

to

a

to

ZSOQT

Table

STATUS

NO.

BIT

7 PWR FAIL

6

5

4

3

2

1

0

writeable

‘User

A

register contents eight pod

3-9. FORCING

Several associated with when lines low could disabled the unaffected.

special

bits

address

made

for

pod

address

in

the Z80

the I

of

the

of

for

mainframe

active,

the

280

cause

during

reports

3-2.

Status

LINES

SIGNAL

—

*‘

RESET

W

mm

”

BUSRQ

"WATT

"Forcing

exists

within the

microprocessor.

register(interrupt

address

forcing

bus

I

the

registeris20000,

AND

INTERRUPT LINES

messages

lines

force

the

are BUSRQ,

the

pod

such

to

condition

a

mainframe

duringaninterrupt

and

microprocessor

stop setup

Control LInes

and

Lines

pod

Thisisuseful

vector

used

are

interrupts.

WAIT,

and

timeout.

procedures.

to

NO. SIGNAL

BIT

7

6

5

4

3

2

1

o

address

register)

and

and RESET.

the

space

acknowledge

it

may

indicate

to

Forcing

into

Note If

the

mainframe,

Blt

Assignments

CONTROL

to set

for UUTs

only

it is

when

take

any

errors

lines

specific

some

Pulling

these

that

RESET

but

LINES

W

WT;

ﬁ—

Kin—o

ﬁt?

*H—AL_T

*BUSAK

the value

that

echoedonthe

The

cycle.

value

from

and

lines

those

are

action.

BUSRQ

lines

two

is

line

pulled

pod

operation

of

the

use

upper

special

0

FF.

to

conditions

which,

Forcing

WAIT

or

can

low,

I

be

is

Interrupt

disabled; RUN UUT

pod

lines

the NMI

software,

During mainframe

any

reporting

eliminates

the

for

input

mode. When

and

reported

they

eﬂect

(trapping)

the

280

is

disabled,

include

hardware

mainframe

the

to

TNT

the

and

disabled

NMI

N—M—l.

input

NOTE

setup,

might

forcing

disabling

have

BUSRQ

on

mainframe/pod

line

interrupts

or

correspondingmainframe

except

if held

and

message.

The

during

is

routinely

low

WA

during

input

W

operation

checked

the UUT.

by

Teliminates

I

operation.

setup

is

Not

simply

software

in

the

by

ZBOQT

ENABLED

LINES

3-10.

the

of

During

setup enabling disabling WAIT. Also

disregard mainframe

3-11.

The be mainframe

output

3-12. The

repetition

selected Quick-Looping traces (available

Unlike

Looping

using 9100 Series mainframes

certain

the

active

operation

NON-DETECTABLE

does

pod

observed,

to

signal.)

QUICK-LOOPING

Z80QT

rates considerably

by pressing

on an

on

ordinary

functions

the

Quick—Looping

mainframe,

forcing

microprocessor.

pod

mainframe

during

signals on

detect the absenceofthe

not

if

necessary,

trigger

Pod

provides

the

functions

oscilloscope

the

rear

mainframe

residesinthe

in

order

a

scope.

LOOP

panel

are

DURING

lines

the

are

read and

MAINFRAME SETUP

the

operator

as

a meansofpreventing

the

For

the

setup,

lines.

forcing

to

display

SIGNALS

280

the

using

by

(Figure

READ

Quick-Looping

faster

key.

particularly

synchronized

of

the

looping

pod

presented

probe

4-4

AND

WRITE FUNCTIONS

than

ordinary

Because

mainframe).

functions,

and

not

write

separately

has the

these

280,

operator

Reporting

the

forcing

signal. However,

m

or

shows

read and

mainframe

their

of

useful

for

the

TRIGGER OUTPUT

to

software

in

the

functions

under

optionofenabling

UUT

lines include

elect

active

line

message.

trigger

mainframe

write

to

forcing

may

scope

the

looping

increased

enhanced

mainframe.

the

of

the

that

pod

viewing

controls

for

from

faults

BUSRQ

(trap) or

report

lines

halts

this

signal

of

output

trigger

scope

functions with

functions

repetition

of

signal

pulse

Quick-

rate,

Instructions

9000

the

headings.

and

not

and

can

the

for

It shouldbenoted Quick-Looping

performed

the

to Subsequent

If

both

the

such

commands

full

Quick—Looping

v1ew1ng.

mainframe

error

ordinary

READ

as

reporting.

error

during

UUT

reporting

mainframe

read

that

diagnostics

read

or

execution

UUT

any

system

and

10

2000

@

operations

For

read

operations

write

operations

the

of

errors

system

errors are

Quick-Looping

LOOP

address

at

ordinary

function

in

(with

looping

every

performed

ordinary

detected

not

reported.

to

the

case

10

2000

read

no

error

the

by

less

are

looping

during

functions

the

Quick—Looping

the

9000

of

the normal

at

operation,

reporting)

pod

rigorous

function.

the

desired,

are

Series. The

the

to

execution

during

than

The

first iteration

you may

read

looping

interjects

pod

enhance

diagnostics

pod

reports

only.

apply

write,

or

mainframe

with

speed

few

a

oscilloscope

of

ZBOQT

CAUTION

To

prevent

the

use

Looping

frequency

The

preceding

repetition rate

MHz)

greatly

long,

probe

the

that

Read

3-13.

response

Probe

Using

Special valid

for

because the

functions.

pod

controlled

heading.

The

operator

3-3.

For

the

3-14.

To

follows:

example,

Quick-Looping

Using

start

Quick-Looping

possible

probe

function

is

less than

caution

of

a

Quick-Looping

increases

stimulus

capability

operation,

the 9000

addresses

9100

quick

selects

these

read

a

read

9100

the

damage

to

generate

is

being performed

is

necessary

the

on

pulses

can cause damage

of

is

unaffected

Series

mentioned

Series

mainframes.

Series

The

recommended

tests

from

functions

operation

Series

read

to

stimulus

1

MHz.

because

function

time

of

the

probe,

by

for

Quick-Looping

NOTE

the

in

provides

the

9100 Series

using

by

address

at

address

at

Quick

tor

the 9100

using

the

probe

it

the

and

pulser.

to

such

high

duty

following

However, softkeys

method

the

10

00

Looping

or

pulses

UUT

the

combination

slow

a

theontime

If

the

as logic

cycles.

Read and

paragraphs

they

to

directly

is

given

special

OFOO

causes

OFOO.

Read and

Series

the

UUT,

while

crystal

UUT clock

probe or

level

not

are

access

running

of

under

addresses

the

mainframe,

do

Quick-

a

clock

or

of

is

excessively

the UUT.

reading

Write

also

are

necessary

these

pod-

a

separate

listed

to

pod

Write

proceed

not

the

(below

with

in

Table

perform

high

1

Note

the

as

WRITE

READ

3-8

1.

Press the

2.

Press

Table

OPERATION

1X XXXX=YY X XXXX

@

1X XXXX X XXXX

@

POD

the

QWK_RD

3-3.

Quick-Looping

key.

softkey,

Read

followed

Write

and

PARAMETERS

=

Write

=

Write

W

=

Read Address

ENTER.

by

Test

Address

Data

Addresses

Z8OQT

3.

Enter

4.

The

and the

read),

To

follows:

3-15.

Quick Memory software

the Quick

Series

3-16. The quickly

faster

is

Quick-Looping

start

1.

Press

2.

Press

3.

Enter

4.

Enter

5.

The

QUICK

inside

corresponding

RAM and

mainframes

Quick

RAM

Quick

than

the

than

particularly

address

the

mainframe

the POD

the

QWK_WR

the address

the

data

podisnow

MEMORY

tests

mainframe.

the

tests

Quick

are

RAM

Test

with

the

RAM

well

suited

is

pod

write

key.

byte

controlled

are

built

ROM

presented

Description

allows

RAM

Short

for

want to

you

displays

in

in control of

TESTS

test

the

control

using

softkey,

desired,

followed

in

value

Quick

into

the mainframe.

functions

separately

the

operator

Short

test.

is

and

programming

followed

read,

contents

the

of

looping

the

9100 Series

followed

by

followed

hex,

the

looping

software inside

by

Memory

the

of

after

test

to

The

Quick

almost

as

applications.

by

the address

of

process.

mainframe,

ENTER.

by

the

right-arrow

ENTER.

by

process.

the

tests execute

Instructions

using

pod

description

a

RAM

address blocks

RAM

rigorous.

The

ENTER.

the first

(from

proceed

key.

rather than

pod, much faster

for

using

the 9000 and 9100

the

of

tests.

more

considerably

RAM

Test

is

Quick

as

than

the

test

The

pattern

'

O

Quick

verification

The

read/

read each low. been reads each

is

expected.

RAM

normal

write

/

bit of

After the

written

address

is

Test

test.

RAM

check, check

each

test

read/write

each address.

to

available

while

is

in

variations:

two

consists

test

the second

performed by writing

address

to

check

of

ensure

is

For

and

compares

the

two

phases:

checks address

phase

and

there

that

completed, a

the

address

read

data

normal RAM

the

first

are

no

a

bits

reading

unique

decoding

with the

unique

test

phaseisa

decoding.

l

and

a

held

bit

pattern

check,

word

0

high

the

and

The

from

has

pod

that

a

or

3-9

Z8OQT

O

The expected

test to period test

that RAM

RAM

Quick

3-17.

The

Quick

quickly

than

performed, obtained

known

good

Table

5-5.

in

obtained

The

Quick

the

by

ordinary

extensive. checksum confidence.

3-18.

Using

Special

valid

because the

pod

controlled

heading.

Starting

manner

specified

WRITE

Quick are address,

or

Quick

greater

3-10

and

than

@

RAM

defined

Z

specifiedas0,

RAM

than

pattern

data.

that

verify

is

than

is

provided

the

memory

are suspected,

test.

ROM

test

with

the

pod

by

performing

UUT. The value

Note

that

with

the

ordinary

ROM

test

ROM

However,

be used

can

9000

the

addresses

9100 Series

for

9100 Series

functions.

quick

ending

the

for

by writing

2X

XXXX=0,

The

test.

WRITE

by

a

is

desired

the

test)

or2(pattern

equal

or

verification

The

the

checked

primarily

test

shouldbeused

test

memory

the

by

for

retains information

the

use

Test

Description

the

allows

the

ordinary

obtains

the

this

checksum

a

Quick

this

of

checksum

operator

mainframe

is

not

rigorous

as

test,

noriserror

the

Quick

detect

to

Series

ROM

a

for

mentioned

mainframes.

provides

The

recommended method

tests

addresses

usual

to

special

ending

@

increment,

address

the

from

for

the

RAM

addresses. The

where X

address,

2Y

YYYY=ZN,

increment

verification

the

to

starting

simply

still

contains

normal RAM

testing dynamic

properly.

verification

pattern

to

ROM

test.

that

is

not

ROM

and

may

test

ROM

the

reliableasthe

ROM

Quick

reporting

test

can

ROM

faulty

RAM

Quick

NOTE

the

in

following

However, softkeys

Series

9100

RAM

Quick

The

test.

XXXXisthe

and

address.

starting

address

where Nisthe defaultstol. N

test).

verifies

following

test

When

over

same test.

detect

that

normal

a

the

correct

The

test.

ROM address blocks

be

the

test

valueasthe

device with

pattern

RAM

If

problems

test

following

the

Quick

compared

same

checksumisalso

signature analysis

in

the

Quick

inactive

Testing

paragraphs

they

to directly

is

given

test

starting

address

increment,

Y

test

specification.

The

not

are

running

of

under

specified

are

and

ending

address

be used

to

and

YYYYisthe desired

be

may

ending

memory

after

data

memory

with

ROM

with

address

signature

ROM

data

high

a

are

necessary

access

a

separate

addresses

is

test

Hz

either

address

contains

RAM

Quick

a longer

verification

to

assure

dynamic

the normal

more

test

checksum

a

block of

available

that

used

test

the

and

bits,

degree

also

these

pod-

inadifferent

to

is

1

are

by a

the

start

ending

omitted

(normal must

be

defined

specification

is

a

is

as

of

ZSOQT

For

example,

through

operations:

WHITE WRITE

To

follow

rewrite

the

WRITE

The

Quick

of

entry

mainframe

unless

test

selecting

by

To

determine

mainframe

the

are,

commands

(which the

status

pod

returns

codes

Read-only

tion

about

The

special

that

sure completed completed

to

pertain aborted.

5FFF

@

that

ending

@

RAM

the

does

requested

another

if

and

special

the

addresses

first

you

before

(or

to

specify

with

20 5000=0

@

20 5FFF=1

test

20 5FFF=2

ending

not

the

a

their

Quick

reading

failed),

normal

a

the default address increment

with

a

pattern

address

test

begins

address.

display

the

by

operation.

Quick

operator READ

a

indicating

byte

meanings are

addresses

RAM

for the

the

specify

at

the

rather

test

Quick

verification

with

the

new

execution

During

information

any

operator.

RAM

test

should

operation

the

in

F0 20XX

the

including

test,

Quick

RAM

READ

of

the

any

information

than

RAM

test

specification:

as

soon

and after

about

The

test

may

is

in

still

progress

perform

at

status

shown

@

special

the

a

the

last entered of

in

Table

range errors test

are

ENTERtofind

addresses.

containedatthe

current

over

1,

of

the

over

the

operator

execution

the

progress

be

aborted

or

RAM

do the

same

of

or

before

what

test

as

addresses

READ@ENTER

test

3-4.

address).

the

or

test

the

contain additional

and

recordsofaddresses

described

test,

out

Unless the

special

and the

in Table

if

the

current

following

address

space,

completes

the

test,

resultsofthe

completion

results

the

test

operation

In

response,

results.

informa-

3-4.

has been

test

has been

test

addresses

will

test

5000

two

the the

The

used.

Make

will

be

For

example,

of

byte You

can

If

the

status

read

correctly

contains

mask

the

if

the address

any

hex

a

get

code

after

bit

positions

contains the

error

where

mask of

is

F0,

being

with

bits

is

reported

the

error

bad

any

bad

the

data

written.Ifthe

incorrect

which

in

the

by

occurred

bits

data

bits

address

data

test,

you

by performing

performing

by

contains

mask

codeisF

status

decoding.

retained

not

was

can

find

If

a a

the

l,

the

READ READ

the

correctly,

least-significant

F0

@

F0

@

bits

that

were

mask

probably

code

status

2008.

2012.

not

is

F2,

3-11

Z8OQT

OPERATION

WRITE WRITE@2Y

READ

F0 F0 F0

F0 F0

2X

@

ENTER

@

READ-ONLY

2000

2001

2002

2004 2005 2006

2008 2009

200A

200C

200E

2010 2012

2014

20FO

Table

XXXX=0 YYYY=ZN

3-4.

Quick

ADDRESS

RAM

Addresses

Test

X

XXXX

Y YYYY =

Returns

=

No

00

A0 =

Aborted,

A1

=

Aborted,

A2 =

Aborted,

=

80

Busy,

81 2

Busy,

=

B2

Busy,

CO =

Complete,

=

F0

Failed,

F1 =

Failed,

=

F2

Failed,

Start

address,

Start

address,

Start

address,

End

address,

End

address,

End

address,

Error

address,

Error

address,

Error

address,

Expected

Actual

Most

recent

Hex

mask

Returns

Most

recent

and

PARAMETERS

=

Start Address

End

Address

=

2

Increment

N

=

Test

Speciﬁcation:

1

=

Perform

=

2

Pattern

Code:

Status

test

requested

new

illegal illegal

write

read/ address

pattern

no errors

read/write address pattern

LSB

2nd

MSB

LSB 2nd MSB

LSB

2nd

MSB

data

code

data

bad

-

increment

code

Codes

Status

RAM

Test Check

Verify

command

data

entered

in

command

addressincommand

check

decoding

verify

check

error

decoding

verity

FUNCTION

byte

bits

and

error

function

error

type

3-12

Z8OQT

3-19.

Special valid because

pod

controlled

heading.

The

Quick

The

starting

The

starting

addresstobe

the

address

desired

the

is

specified

or

greater

For

example,

do

0FFF,

WH/TE WRITE

Using

for

functions.

ROM

and

address

increment

ending

as

the

than

to

the

following

@ @

9000

the

addresses

9100

Series

the 9100

quick

test

ending

is

used

are

address

the

0,

starting

specify

30

0000=0

30 0FFF=1

for

Series

mentioned

mainframes.

Series

provides

The

recommended

testsfrom

is

specifiedina addresses

defined

by

the

start

to

defined

by

Zisthe

and

increment

address.

ROM

Quick

a two operations:

ROM

Quick

Testing

NOTE

in the

followingparagraphs

However,

softkeystodirectly

the

9100

Series

manner

are specifiedbywritingtospecial

WRITE

a

ROM

Quick

WRITE

a

optional

will

default

test

they

are

method

similartothe

3X

@

3Y

@

to

over

of

is

under

given

XXXX=0,

The

test.

YYYY=Z1,

increment.IfZ

The

l.

ending

ROM addresses 0000

not

access

running

a

Quick

where

ending

where

address

also

are

necessary

these

pod—

separate

RAM

addresses.

XXXXX

address and

Y

YYYY

is

specified

not

must

through

test.

is

be

The

Quick

of the

entry

mainframe

unless

test

selecting

by

To

determine

the

are,

commands

(which the

pod

codes and

status

Read-only

tion about

The

special

ROM

ending

will

not

requested

another

if

the

mainframe

returns

special

the

Quick

addresses

test

display

by

operation.

Quick

operator

READ

a

byte

a

their

addressesintheF030XX

ROM

execution

begins

address.

the

During

information

any

operator.

ROM

should

test

operation

indicating

meanings are

including

test,

for the

Quick

The

is

perform

the

showninTable

ROM

as

soon

and after execution

test

still in

the

at

status

errors

test

the

as

the

about

may

last entered of

range

progress

be

aborted

progress,

READ

a

the

test

3-5.

contain additional

and records

described in

are

operator

before

what the

or

@

ENTER

address).

the

or

of

completes

of the

test,

of

results

or

completion

results

test

operation

In

response,

results.

test

informa-

addresses used.

3-5.

Table

3—13

the the the

The

ZBOQT

3-5.

Table

OPERATION

Quick

ROM

Test

Addresses

Codes

Status

and

PARAMETERS

WRITE WRITE

READ@ENTER

F0 F0 F0

3X

@

3Y YYYY=21

@

READ-ONLY

3000

3001

3002

3004 3005 3006

3000

300D 300E

3010 3014 30F0

X

XXXX=0

XXXX = YYYY

Y

Returns

=

No

00

=

A0

A1

2

A2 =

Start

=

End

=

2

Increment

Status

test

Aborted, Aborted, Aborted,

Address

Code:

requested

command

new

illegal illegal

m=mw

CO

=

Complete,noerrors

C1

2

Complete,

ADDRESS FUNCTION

Start

address,

Start

address,

Start

address,

End

address,

End

address,

End

address,

Checksum, Checksum,

Hex

mask—inactive

Most

recent

Returns

Most

recent

inactive bits

LSB 2nd MSB

LSB

2nd

MSB

LSB MSB

code

increment

code

byte

in

data address

bits

entered

command

in

command

detected

more

information

the

at

For

operations

READ@ENTER

of

the

any

information rather than

special

contained

the

current

special

find

to

addresses.

at test,

about

addresses

out

Unless

the

and

the

listed

if

the

special

the

test

the

addresses

current

results,

in

Table

has been

has

test

the

operator

3-5.

completed

been

will

You

should

completed

pertain

be

aborted.

may

first

before

(or

to

a

specify

perform

reading

failed),

a

at

the

test

ZBOQT

3-20.

Proceed

3-21.

Proceed

the

Using

follows

as

1.

Press

the

display

2.

Press

3.

Enter the

4.

Enter the

5.

(Optional)

the

right-

6.

(Optional)

right—arrow

7.

Press

8.

When the

returned,

the

Using

follows

as

1.

Press

9100

Series

start

to

the RAM

QUICK

the

QUICK

beginning

ending

To

selectanaddress

arrow key,

To

select

then

key;

ENTER

to

BUSY

the UUT has

9100

Series

to

start

the ROM

for

Quick

RAM

Quick

a

followed

key,

softkey.

softkey,

followed

address,

address.

followedbythe

insteadofthe

verify

2.

select

the

start

test.

indicator

passed,

for

Quick

ROM

Quick

a

key.

RAM

test

using

the

by

followed

step

off

goes

ROM

test

using

Testing

the

9100 Series

right-arrow

ENTER.

by

the

by

other

than

15).

to

(up

default of

and

no

Testing

the 9100

mainframe:

if

key

necessary

right-arrow

default

the

test,

error

messages

Series mainframe:

key.

of

press

1

to

press

the

are

2.

Press

3.

Press the

ENTER.

4.

Enter

5.

Enter

6.

(Optional)

the

right-arrow key,

7.

Press

8. A

checksum

the TEST

right—arrow

the

beginning

the

ending

To

ENTER

is

softkey.

then the

key,

address,

address.

selectanaddress

followedbythe

the

to start

returned

test.

when

followed

step

the

test

QUICK

by

other

(up

is

softkey,

the

right-arrow

the

than

15).

to

complete.

default

followed

key.

1,

of

by

press

Z8OQT

QUICK

3-22.

Fill

Quick the

accuracy

information

and

Verify

of

into

FILL

the

special

AND

fills

blocks of

contents.

addresses

VERIFY

Quick

memory

Fill

as

with

and

Verify

described below.

user-selected

is

controlled

data,

by

then

writing

verifies

setup

Quick

In

tests. might

Three specified

3

at

or

0

Quick address

0

Quick block address.

9000

0

Quick Verify

3-23.

Special valid

because

pod

controlled

heading.

Fill

and

Verify

addition,

be desirable

variations

when

writing

the

keyboard

Fill

to

Verify and

Errors

Series)

Fill

into

the

Using

addresses

9100 Series

for

the

functions.

are

allow the

testing

the

ending

are

reported

the

to

Verify

step.

Series

much

user

a

Fill

and

address

the

9100

writes the

1)

2)

by

each

display

(specified by

for

tests

they

when

of

Quick

(using

(specified by

allofthe addresses

(specified

compares

or

and

one

9000

mentioned

mainframes.

9100 Series

quick

The

recommended

tests

from

provides

the

faster

to

memory-mapped

Verify

Series).

the

than

customize

are

(using

the

data that

in

the block.

reads

one

via the

(9100

Quick

to

special

data

the

Series).

combines

3)

Fill

and

from

data

NOTE

the

in

followingparagraphs

However,

softkeys

method

9100 Series

mainframe’s special

memory

video

display.

available. The

9000

Series)

is

contained in

all of the

containedinthe

Verify

are

directly

of

described

Quick

not

running

under

addresses

they

to

is

given

normal

variations

or

addresses

Fill

are

necessary

access

a

separate

memory

such

tests,

entering

the

starting

below

and

'

also

these

pod-

are

l,

in the

(for

Quick

as

2,

Fill

Quick

The

test.

starting

to

XXXX=0,

address,

YYYY=ZN,

increment,

3-16

address,

special

address

and

data

addresses. The

whereXXXXXisthe

whereYYYYY

and

Verify

be

to

then

increment,

Nisthe

tests

written

the

starting

test

are

starting

and

specification.

and

address

test

specification

desired

the

in

ending

to

specified

all addressesinthe

to

is

If

a manner

addresses

is

defined

be

used

are

ending

is

Z

not

similartothe

is

are

by a

defined address,

first written

specified

the

by

or

block

to start

specified

WRITE

test.

WRITE

a

is

Z

is

specified

Quick

by

The

the

RAM

the

to

writing

4X

@

ending

4Y

@

optional

0,

as

Z8OQT

increment

the

and

(fill address.

For

an

Quick of

not

requested selecting

Special Quick used, Verify

To

the

READ

indicating meanings are

verify

example,

increment

WRITE

Fill

the

ending

display

another

addresses

Fill

errors,

are

determine

operator

operation

or

by

and

described

the

defaults

block).

to

specify a

ofland

00

@

40

@

40

@

Verify

address.

information

any

the

Verify.

and

if

Quick

should

status

shown

to

The

data

0000=AA

0000=0

0FFF=

begins

During

operator.

operation.

in

the

range

These

other

information.

in

Table

Fill

perform

last entered

the

at

of

the

in

Table

1.

N

be

may

address

ending

Fill

Quick

11

execution

for

do the

AA,

(Write

(Specify

(Specify ending address, increment,

as

after

and

about

The

test

of

F0 40XX

read-only

3-6.

is

Verify

or

READ

a

address). the

test

or

3-6.

I

either

data

the

locations contain

The

still in

@

must

RAM

following

AA

starting

as

soon execution

progress

be

may

contain

special

progress

ENTER

In

results.

test

(fill

be

memory

three

to

address)

the

of

aborted

additional

addresses

operation (which

response,

block),2(verify block),

starting

operator

the

or

The

than

greater

0000

through

operations:

address)

completes

the

test,

resultsofthe

before

information

records

for

what the

or

the

pod

status

or

the

starting

with

OFFF

and

test)

the

entry

test

Fill and

results

will

unless

about

are,

byte

a

their

mainframe

completion

of the addresses

Quick

test

commands

returns

codes and

3

by

a

For

more

operations ENTER

addresses.

special

contained current

3-24.

Using

Proceed

Series

9100

a

1.

2.

information about

the

at

special

to

test,

as

find

at

follows

Press

if

out

Unless the

the

special

the

and

9100

the

to

mainframe.

POD

the

QWK_FILL

current

run

addresses

the

test

addresses

Series

Quick

key.

the

has

test

listed

been

has been

will

for

Quick

Fill,

Quick

softkey,

results,

pertain

be

the

operator

in

completed

aborted.

3-6.

Table

before

completed (or failed),

to

Fill

and

Verity

Verify,

or

followed

by

You

Quick

ENTER.

may

should

reading

test

Fill

specify

first

at

information

the

rather

and

Verify

READ

of the

any

than

read

@

the

using

3-17

2800T

Table

OPERATION

X

WRITE

WRITE WRITE

READ@ENTER

READ-ONLY

F0

4000

F0

4001

F0

4002

F0

4004

F0

4005

F0

4006

F0

4008

F0

4009

F0 400A

F0

400C

F0 400E

F0

4010

F0

4012

F0

4014

F0

40F0

XXXX=DD

@

4X XXXX=0

@

4Y

@

3-6.

Quick

YYYY=ZN

ADDRESS

Fill

and

Verity

X

XXXX

DD=Fill

X

XXXX

Y YYYY =

Returns

=

No

00

=

A0

Aborted,

A1 =

Aborted,

=

A2

Aborted,

BO

=

Busy, filling

B1

=

Busy, verifying

CO

=

Complete,

=

F0

Failed,

Start

address,

Start

address,

Start

address,

End

address,

End

address,

End

address,

Error

address,

Error

address,

Error

address,

Expected

Actual

Most

recent

Hex

max —

Returns increment and

Most

recent code

Addresses

=

Start

Data

=

Start

End

=

2

Increment

N

=

Test

1

= =

2

=

3

Status

test

requested

verify

LSB

2nd

MSB

data

code

bad data

and Status Codes

PARAMETERS

Address

Specification:

Fill

Memory

Verify

Fill

and

Code:

new

illegal illegal

LSB

2nd

MSB

LSB

2nd

MSB

Verify

command entered

in

data addressincommand

no

errors

FUNCTION

byte

bits

function

command

type

3-18

ZBOQT

3.

Enter

4.

Enter

5.

Enter

(Optional)

6

the

right-

7.

(Optional)

the

right—arrow

8.

Press

3-25. 3-26. The characteristics

pod marginal

actual

easier reveal

3-27.

the

MARGINAL

Introduction

is

pod

differ

does

UUT

microprocessor

in.

The

UUTs access

differences

pod

troubleshoot.

to

marginal problems

UUT

designed

operate

may

reportingoferrors

the

beginning

the

ending

the

data

To

arrow

To

ENTER

UUT

designed

the

of

microprocessor

in

some

problems

Operating

to

operate

marginally.

address,

in

hex,

byte

select

key,

select

key;

to

respects.

more installed, tend

Different UUT

Speed

address

an

followedbythe

function

a

then

enter

the

start

PROBLEMS

approximate,

Visible.

but tend

make

to

described

are

and

at

speeds

Inherent

in

memory.

followedbythe

followed

2

test.

that

In

general,

A UUT

marginal

and

Memory

that

other

step

other

for

verify

as

closely

it

replaces

these

may

exhibit

to

UUT

pod operating

in

the

paragraphs

Access

approach

delays

by

than

present

right—arrow key.

right—arrow

the

right-arrow

than

the

to

15)

(up

the default

3

for

or

as

in

the

differences

operate errors problems more

the

time in

key.

default

of

fill

then

possible,

UUT.

However,

tend

marginally

the

with

conditions

follow.

that

limits

the

pod

key.

of

fill

(1),

verify.

the

to

with plugged

pod

obvious

that

for

memory

may

1

,press

press

actual

make

result

the

and

may

in

3-28. UUTs enough,

case

or noise

noise

of

use

3-29.

The

pod

also

presents

make

UUT

operate

it

does

disturb

may

exist.

could problems

the

pod

Bus

loads

bus

any

Noise

with

affect normal

not

The

will

and

Loading

UUT

the

more

drive

Levels

certain

a

actually

mainframe.

capacitance

the

integrity

pod

may

slightly

problems

amount

be made

of

operation.

of

the

introduce

worse

more

the

than

obvious.

more

and

noise,

shielding

as

Removing

to

additional

easier

(and

the UUT

than

microprocessor.

noise

the

as

long

the

UUT

the

noise.

where

point

In

general,

to

troubleshoot)

microprocessor.

These

level

its

chassis

from

intolerable

marginal

through

The

effects tend

is

low

pod

to

3-19

Z8OQT

3-30. CIock

The rarely more

3-31.

As

normal

clock)

3-32.

A

mainframe

above

specifications

pod

obvious.

driving

a

power

increases

have

POD

280

TTL

are

POWER

sensing

whenever

certain

Loading

clock

the UUT

capability.

+5V

The

power

[-1.

load

on

operation,

bus,

the

pod

supply

power

failure detection

the normal

affect

any

DRIVE CAPABILITY

source

current

table,

on

drive

compatible.

FAILURE DETECTION LIMITS

circuit within

the

limits.

Table

the UUT

it

the

pod

All

pod

produces

in

clock.

may

provides

inputs

UUT

the

make

a

While

marginal

equal

and

power

drops limits

this

to

outputs

fail below

are

loading

clock

better

or

(except

output

or

listed

will

sources

than

the

to

increases

in the

3-20

ZBOQT

INTRODUCTION

4-1.

contains

section

This generalized;

the

pod

description

4-2.

The

pod

0 Processor

0 UUT

0

4-3. The

Processor

RAM,

small

a

operations

pod

disrupting

UUT

it describes

the 9000

to

covers pod

GENERAL

may

Interface Section

Timing

Processor

ROM,

a

computer

inputs

from

faults

Series

POD

divided into

be

Section

Section,

and

an

system

during

hardware

are

disabling

block

two

the

operating

9100 Series

or

operation

OPERATION

the

in

shown

interface

I

/

0

which receives

execution.

disabled,

the

pod microprocessor.

Theory

diagram

concept

in

more

following

Figure

the

to

All

reset,

or

of

descriptions

of the

pod

mainframe and

detail.

three

major

is

madeupof

4-1,

mainframe.

mainframe

non—maskable

may

commands and

software

be

Section

Operation

of

the

pod.

and the

relationship

the UUT.

areas:

a microprocessor,

These

elements

interrupts,

disabled,

The

second

The

comprise

directs

and

to

prevent

first

other

4

is

of

all

The

Processor

the

with of time, UUT

UUT,

time

its

the

Interface Section

continuous

to

refresh

order

Section

but

monitoring

and address

data

read

with

not

the

operations

dynamic

any

the

has

both

mainframe

buses

(although

at

RAM).

capability

concurrently.

I

/

0

of

the

Processor

the

pod

the

reset

of

operating

The

interface

sends

address

with

the

microprocessor

for

commands.

Section

signals

appear

are

to

isolated

the

be

mainframe,

spends

During

from

UUT

so

taking

place

or

most

this

the

that

in

ZBOQT

MAIN

FRAME

HANDSH/IKE

LINES

A

I

|

I

'

L

r_

I

|

I

|

I

A

l

|_______________________I

”0

_

RAM

INTERVAL

TIMER

TIMING

CIRCUITS

I

——>DISABLE

:

INTERFACE

PROCESSOR

SECTION

MICRO-

PROCESSOR——

___________

__________

RAM,

ENABLE

RESET

TIMING

-

SECTION

mm,

m

BUFFERS

POWER FAILURE

POD

I

|

|I

I

|

I

'

I

Z8OQT

UUT

|

I

|

I

|

1

DATA/

ADDRESS

BUFFERS

STATUS

CONTROL

ENABLE. BUFFERS

:

SIGNALS

'

PROTECTION

_

UUT

INTERFACE

SECTION

UUT

CIRCUITS

AND

LOGIC

LEVEL

SENSING

CLOCK

POWER

SENSING

CIRCUIT

STATUS

A

CONTROLA

I

|

J

6——

UUT

V

POWER

UUT

MICRO-

PROCESSOR

SOCKET

Figure

4-1.

General

Block

Diagram

ZBOQT

UUT

4-4. The UUT elements:

Interface

Section

Section,

shown

in

Figure

4—1,

include

the

following

0

The

UUT,

buffers

Each

of

a

voltage

Each

latch connected

a senses

each UUT individually

then

4-5. The work pre—determined by work

mainframe

The

Timing

and

Data

Protection

level

Logic

and

data

line

lOO-ohm

line

address

disabledtoisolate

or

is

maintained

the

to

series-resistor and

conditions from

the

UUT

to

the levelatthe UUT

operation,

addressed and

compared

Timing

primary

with

Section

function

either

one

commands,

Section of

an

arrangement

microprocessor,

the

addressing

Interface

Processor

Section

microprocessor

their

of

Vice

or

reset the

mainframe

set

on

to

versa,

state,

Processor

the

microprocessor

the interval

prepare

UUT,

In

part

When the

operation,

value

Section UUT.

address buffers

circuits

for

detection

UUT

to

the

sectionorthe

circuits

buffers

the

by

contains

damaging

contains

the

UUT

side of

stores

the desired results

of

the

Processor

microprocessor

permits

the

pod,

of

determines

(and

to

timing

Section

UUT).

address the

result

would

the

timing

Section,

issues

a pod

timer

command

for

lines

signal

for

enabled

are

the

microprocessor

section.

timing

a

protection

clipping

pod

detection

a

side of

the

protection

the levelofthe UUT

readbythe Processor

section

timing

Section

other

the

use

shown

circuits.

timeatwhich

the

(RAM,

This

timing

Processor

in

improper

circuits

which includes

command

the

sets

corresponds

execution

address,

data,

to connect

circuit. A

diodes.

components.

circuit.Adetection

lOO-ohm

as

a means

is

to

the UUT

or

itself.

Causing

required

as

of

only

one

in

cause

4—1,

Figure

The

the

and

ROM

is

critical,

Section

operation.

the

microprocessor

an

which calls

interval timer

the

to

prior

status

the

from the

microprocessor

UUT.

protection

circuit

This

protection

andatthe

circuit,

line.

Section.

of

detecting

the

cause

Interface

the

during

microprocessor

consists

interval

microprocessor

time

timer,

I

to

/ O)

addressing

since

with

addresses

I

port

/0

for

a

to

a

needed

to

actually addressing

control

and

Control

-

circuit consists

prevents

consists

circuit

resistor. The

conclusion

Each latch

Their

contents

UUT bus

microprocessor

Section

microprocessor

the

of

any

to

UUT read

specific

by

at

execution

in

the

interval

an

preset

switches

the UUT

attempt

meant

to

operate

mainframe.

the

or

value.

the Processor

lines

to of

over

latch

is

then

faults.

time

a

pod.

timer

by

from

by

for

as

write

The

the the

of

are

to

of

the

the the

a

the

4-4

ZBOQT

interval timer

the

When

disable

the

a

UUT

instead

address

fixed

and the

the

RAM, ROM,

action

This

is

write).

a

period

microprocessor

of

the

logic

transaction.

bus

RUN

to Section. Section

having completed on

executed

After UUT,

elements within

the

When

microprocessor

the Section. in from the Section.

4-6.

Figure UUT

event

Interface

UUT

In

RUN

the

mainframetothe

UUT

4—1

power UUT

addition,

UUT

Power

also

supply.

power

causes

the

Processor

of

preparation

and

bus,

of

time,

Processor

detection

level

UUT

to

change

Section,

the

mode.

Sensing

shows

a

This

drops

reaches

timeout,

I

and

mode

RESET,

power

below

and

O,

/

the

microprocessor

Section.

for

command

UUT dataonthe

the

timing

returns to

Section, The

circuits

is

commanded,

from

controlling

does

but

NMI,

pod,

which

sensing

produces

rises

or

UUT

The RUN

circuit

the

timing

enable

to

At the

data

circuits

controlling

timing

to

store

the

not

return

WAIT,

mode

returns

circuit which

an

above

circuits

the buffers of

control

to

same

execution,

bus

terminate

circuits the

state

the

Timing

Processor Section

control

and

BUSRQ

is

terminated

control

time,

places

(if

the

RAM,

also

of

back

backtothe

the

operate

the

Section

constantly

the mainframeinthe

to

output

established

limits. See

produce

the

inputs

an

Interface

UUT

Interface

UUT

microprocessor,

UUT

address

a

command

addressing

and

ROM,

the latches

UUT

bus

causes

to

controlling

the

Processor

to

enabled

are reset

by a

Processor

monitors the

Table

output

being

the

of

I

/

during

the

signal

1-1.

0

DETAILED

4-7.

block

The identified

diagram

4-8. Refer following

0

diagram

in

of

the

Processor

Figure

to

components:

Microprocessor,

ROM,

0 RAM

0

I/O

ports

0 Address

Status

0

BLOCK

description

the

previous general

is

presented

pod

Section

4—2.

The

U2

(128X8),

A and

decoder,

line

buffers,

DIAGRAM

that

Processor Section of the

U5

U19

U21-U24

B,

U31

U7,

U7

DESCRIPTION

follows

description

in

Figure

4-2.

eachofthe three

covers

of

pod

operation.

is

pod

sections

pod

detailed

A

madeupof

block

the

ZBOQT

E

g

u.

z

<

2

§

O

a: u.

\

o

I—

0—7

POD

H

————

MAINSTAT

——.I

PODSTAT

«—

4

gm—C

:

POWER

A V

-5V,

+5V,

\

ATA

D

W

A

PORT

I/O

B

PORT

RAM,

I/o.

INTERVAL

TIMER

EMULATOR

U16-U29

I/O

B

PORT

__

IRQ

TIMER

*

TIMING

CIRCUITS

U9,

U11,

L112

SYNCTOLATCHES

FAIL

+12V

A

V

csz

t:

CHIP

SELECT

A0-A7

v~

0

cl,

D

DRIVE

(CONTROL)

STATUS

RUN

OUT

UUT ON

_

,

ROM

U2

gs

UUT

‘

a.

v-

<,<

3

SIGNALS

ENABLE

TO

I

CIRCUIT,

*7

POWER

‘

,

“

I,

MICRO-

PROCESSOR

U5

Ar

UUT

HOLD

Low

U12

IN

DATA

—

RD

ADDRESS

.

ON

BUS

ENABLE

BUS

(AO-A15)

DISABLE

STATUS

LINES

BUFFERS

J

VOLTAGE

SENSING

CIRCUIT

U10

I

(DO-D7)

:

J

ZSOQT

DATA

BUFFER

(B

ECTIONAL)

I

DIR

—._¢.

20535.5?

U3,

v g

E

ADDRESS DECODER

"

ADDRESS DECODER

u31

_

a

I-DIR-

U1

“EN

"EN

U5

U7

C—STO

—'>

EMULATOR

"—’

4

‘

D—AT’AWI

A'DDHIEN/ ADDLOEN‘

——

BLATCHEN

CONTEN‘

__

ROM

__

TO

032

POWER

SOURCE/

SINK

u10

BDO—BD7

A.

A

.

II

*SYNC

LE

4

LATCHES

U2

OE

UUT°—"

—

$

LE

‘

LATCHES

U4,

‘

OE

STATUS SIGNALS

‘SYNC

LE

‘

LATCHES

U8

""05

CONTROL SIGNALS

A

‘SYNC

LATCHES

U9

OE

BAO

SYNC

U6

N

_

BA15

+4.3v

—>

+0.7v

_,

+4.3v—b

+0.7v

LDO»LD7

4

HOLD

CIIRCCVJIT

”‘2

+0.7v_

LAO-LA7

4

‘

+4.3v

+0.7V

V

+4.3v

+0.7v

‘

T0

CIRCUITS

_,

{7

PROTECTION

A1,A4,

‘1

49,9

'5

.

A1

I

+43

NW

1

v92

-

;

j

.

A3

A2,

{ALE/9

A

-

‘

'}

i

A“

.

A4

*3/91?

A5

'

_

T

_

.

'

A

CLOCK

A5

DATf

ADDRESS

STATUS

A

‘

CONTROL

J

V

;

'5

2

’

O

E

\

E

'

Flgure

4-2.

Detailed

Block

Diagram

A

+5VJ

ZBOQT

The

Processormonitors for mainframe of

address

I

/

O,

or

The

mainframe

lines

on

emulator

received,

4-3

insure

to

Each

mainframe

routine

ing

mainframe

necessary example,

commands.

A0—A7

lines

A12-Al4

Interval

POD0-7. The

Timer.

places a

and

reading

the

handshaking

thatnodata

commands

contained command

internal

if

mainframe

the

microprocessormust

the

command.

addition,

any response

reflects

data

ready with

In

transmits

which

transmission

data

as

is

operate

no

to

the

routine

the

of

data

shown in lost

during

be

the

handshake

The

and

to

microprocessor

address

produce

lowonthe MAINSTAT

decoder,

the

MAINSTAT,

line,

signal

@

microprocessorresponds

each

lines

is

in

ROM U2. first

by

byte

operate

lost.

causes

setting

mainframe

the

of

as

the

microprocessor

This

the interval

shown

routine,

operationsinpreparation

command calls

perform

written,

current

and

the lower

the

and

the

directs

backtothe

data

condition

status

portionofFigure

transmission

steps

perform

actual

back

necessary

housekeeping operations

write

mainframe,

of

the

to

process.

I

at

/

B,

port

B

by

the

is

A

0

port

As

each

of

correspond—

a

performs

performing

the

UUT.

the

UUT,

address,

associated

of

the

status

During

insures

waiting

means

RAM,

placed

of the byte Figure

the

all

For

the

UUT,

byte

the

lines

that

0

selects

that

when

addressing

command.

the

upper

execute

to

executed,

and

addressing

Write

a

assemble

functions

read

and

produces a

and UUT.

The

handshake

I

/

0

port

either

command

a

I

/

portion

then

to

the UUT

the

handshake

addresses

U31. The address decoder decodes

line

by

in

when

timer

for

to

and

pod

mainframe,

4-3.

is

The

microprocessor

and

HALT,

as

microprocessor

WAIT,

as

a means

pod operation.

the

for

status

lines

emulator.

4-9. UUT Refer

components

0

4-8

Interface

to

Figure

shown

Bidirectional

Protection

has the

a

means

control

can

of

preventing

are

drive

written

Both the

Section-General

4-2. The

in

Figure

data

buffer,

circuits,

capability

of

verifying

the

enabling

signals

by

UUT

4-2:

A1-A5

of

software~driving

that

or

stuck UUT

the

for

the

microprocessor

Interface

U1

they

disabling

status

control

Section

control lines BUSAK

driven.

be

can

of lines lines and the

through

lines

status

from

interfering

enable

I

/

0

includes the

Also,

BUSRQ

signals

B

port

following

the

and

with

of the

0 Address

buffers,

U3

and

ZBOQT

U5

0

Sensing

Hold low

0

0000 when

0 Power

UUT

4-10.

The

Data

processor

meant enabled

is

for

by

Processor

BDO—7.

function

All

data

The

of

passing

protection

the

data

the

respective

resistor

data

lines

detection

overvoltage

lOO-ohm

clip

The line. The of provides

latches,

circuit,

the UUT

source/sink

Interface

Ul

Buffer

controlling

UUT

the

timing

Section,

direction

the

microprocessor

between

circuits;

in series

line

at

also

are

protection

U2,

U12

U10

Section

is

disabled

the

from

circuits when

such

as,

the

of

circuit

one

with

and+5volts.

zero

equipped

circuits

protection.

U6,

U4,

associated

and

is

accessed

not

for

Data

-

Processor

reaching

during

dag:

RD line.

the

pod

per

the

with

consist

circuits. A

U8

protection

U9

and

components,

circuits

to

Lines

timing

read/

a

pair

level

circuits

This

Conversely,

write

UUT

protection

of

detection

latches

the

by

Section.

the UUT.

the

microprocessor

UUT

a bufferiscontrolledbythe

and the

line.

Each

and

line,

logic

of

series of

a

series resistor

whenever

disabling

is

operation

is

fed

clipping

circuits;

coupled

the

at

hold address

the

prevents

the

not

data

buffer

data

controlling

via

data

DIRIN

series

diodes.

one

to

the

of

a

The

circuit

UUT

each

through

circuit consists

input

lines

micro-

not

the

lines

line,

of

diodes

per

side

latch

at

is

a

of

a

The

to

driven

logic the

At

lines

data

each

levels,

state

latch

low. The

at

of

each

is

the

the conclusion

microprocessor.

of

contents contents

between the

the latchesonthe

of

the addressed latch

contents

error.

coupled

are

logic high

LATCH

time

data

Address decoder

to

signal

shown

line.

ofaUUT write

of

the latch

the

if

the line

in

of

inputs

is

driven

from

the

Figure 4-4,

operation,

U7

produces

bus. The

data

with

the

and

the intended

latches U2

Timing

to

intended write

by

and

high,

Section

the

store

U2

latch

the

DATAEN

microprocessor

data

lines

logic

are

data.

LDO—7.

low if

latches

levels

addressed

signal to

Any

is

considered

The

line

the

data

representing

by

place

compares

difference

a

input

is

line

the the the

data

ZBOQT

>Q<mm

_

.

._.a:m0m_m

QmOij>>OZ¥O<

00m

0...

MESH—".225.

<P<O

20¢".

m_

<h<o

wmmI

0232200

mo

man—252.200

<._.<Q

Dm>_m_0m_m

‘

DZ<_>:>_OO

mthOImmamDOmh

0...

DO...—

Eomn.

<h<o

828%

<55

q

mo“.

<55

>o<mm

bum—0mm

QwOqu>>02¥0<

m.

<P<D

NEMI

4-10

F<sz_<_>_

Flgure

._.<._.wDOn.

4-3.

Handshaklng

F<FWZ_<—>_

Signals

.r<._.mQOn_

ZBOQT

READ

UUT

AO—A1

00-07

SYNC

LATCH

UUT ON

DO-D7

r

1“

0

x

5

pc

E

_.

.0

ADDRESSX

w

.4

REFRESH

ADDRESS

:‘F

TalTl

x

F_‘l

MEM

READ/WRITE—«rIt-M1

|T2|

7LT

MEMORY

AC

T3

DRESS

|

[._

T1

PC

AD

L

DATA

OUT

\‘ILVRITE

(I)

.<

2!

UUT

LATCH

‘UUT

5

MAINFRAM

SYNC

OUT

ON

O

£77!

LA1

E

K

Figure

4-4.

UUT ON

Signal

and Latch

Times

Z8OQT

UUT

4-11.

In

a

manner

through

diodes.

function

Section

Address the UUT isolate

controlling from

addition, protection

This

holding

associated downto-0.7 volts whenever the UUT addressof0000.

operation

described

As

detection

latches resistoratthe

The

address

LAO-LAIS. The logic

latches logic

Interface

similar

series

a

diodes

The

of

holding

is

not

buffers

Interface

the

microprocessor the

addressing

the

circuits.

components.

the UUT and

of

circuits;

coupled

lines

if

low

the

address

levels

representing

controlled

address

action

for

input

Section-Address

described for

that

to

of

protection

used

to

the address

by

U3 and

Processor

US

Section.

Section. This

the UUT when

lines

is

provided

This circuit

Maintaining

the

data

lines,

circuit

one

UUT

the

to

each latch

of

are coupled

each

to

input

lineisdriven

line

logic

the

circuits

protect

lines

the

microprocessor.

enabled when

are

Conversely,

the UUT whenever

from

operating

held

are

by

the UUT

associated

the

line.

per

side

of

provides

the

to

latch

low. The LATCH

at

levels,

of

state

Lines

the

data

equipped

the address

at

zero

the address

isolation

as

at

zero

the

hold

the

drives

is

not

address

at

systems

detection

The

respective

lines

overvoltage

address

the

inputs

is

high

logic

time

the

each

data

all UUT addresses

lines,

with resistors

lines

perform

volts

the

part

volts

low

being

equipment.

time the

any

microprocessor

buffers

the

prevents

the Processor

of

the diodes

by

circuit,

+4.3-Volt

diode

addressed,

0000

prevents

equipped

are

circuits consist

made

protection

protection.

latches U4 and U6

of

line

if

the

from the

signal

in

shown

line.

Figure

and

clipping

the additional

Interface

UUT

is

controlling

disabled

are

microprocessor

the

microprocessor

Section. In

used

of U12

up

clipping voltage

creating

inadvertent

any

with

logic

ofaseries

circuits. A series

Timing

to store

4-4,

by

high,

is

driven

fed

are

in the

and

UUT

a

level

lines

and

Section

the

to

is

of

At the

conclusion of

addressedbythe

and ADDHIEN

byte latches

latches and

4-12.

The

detection

provided

a

with

UUT

status

actual address

and

circuits

with

time.

at

paragraphs.

4-12

a

microprocessor.

signals

The

microprocessor

the

actual

Interface

Section

control

and

latches.

the

data

UUT

operation,

to

place

address.

is

considered

-

lines

are provided

These

and address

Address

the

decoder U7

contents

compares

difference between

Any

an

Status

and Control

circuits

lines,

latches U4 and

produces

the latchesonthe

of

the

contents

address

with

operate

error.

protection

in

described

and

Lines

a

manner

U6

are separately

the ADDLOEN

data

of

the addressed

the

contents

circuits,

similar

in

the

bus,

of

logic

to

the

level

those

ZBOQT

4-13.

The

timing

series

of

description

command internal

set to

a

perform

time

the

At

from the

output

times

timer produce

produce

the

disable

A

signal. releasing

the

With

and addresses

data

The

UUT. and

U31,

the

With

selected.

not

At the end

circuits

address

enable back

to

Section

Timing

section consists

circuits

timing

the Processor

of

first

by

operations

time

equal

all

necessary

interval

the

timer

the

out,

SYNC

the

UUT

high

a

address

corresponding

address

the

and address

data

Processor

receives

which

the

of

to

decoder,

the Processor

decoder

instruction

their

address

return

control

made

setting

in

preparation

the

to

internal

timer

holds the

lR_Q

signal.

ON

decoder.

low UUT ON

from

bus

placed

Section

the disabled,

reset

U7 and

the interval

of

up

Section,

interval

the

amount

operations.

is

set,

timing

output

time

At the

to

signal

Refer

the

buffers

the buses

on

is

disabledatthis

UUT

cycle (except

state to

U31.

Section

timer contained in

U11

of

U9,

the

timer

for

addressing

time

of

and

goes

of

enable the

to

Figure

signal

forced

enabled,

by

ON

signal

the

ROM and

disable

This action switches

instead

and

microprocessor

and then

required

until

the

circuitsintheir

low

enable

to

the

4-4 disables

UUT

address

and

the

microprocessor

point

generated

in

the

of

U25

and

U12.

the UUT. The interval

by

timer

clock

and

for

the

hold

the

by

RAM-I/

RUN UUT

data

the UUT

mentionedinthe

As

executes

performing

the

microprocessor

times

out,

reset state.

the

timing

the

pulse,

address

of

timing

low

hold

0000.

of

circuit

low

are

the address

the

by

timing

O-Interval

mode),

and

address

the

microprocessor

Interface Section.

the

all

a

circuits

timing

buffers,

the

circuit,

directed

decoder

buffers and

and

U26,

mainframe

necessary

timer

TIE

high When the

and

circuits

and

UUT

ON

U12,

disabled,

the

to

U7

circuits,

Timer

are

the

timing

a

is

to

Just

prior

circuits terminate

timing latches

store

processor,

associated

line

an

levels

error.

UUT be

mainframe

When

RUN

the

timing

the

non-RUN

circuits the

to

microprocessor

to

returning

the

address

via

UUT

with

Any

the

at

UUT

circuits

UUT mode.

held

be

condition

line

on

the

error

conclusion

starts

produce

in

state

a

the

to

their

to

the SYNC

of

decoder

the

data

known

conditions

of

the

and

the

high

However,

which

UUT.

reset

signal

all UUT

U7,

bus. The

expected

are

each

command.

interval

UUT

the

maintains

this

In

while

state,

latch

to

lines.

When addressedbythe

latch

each

microprocessor

result and

indicated

timer

produces

ON

signal

RUN UUT

the

mode,

UUT

all

UUT

the

places

considers

in

the

as

command

UUT

RESET,

lines line

condition

the

compares

any

status

the

low

previously

causes

ON

signal

W,

are

logic

the detected

difference

byte

E

described

and

BUSRQ,

stable,

levels.

micro-

of

to

sent

signal,

the

timing

dedicates

the

The

the

to

the

and

for

and

4-13

ZBOQT

WAIT place

The RUN UUT mainframe. to

resume

inputs

the

of

control

are enabled,

microprocessor

The

allowing

removed

mode continues

RESET

of

signal

the

Processor

the UUT

until

from

facilitate

to

a

the

mainframe

Section.

utilize

to

RESET

the

pod

signal

causes

pod

microprocessor

connection.

is

received

the

microprocessor

from

in

the

4-14

ZBOQT

INTRODUCTION

5-1. This section

test

information,

shooting

5-2. SELF The 9000 which provides display Section the test

information.

Series

is

operational

fault

messages

(280,

processor

commands

test

Self

may

alternativemethod known-good

failures.

provides

TEST

RAM, ROM,

section

indicate

maintenance

repair

9100

or

enough

locationtoseveral

mainframe.

the

on

is

necessary

issuediby

does

not

an

U

UT

informationfor

precautions, disassembly

mainframe

Series

to

I/O,

mainframe.

the

examine okay

pod

checking

of

and

mainframe,

communicate with the

and in

the

of

areas

In

order

buses)

orderfor

NOTE

pod

for

when

not

operabilit

pod

can

the

to

must

the

all

observing

Maintenance

the

pod,

procedures,

self

perform

pod

perform

pod

conceivable

completely

a

mainframe.

by

creating appropriate

self

be

operational.

to

accept

operable.

is

exercising

y

reported

any

test,

faults,

Section

and includes

trouble-

and

test

on

any Self

the Processor

Operation

and

execute

and

An

with

a

UT

U

5

self

pod

test

of

self

Performance

the self

test into facilitate

0

self

the

testing (refer

The

high series become

self

of

test

located

socket

test

socket,

also

address

order

resistors. This

data

during

requires

on

the

to

connection

test

a

that

the

pod.

following

the

schematic

lines

are

read

the

When the

connected

operation.

cable

ribbon

electrical connections

diagram

backtothe

allows the

connector

cable

contained

order

high

be

plug

in

data

address

inserted into

is

inserted

made

are

Section

lines

through

bits

to

7):

to

ZSOQT

To

perform

8

An

MHz

signal

replaces

pod.

All

forcing

lines

allows

is

+5V

dc

fail

sensing

self

If

not

shown

Open

using

Turn the

If the

is

reads

Ground

mainframe

1.

as

2.

thumbwheel. socket

3.

4.

display

clock

signal

the clock

lines

and

interrupts

of

testing

applied

circuit.

applied

that

witha9000

test

already

in

Figure

the

Insert

the

to

through

the

pod

connected,

2-1.

of

pins

the

thumbwheel.

mainframe

and

POD SELF-TEST

is

applied

normally supplied

individual

11

to

is

in

Series,

to

are

simulate

the

ribbon

self

the

proceed

the clock

set to

connect

the

Secure

the

ribbon

on

pod

self

and

connector

test

cable

press

are

operating

Z80QT

the active

hardware

UUT

cable

test

configuration.

as

interface

the

socket

into

plug

BUS TEST

OK.

input

the UUT

by

software

or

power

to

follows:

using

by

operating

the socket

normally,

of the

pod.

to

operate

state.

Setting buffering.

and check the

29

to

mainframe

the

to

pod

the

sliding

the

and

self

initiate

to

mainframe

the

This

clock

power

notify

collar.

adjacent

close the

test.

the

these

the

5.

displays pod

further

6.

-ATTEMPTING responding troubleshooting

To

perform

1.

shown

as

If

the

pod

POD

listed

fault

isolate

the

If

podisinoperative,

to

self

test

If

not

already

in

Figure

is

defective

SELF-TEST

in

Table

the

problem.

RESET.

commands

procedures

with

9100

a

connected,

2-2,

but

Z80QT

5-1.

Refer

the

This

issued

isolate

to

Series,

connect

Secure the

not

completely

FAIL

the

to

mainframe

message

by

the

proceed

the

connector

mainframe

the

dead,

where

xx

pod

the

POD

that

represents

the

Refer

the

to

sliding

TIMEOUT

pod

mainframe

collar.

xx,

troubleshooting procedures

reads

indicates

the mainframe.

problem.

follows:

as

interface

using

the

to

is

not

the

to

Z8OQT

FAILURE

FAILURE CODE

CODE DESCRIPTION

00

01

02 03

0

1

2 3 4 5

6—1

3

40-45

2001

2002 2006

2007

2.

Open

thumbwheel. socket

using

UUT

Sell

read

write

Test

access

Table

5-1.

9000-SERIES POD SELF TEST

Control lines

Enableable

9100-SERIES POD SELF TEST

Read

access

Write

access

Control lines

enableable

Disable Sync

Address

Data

Address

Not

mode

lines

in

self

failure

lines

failure

space

test Unexpected Unexpected Unexpected

of the

the

ribbon

self

the

pins

Insert

the

thumbwheel.

Failure Code

failed

be

cannot

status

line(s)

DESCRIPTION

failure

lines

failure

access

powerfail

timeout

pod

response

socket

test

cable

plug

Summary

driven

failed

failure

failures

when

by

into

disabling

operating

the socket

enableable

the

and

close

lines

adjacent

the

3.

Turn

left-arrow

4.

Press

5.

Move

6.

The

display

MAIN:

7.

Press

failure

message

pod

is

the

FAILURE

code.

mainframe

the

to

key

move

the

SELFTEST

the

cursor

should

SELFTEST

the

ENTER

is

inoperative.

=

it

appears,

then

on,

the

cursor

softkey.

the

to

POD

to

key

perform

displayed.Ifa

If

another

refertoTable

the

to

and

the

MAIN

left-most field.

the

press

self-test.Ifthe

press

field

POD TIMEOUT

in

form

5-1

the

for the

failure,

MENU

POD

message

POD

meaning

and

key

softkey.

self

test fails,

is

displayed,

SELFTEST

of

the

use

failure

a

5-3

ZSOQT

5-3.

REPAIR

PRECAUTIONS

CAUTION

Static

discharge can

the

cautions

0

Never circuit mainframe.

0

Perform all

0

Do

0

Wear

0

Use

0

Remove

0

Use

The

soldering

prevent

5-4. TROUBLESHOOTING 5-5.

Pod

messages

overheating

introduction

failure

To

pod.

prevent

when

remove,

board)

repairs

handle

not

static

a

conductive

a

which indicate

ground

all

plastic,

grounded

iron

used

is

usually

the PCB

troubleshooting

install,

assemblies

at

ICs

or

foam

vinyl,

soldering

in

pod

identifiable

pod

damage

this

otherwise

or

static-free

a

PCB

strap.

to store

and

iron.

repair

assembly.

failure

MOS

possibility,

and/

connect

without

work

assemblies

replacement

styrofoam

should

the

from

are:

components

take the

repairing

or

disconnect

or

disconnecting

station.

their

or

from

a

connectors.

removed

the

rating

by

have

mainframe

contained

following

the

[Cs

work

25

of

display.

unit.

PCB

pod

area.

watts

Two

in

pre-

(printed

from

or

types

less

the

to

of

A

0

Troubleshooting based

5-4

timeout

pod

does

pod

of

message

mainframe

Any

recurring

known—good

good,

errors

errors.

and

UUT,

message.

not

respond

also

may

setup

UUT

UUT indicates

attributed

the

pod

requires

When

mainframe

to

due

be

procedures

test

to

is

similar

the

equipment

timeout

pod

a

commands

stuck

to

described

failure

pod

the

to

troubleshooting

forcing

or error

failure.

UUT

by

listed in Table

in the

Since the

the

message

reset

or

lines

not

mainframe

message

UUT

mainframe

other

any

5-2.

The

is

displayed,

pulses.

disabled

’manual.

when

is

known

actually

are

microprocessor-

This

during

testing

type

to

the

be

pod

troubleshooting

a

ZSOQT

in

information fault employing

Figure outlines and

electrical

m3

The schematic

presented

The intended

presented

isolation

normal fault

shows

5-l

identification

points

procedures,

troubleshooting

diagrams

Section

in

troubleshooting

assist in

to

troubleshooting

Centerisrecommended. Refertothe

Service

Fluke

list

for

5-6. Before

determined. depending

If

defective the described

a

the

heading

of

Detective

Pod

attempting

A

upon

fails the self

pod

but

not

under

faulty

Troubleshooting

the

following

but

isolation

the

non-component

superimposed.

interface

the

on

information

containedinSection

4.

guidelines

isolation

the

failstoreveal

Service

Centers.

or

Inoperative?

to

repair

can

of

test,

be

the

but

Troubleshoot

Selecting

pod

the

result

inoperative.

the

heading

paragraphs

provides

techniques.

side

PCB

during

shouldbeused

presented

of

the

pod

a

faulty

categorized

self

test.

does

not

Defective

a

of

faults

fault,

pod,

timeout,

UUT

does

not

troubleshooting

interface

the

Refertothis

figure

troubleshooting

in

7

and

in the

within

return

the

either

as

defective

a

Pod. Select

for Pod

conjunction

the

Theory

following

the

of

the

mainframe Service Manual

level

defective

the

pod

Testing.

provide

PCB

guide

with

locate

to

procedures.

of

step-by-step

for

use

component

with

Operation

paragraphs

pod.Ifattempted

of

is

a

the

to

pod

failure

as

should be

inoperative,

or

consideredtobe

described

suitable

UUT

while

various

the

are

nearest

under

as

is

It

possible

causes

pod

mainframe

attributed

errors

EQUIPMENT

Test

Digital

Interface

Multimeter

Digital

Oscilloscope

Pod

to

a

for

pod

the

when

System

display

to

Table

pass

test

of

used

to test

U

T

the

5-2.

Required

TYPE

Mainframe Fluke

NOTE

test

a

self

failure

a

known-good

are actually

Test

still be

and

or error

Equipment

Fluke

Philips

messages

U

UT.

errors.

pod

REQUIRED TYPE

9000

9000A-2800T

77

or

PM

faulty.

this

In

9100

or

equivalent

3065

or

Such

a

the

on

case,

Series

equivalent

ZBOQT

_.

.....

.u/

ﬁwﬁLﬁﬁgﬁﬁﬁ

“

(51%

;.

ﬁaﬁgggiﬁi

w”

éimwﬁam:

§a§@$$w

my:

3::

ﬁn;

3

_

aagaww

gé§ﬁi§

@

g;

owo

Flgure

,kgg

W

w

awmmawaﬁ

mag

5-1.

lntertace

PCB,

Non-Component

Side

Z$OQT

If the result of

timeout

inoperative Pod. Select Pod

message,

Testing.

The

pod

lines which

during

manual.

5-7.

Selecting

In

order

to

via

pod

normally

applied. testmg:

0

Instead

be

compatible high details).

However, places

mainframe

operation

the

employs a

The

RAM

Z80

compatible

+5V

dc

connection

of

connectedtothe

address lines back

order

insertionofthe

29

of

and

self

a

test,

the

described

pod

as

suitable

a

UUT

timeout

can

mainframe

UUT

a

troubleshoot

cable

ribbon

Z80

UUTisneeded

and ROM

clock

UUT

power

to

self

test

clock

signal,

at

ground.

self

the

test

allows

only

or

any

is

considered

pod

under

described

as

message

disable

for

a known-good

connection.

can

the

procedures

setup

Pod

Testing

pod,

a

and

connector.

microprocessor

to

performing

signal

check

to

socketonthe

+SV

dc,

the

to

cable

ribbon

The

pod

self

testing.

mainframe

other

be

to

inoperative.

the

heading

N

0

also

pod.

known-good

provide

read/

drive

to

the UUT

and also simulates

data

connector

senses

As

under

TE

result

Forcing

as

The

the

UUT, pod.

lines

the

result,

a

described

and

write

the

power

The self

(refer to

ground

Troubleshooting

the

from

UUT

to

following

pod

the

directly

the

operation

heading

stuckUUT

lines

can

the

in

must

maybeany

which

power

functions

operations

sensing

cable

ribbon

socket

test

ROM

schematic

the

into

at

mainframe

produces a

Troubleshoot

an Inoperative

Selecting

forcing

be

disabled

mainframe

be

connected

device which

can

during pod

circuit

connector

provides

by

connecting

diagram

the self

29

notiﬁes

and

inhibits normal

a

easily

test

UUT

to

a

socket

pod

an

for

the

be

may

Z80

the for

the

pod

During

allowed.

cable

connector

connection,

test

To

effectively

connector

1.

troubleshooting

Consequently,

in

the

29

remove

and

modifyitas

Remove

procedures,

the

self

of

29

must

pod

socket.

test

the

connector must

29

the

of

follows:

from the IC socket.

normal mainframe

be

prevented

To

prevent

be

effectively

connector,

obtain

the

from

pod

from

40-pin

a

operation

sensing

removed.

IC socket

the

must

ribbon

the

be

self

or

5-7

Z8OQT

2.

Insert the

3.

Insert

In

addition

disable

traps

Disabling socket

5-8.

to

all

forcing

NO

to

since

during

these

all

Troubleshooting

Thefollowing

identified

the

Timing identified

are

A

is

considered

pod

in

Table

5-1.

For

fact

Section,

that

a

since

self

operation

communication.

Interface

Prepare

Section

troubleshoot

to

modified

the

ribbon

effectively

line and

setup

and

inputs

lines

are

paragraphs

the

Processor

as

Circuits.

the

in

defective

detailed

more

test

can

of

With

the

or

IC socket

cable

connector

modifying

interrupt inputs,

editing

messages

wiredtothe

Defective

a

NOTE

reference

Section,

The

components

Theory

of

when it failsaself

self

be

the Processor

testing

performed

Processor

the

Circuits

defective

Timing

into the

the

ribbon

and

described

as

is

necessary

active

state.

Pod

three distinct

the

which

Operation,

error

indicates

Section

contain

pod as

self

the

into

cable

all

set

in

UU

Tlnterface

makeupthese

presented

test.

analysis,

operation

is

necessary

proven

the

follows:

socket.

test

modified

connector,

line

forcing

the mainframe

when

utilizing

areas

Section,

in

faults

Pod

refer

of

for

be

to

fault.

IC

socket.

be

and

interrupt

manual.

the

of

pod

and

sections

Section

to

4.

summarized

are

5-3.

Table

the Processor

mainframe/

the UUT

good,

sure

self

to

test

The

pod

1.

Disassemble

the shield

and tion

PCB

2.

the means

the

to the UUT

All shooting

noted,

the

under

assembliesatthis

Connect

UUT,

as

of

the

microprocessor

UUT,

although

for

Pod

references

guide

all

mainframe probe

synchronized

the

from

heading

the

pod

shown in

shielded

Testing.)

data and

to

are

mode.

pod by

the PCB

Disassembly.) point.

the

to

mainframe,

Figure

cable,

socket.

suitable

any

in

hexadecimal

removing

assemblies.

5—2.

Note

and

not

Also,

Figure

UUT

NOTE

addresses

operations

assemblies

PCB

the

(Refertodisassembly

is

It

not

necessary

in

ribbon

mainframe

the

of

second

a

5-2

shows

be used.

the

following

Unless otherwise

performed

are

and the

that

by means

may

notation.

from

to

cable

is

pod

the

self

(Refer to

trouble-

the

informa-

separate

connector

connected

socket

test

Selecting

the

in

case,

the

to

by

as

a

Table

5-3.

Recreating

ZBOQT

Sell Test Routines

FAILURE

CODE

00

NOTE

01

02

03

FAILURE

CODE

0

NOTE

1

2

3 Disable

4

5

6

7

9000-SERIES POD

OPERATOR

OPERATION RECREATE TEST

POD

Pod

Reset

READ

@

OFFO =

Cycle

OF READ

(If

a

the

WRITE

@

control

Test

commandtoenable

Send

enableable

each

that

verify

occurs.

a

(This

transparent

OPERATION

POD

Pod

Reset

Read

special

OFFOOFFO

OFFO

0F WRITE

lines

BUS

Enable

line

timeout enabled.

pod

timeout

to

the

9100—SERIES POD SELF

address

and

is

user.)

that

OPERATOR RECREATE TEST

Cycle

READ

(If

a

=

the

Write

data

Special

OFFOOFFO

control

Test

on

Sync

Read

special

OOOOFOOF

Write

data

address

Write

data

0F,

address

lines

all

enableable

ADDR

FE,

00000001

F

D,

address

special

WRITE

TEST

SETUP POD

SYNC

READ

WRITE

address 00000002

SELF TEST

ACTIONS TO

Power

0FFO

@

powerfail

power

TEST

a

detection

OFFO =

@

BUSRQ

timeout

error

occurs

TEST

ACTIONS

Power

SPECIAL

powerfail

power

error

detection

DATA

0F

AT

BUS

ADDR

ENABLE ENABLE

PROBE

TO

SPECIAL ADDR

DATA

FE

DATA

FD

message

circuits.)

OF

WAIT

and

when

ADDR

message

circuits.)

TO

SPECIAL

FFF

BUSRQ

WAIT

POD ADDR

TO

SPECIAL

TO

SPECIAL

separately;

either

TO

OOFFO

00F

0F

occurs,

ADDR

OFF

ADDR

check

verity

line is

check

00FFO

00001

00002

5-9

ZBOQT

5-3.

Table

FAILURE

CODE POD OPERATION

Write

8

address

9 Write

address

10 Write

address

11

Write

address

Write

12

address

13 Write

address

38

Enable

line,

data

first

verify

FB,

00000004

F7,

00000008

EF,

00000010

DF,

00000020

BF,

00000040

7F,

00000080

enableable

pod

occurs

first

Disable

line

39

Enable second enableable pod

Disable enableable

40 Write

address

41

Write

address

42

Write

address

enableable

again

line,

timeout

occurs.

second

line

data

FF,

00000000

data

FF,

0001

FF,

data

MEMORY ADDR

of

space

43

Write

address

FF,

data

MEMORY ADDR

of

space

44

Write

address

data

FF,

of

I/O

Recreating

9100-SERIES

special

timeout

verity

again

special

FFFF

low

high

low

space

Self

Test

POD SELF

OPERATOR RECREATE

DATA FB

WRITE

DATA

WRITE

DATA

WRITE

DATA

WRITE

DATA BF

WRITE

DATA

WRITE

POD

SETUP

POD

SETUP

POD

SETUP

POD

SETUP

DATA

WRITE

DATA

WRITE

DATA

WRITE

OPTION: MEMORY

DATA

WRITE

OPTION:

DATAFFTO

WRITE

OPTION: I/O

ADDR

Routines

TEST

ACTIONS

TEST

TO

F7

TO

EF

TO

DF

TO

7F

ENABLE

TO

FF

TO

FF

FF TO

TO

FF

MEMORY

(cont)

TO

SPECIAL ADDR

BUSRQ

WAIT ON

WAIT

OFF

SPECIAL

SPECIAL ADDR 1FFFF

ADDR

0000

ADDR FFFF

ADDR

0000

ON

OFF

ADDR

00004

00008

00010

00020

00040

00080

00000

5-10

Table

5-3.

Recreating

-SERIES POD SELF TEST

9100

Sell

Test

Routines

Z8OQT

(cont)

FAILURE

CODE

45

2001

2002

2006

2007

NOTE: For

OPERATION

POD

Write

data

of

address

UUT

Pod

connector

socket

test

VCC is

Pod

(no

high

timeout not

on

expected

BUSRQ

and

disabled

information

more

MAINFRAME

FF,

high

I/O

space

cable

in

self

test

power-fail)

WAIT

on

are

these

OPERATOR

RECREATE

DATAFFTO ADDFI

WRITE ADDR

OPTION:

check

None;

SELFTEST

internal

self

the

test socket

(GND).

None;

check and the

cable,

troubleshoot

None;

Disable

enableable

not

report

error codes,

HQ

pod

TO

isinself

ACTIONS

TEST

that

signal

UUT

by

VCC line

timeout.

see

SELF WITH MODIFIED

through

POWERFAIL

defective

a

as

lines.

text.

the

SOCKET

TEST

CONNECTOR

*

is

Pod

FFFF

pulled

cable

signal.

should

test

the

pod.

and

low

UUT

the

at

29

Flgure

5-2.

Troubleshooting

PROBE

”a

DEFECTIVE

Defectlve

3

POD

Pod

5—11

Z8OQT

5-9.

If

self

a

one or

When

troubleshooting

simple

RAM

tests)

then be

SELF

TEST CODE 0

test

produces

of

more

type

used

(such

to

the

as

reveal

trace

failure

a

following

a

pod, perform

reads

afault

a

fault

code of

problems

NOTE

writes

and

symptom.

such

once

0,

is

looping

Opposed

as

A

synchronizedprobe

looping

a

read

UUT

a

indicated:

tests

of

to

has

test

operation

the

most

ROM and

can

isolated.

it

has

failed,

and

To

UUT

power

Control

Address Wrong

further

1.

+5V

line.

necessary,

2.

socket the

place.)

line(s)

data

isolate

Check

UUT

Check

Perform

as

data

Use

If the

a.

line(s)

the UUT.

lines.

mainframe looping

control

b.

If

the

address

the

error,

failure.

If

the

c.

when

using

the

UUT used

indicated.

of

point

performing a looping

sensing

cannot

read

the

trouble,

operation

supply

the

at

read

a

During

address

any

mainframe

display

the

on

failure.

line

mainframe

line(s)

use

data

the

Determine

failure

circuit

of the UUT

the

at

Power

shielded

operation.

(The

error,

indicated

the

probe

read,

selftest

for

using

failure

driven

be

driven

be

proceed

cable

ribbon

Fail

line

cable

self

test

self

test,

containing

indicates

determine

to

the

use

indicates

the

on

or a

indicated

socket,

this

test,

failed

the

read

operation.

follows:

as

sensing

power

connector

PCB-to—PCB

the

at

connector.

Use address

socket sends

read

operations

knowndata

control

a

the stuck

or

probe

address

an

mainframe

locate

to

scope

the

on

is

not

or

lineoraddress line

data

a

synchronized

line(s)

from

circuit

and

OFFO

the

upper

at

if

using

line

error,

control

a

scope

line

display.

the

mainframe identical

the

display

probe or

0V

on connector,

if

using

OFFO

examine

locate

to

error,

point

display,

the

to

by verifying

the

Power

the

address

FOOF

and

other

some

the entire

line(s).

the

note

While

looping

of

address

is

known

failure

and

locate the

a

scope

and

self

byte

UUT.

While

point

failed

not data

while

the

Fail

if

test

to

take

of

on

line

0F

of

is

3.

order

Repeat

to

toggle

steps

2b

and

each of

20

different

at

the address

addresses

and

data

lines.

and

for

different

data

in

ZBOQT

4.

observing

operation

signal

at allows latches UUT

read

5-10.

self

Ifa

indicated:

0

UUT

0

Control

0

Address.hne(s)

0

Data

To

further

1.

the Fail

necessary,

2.

data.

Check

SELF

test

Check

+5V

line.

Perform

is

at

19

of

the

pod

from

self

(or

the

from

TEST

produces

power

line(s)

isolate

the

UUT

Check

at

for

operation

18

U20

of

executed.

10

the

of

PCB-to-PCB

the

communicate with

to detecting test

socket).

from

UUT

CODE

failure

a

circuit failure

sensing

cannot

be

cannot

the

trouble,

operation

supply

the

Power

shielded cable

the

write

a

2f_the

for

(IRQ)

If the

IRQ

shielded

cable

connector.

addresses,

Failure

reaching

1

of

driven

proceed

the UUT

of

the

ribbon

Fail line

1,

as

connector.

code

be

driven

at

operation; use

interval

timer

a low-going

is

signal

connector,

The absence

the

mainframe,

and control

data,

these

of

oneormore

signals

the

cable

microprocessor.

pod

follows:

power

connector

the PCB-to-PCB

of

OFFO

for

and

timing

each

output

and

check

for

UUT ON

a

of

present,

but

signals

also

may

the

of

following

circuit

sensing

and 0V

connector,

the address and

circuits

time

for

a

these

prevents

sent to

prevent

failures

verifying

by

the

on

UP

read

a

SYNC

signal

signals

the the

data

Power

and

for

the

by

is

if

If

the

a.

mainframe looping on

control

If

b.

the address the

error,

failure.

If the

0.

indicatedonthe the

probe

3.

Repeat

check address

to

mainframe

display

the

failure.

line

mainframe

line(s)

the

use

mainframe

a

or

2b and

steps

and data

to

error,

indicated

probe or a

mainframe

to

scope

2c

indicates

determine

the

use

indicates

the

on

indicates

locate the

using lines

control

a

probe

an

mainframe

scope

data

a

display.

FOOF

in

the

or

address

locate the

to

line

While

point

for

the

opposite

line

stuck

a

scope

error,

of

error,

control

line

display.

looping

failure.

address

state.

examine

locate

to

error,

point

note

and

line(s).

note

While

of

the

on

F0

the

point

the

looping

address

failed

the

error,

forthe data

entire

While

of

failed

on

line

line(s)

use

5-13

Z8OQT

4.

observing pin

operation

signalatpin at

pin allows the latches UUT

data

5-11. If

lines

perform

locatedinSection3,for

5—12.

If

is

or

from

Buffering means

RAM-I/

5-13.

SELF

self

test

a

is

indicated.

a

SELF

self

test

a

indicated.

otherwise

the

microprocessor.

of

0-Interval

TroubleshootinganInoperative

for

Check

is

10

19

of

pod

from

self

(or

from

reaching

TEST

produces

To

BUS TEST.

TEST

produces

Eachofthe

interfere

of

the

RESET,

which

gates

operation

18

executed.

of

the

PCB-to-PCB

to

detecting

test

CODE

a

check eachofthe

CODE

failure

a

with

Timer.

the interval

of

U20

of

the

If

shielded

(m)

the

for

m

cable

a signal

connector,

connector.

communicate with the

socket).

the UUT.

2

failure

addresses,

Failure

code

of

data,

of these

failure

2,

control

Refer

interpretation

status

the

to

3

(APPLIES

code

(forcing)

of

3,

heading

of the

TO

failure

lines,

microprocessor

or

and

inhibited

NMI,

are

BUSRQ,

enabled

Pod

NOTE

timer and

low-going

is

present,

The mainframe,

and

signals

of

lines,

Bit

Assignment

mainframe

SERIES

9000

of

oneormore

which have

operation,

WAIT

timing

output

check

for

and

absence

control

one or more

by

may

use

the

are

lines

port

signals

also

the

message.

ONLY)

ability

selectively

is

B

circuits

timeawrite

each

SYNC

for

a

UUT ON

a

of

but

mainframe

~Control

status

accomplished by

outputs

these

prevents

sent

prevent

of

the

line

to

signal

signals

to

write

control

Lines,

buffers

interrupt

buffered

of

by

the the

to

the

The

identified

the identified

A

is

pod

mainframe

from

lack

a

function

response

Prepare

I.

5-14

following

as

Timing

in

considered

operation,

of

response

of

the

Processor

indicates

troubleshoot

to

Disassemble

paragraphs

the

Processor

Circuits.

the

Components

Theory

inoperative

producesapod

by

Section of

failure

the

pod.

reference

Section,

Operation,

of

when the

the

pod

to

the

inoperative

respond

Processor

Refer

three

the UU

that

performance

timeout

mainframe

to

Section.

pod

to

Disassembly.

distinct

Tlnterface

make

up

presented

message.

commands.

mainframe

to

follows:

as

areas

these

in

Section

of self

Such

the

of

pod

sections

4.

test,

a

message

Since

and

or

Section,

commands,

are

any

other

results

is

it

lack

the

of

2.

Remove

the

microprocessor

from

its

Z8OQT

socket.

Refer Section guide:

3.

Connect

to

power

15

for

and

mainframe

second pod.

4.

Connect

mainframe, processor

Do

not

apply

between

ll

A

references

guide

are

the

to

Theory

7

troubleshoot

to

1.

Reset the

cable

connector

2.

Perform

address.

default

the

connector

+5V,

a

then

socket

or

remove

second

data

to

hexadecimal

in

of

pod by

locatedonthe

BUS

a

Instead,

under

pod

normally

21

for

shielded

and

mainframe

connect

of

the

pod

any

and

pod

addresses

and

Operation

inoperative

an

momentarily

Because

test.

set

test

to

and

-5V,

cable

to

a

the

second

under

CAUTION

power

inoperative

NOTE

notation.

in

Section

upper

of

the

BUS

+5V

coupled

second

test.

with

-5V

and

the

to

25

for

ground.

to

provide

pod. Apply

ribbon

pod

ribbon cable

power

mainframe;

self

cable

pod.

in

the

following troubleshooting

4

pod

shorting

PCB

contention

a

test

and the

using

address

schematic

the

22 and23of

pins assembly.

situation,

to

following

supplies. Apply

use

If

available,

test

power

the

to

connected

diagram

steps

the

do

2000.

not

pins

use a

the

to

the

to

micro-

as

shielded

the

use

2

in

a

3.

Perform

4.

Perform

ROM in Table

5.

Check the

U23)

as

a.

lines write

a

checksum

5—5.

follows:

Perform

I

of

/

0

data

RAM

ROM

returned

output

a

port

is

FF.

test.

write

A

The

RAM

ROM

The

Quick

a

by

operation

(PAO—PA7)

addresses

ROM

of

I/O

the

to

as

outputs.

addresses

test

port

A

port

listed in

are

listed in

are

ofthe

A

(contained

direction

write

The

pod

register

address

Table

ROM

in

5-4.

is

U21

to set

is

5-4.

The

given

and

all

2081;

5-15

ZSOQT

VOLT

+5

SUPPLY SUPPLY

—5

VOLT

TROUBLESHOOTER

INOPERATIVE

POD

SECOND

POD

PROBE

5—16

Figure

5-3.

Troubleshooting an

lnoperatlve

Pod

ZSOQT

ADDRESSABLE

RAM

ROM

l/O-Port

-Port

Timer-Divide

Interval

Timer

Interval

UUT

Address

UUT

Data

UUT

Control line

UUT

Address

UUT

Status

Table

Table 5-4.

A

Direction

A

Data

B

Direction

B

Data

line latch

ZBOQT

Pod

Memory

DEVICE

Register

1

by

Disable 2094

line

latch

(high

byte)

latch

line

latch

(low byte)

latch 7000

line

ZBOQT

5-5.

lntertace

Quick ROM

Pod

NO

and

ADDRESS

—

207F

2000

-

1FFF

0000

2081

2080

2083

2082

2090

3000

4000

5000

6000

Addresses

(HEX)

(See

Checksum

Table

5-5)

ROM

ADDRESS

0000

b.

_

high.

c.

logic

d.

e.

6.

Check the

follows:

as

RANGE

1FFF

to

Performawrite

write

The

Check the

levels.

high

Repeat

step

Repeat

step

input operation

address

port

b

c,

CHECKSUM

operation

is

lines

A

00

with

checking

the

to

write

2080;

(PAO-PA7)

the

write

as

all

for

logic

of

0

I/

port

data

with

data..

A

SOFTWARE

A

data

is

FF.

the

levels.

low

(contained

register

probe

1.0

or

in

VERSION

set

to

scope

U21

and

all

for

bits

all

U23)

5-17

ZSOQT

Perform

a.

lines

of

write

data

b.

Perform

while

sequentially pins

input

mainframe

A.

port

7.

Check

repeating

and

address

8.

Check

repeating

write

data

address cable

9.

first address

response

10.

timing

PCB—to-PCB

2082,

connector.

Check

writing

209C.

to

Check

circuits

write

a

I/O

port

is

00.

read

a

2-9

(pins

should

the

output

5

and

step

2082

for

the

input operation

6.

Use

step

00

to set and

apply

operation

00

to

Verify

the second

the

for

as

connector,

operation

A

(PAO-PA7)

operation

applying

of

U2!)

indicate

operation

address 2083 for the

using

the

port

address

line

PB7

both

of

the interval timer

address

occurrence

a

2094

the

that

write

operation.

resultofthe

repeating

by

the

to

as

inputs.

the

at

port

+5V

both

and

observing

each

high

B

of

port

B

data

register.

of

port

2083 as an input.

+5V

m

of

for

and

to

the

ground

reset

output

UUT ON

low

step

A

port

The

A

data

and

ground

the

low

and

(contained

line

B,

port

Perform

(contained

the

timer,

at

lRQ

9.

direction

write

register,

to

mainframe

applied

in

B

port

PB7

(MAINTSTAT)

B

direction

the

to

then

U20,

signal

signal)

register

address

of the

each

display.

the

to

U22 and

direction

register

looping

12

of the shielded

U25

in

and

writing

18,

goes

(produced

19

at

to set

is

2081;

2080,

port

inputs

U24) by

register,

read

26) by OF

low

by

of

all

A

The

of

by

and

at

to

in

the the

Check

ll.

shielded

12.

Check addresses respective

13.

If

preceding checks,

If self

test. Defective

The

troubleshooting

ed

intend

assist

to

troubleshooting

Service

Fluke

list of

for

5-18

a

Fluke Service

for

cable

connector,

both

0000,

2000, 3000, 4000,

decoder

have

repairs

test

operates,

Pod.

guidelines presented

in

the

failstoreveal

is

Center

the

occurrence

repeating

by

address decoders

output

goes

been

madetothe

but

the

reinstall

isolation

the

recommended.

Centers.

pod

of

the

by

5000,

low

when

pod’s

pod

of faults

fault,

Refer

SYNC

signalatpin

9.

step

performing

and 7000.

6000,

addressed.

inoperative

microprocessor

refer

fails,

the

in

preceding

within

the

of

return

the

to

the

mainframe Service

read

operations

Verify

pod as a

to

result

and

attempt

Troubleshooting

paragraphs

lf

pod.

the

to

pod

10

of the

the

that

of

the

self

are

attempted

nearest

Manual

at

a

5-14.

To

gain

DISASSEMBLY

the

two

to

access

PCB

assemblies

within the

pod,

proceed

follows:

as

Z8OQT

1.

Remove the

2.

Remove the

together

3,

screw

To

two

shows

relative

4.

replace

from

5.

each

adapter,

relationships

and

With

which retains

troubleshoot

PCB

the

to

is

Ifit

the

their

To

operate

other,

Fluke

ribbon cable

four

carefully

PCB

the

necessary

shield

the

reconnect

assemblies

the

of

retaining

pod

the

assemblies

location

the accessible

not

standoffs and

part

maintained.

are

plug

Phillips-head

the

open

removed

shield. Remove

NOTE

it

pod,

may

to

except

each

component

non-component

to

separate

screw;

carefully

with

the

in

them

613828.

no.

from

screws

case.

from

the

be

not

necessary

replace

on

the

two

otherwise,

the boards

pull

two

printed

a side-by-side

Make

self

the

holding

shield.

components.

the

sideofthe board.

PCB

circuit

sure

test

the

case

lower

assemblies,

remove

apart

boards

fashion

that

socket.

the

halves,

to

separate

PCB

correct

Figure

the other at

pod

case

remove

the

5-1

assembly

temporarily

the

connector.

separated

using

pin—to-pin

halves

screws

the

from

test

5-19

ZSOQT

INTRODUCTION This section Components

lists

Parts

1.

Reference

2.

Description

3.

FLUKE

Federal

4

Troubleshooter

5.

Manufacturer’s

6.

Total

contains

are

include

an

listed

alphanumerically

the

following

Designation.

of Each

Stock

Supply

Service

Quantity

List of

illustrated

information:

Part.

Number.

Code

Manual for

Number.

Part

of

Components

parts

by

for

Manufacturers.

Section

Replaceable

breakdown

assembly.

Code-to—Name

Per

Assembly.

of

the instrument.

the

(See

list).

Parts

9000

6

Series

7.

number period parts

isolated instrument

HOW

6-2. Components

from the

FLUKE

John

STOCK

Recommended

of

spare

2

of

years.

maintenance

the

at

itisrecommended

site,

stocked.

be

OBTAIN

TO

ordered

be

may

Fluke

Mfg.

NUMBER.

parts

This

quantity:

necessary

list

presumes

site.

PARTS

directly

Inc.

Co.,

This

entry

to

support

an

maintenance for

For

that

at

from

the

authorized

or

an

indicates

to

one

availability

least

manufacturer’s

of

one

representative

the

five

instruments

of

common

1

year

each

recommended

electronic

or more

assembly

number,

part

by using

for

a

at

an

in

the

or

the

6-1

ZBOQT

In

the

replacement

instructions

To

ensure

event

the

will

if

prompt

information.

1.

Quantity.

2.

FLUKE

3.

Description.

4.

Reference

5.

Printed

6.

Instrument

A Recommended

This

price

is

available

kit

the

information

factory.

lists in

parts

Parts

representative. which

ordered has been

part

be

accompanied

necessary.

and

Stock Number.

Designation.

Circuit

Model

Spare

contains

quantities

Prices

are

upon

efﬁcient

Board

and

Kit

Parts

those

recommended.

is

available from

available in

also

request.

replaced by a new or

by

an

explanatory

handling

Part

Serial

for

items

of

Number

Number.

basic instrumentisavailable from

your

listedinthe

the

a

your

and

John

Fluke

improved

note

include the

order,

Revision

REC

QTY

Fluke

Mfg.

Replacement

column

Co.,

Parts

part,

following

for

Inc.

or

Catalog,

and installation

Letter.

the

the the

its

Indlcated

devlces

are

subject

CAUTION

*

to

damage by

static

dlscharge.

ZBOQT

IMI

o

a

z

m

0|

H

INHO

908

mmNB

mmmzbz

UHmmzmu

mmmmDHU<sz¢z

Hm<m

MOI

IWQOUI

qum

mam:

muoam

mmaqm

unozpl

aHnEmmmﬂ

HmcHh

¢

IIIII

mrmmhm

mwmmhm

omovmw

mommow

mHmmmH

mmHNmm

NMHNmH

hppmmw

wmmmw

mmmmm

wmmmm

wmmmw

wmmmm

mommpm

omOHmm

mpmmbm

mommow

NmHNmH

mmHNmm

memmH

prmmm

uuuuuuuuuuuuuu

H

m

H

mhwwwm

meNmm

wmmmm

mHmem

homwvw

wormmm

mvamw

wmmmm

mh«wmm

monmmm

pommqw

memmm

H

mHmem

Huwmmw

ommmm

memm

meHmm

HNHmmm

H

Hm¢mmm

vammm

h¢¢mmw

vmmmom

wmmmm

unmmm

wmmmm

.uumm

Hmvmmw

«mmmwm

mmvmmm

vammw

0>HuHmcmmuoHuMUm

tom

..Huw

oomunoucH

muson

wmm.

HOoledooom

.le

anma

onHmHmummo

...........

a-cm

AuuuumuHmmzpzuA<n

moeczuHmmo

mozmmmumm

«\onvu¢.Ham.m2mm

quzmmm<

Hgmzmmmc

onap<o

oom.oxo«-v.qam.m.mm.=omz.zmmom

onHn<o

mum

mmm.mo<z.zmmum

memmmoomm

mummmmazH

H

«

H

HH

«H

m

<

a

zoaaom

oHsmam

moa

Hop

moa<pao<

‘qumm

.qumm

.Hmmmq

.Hmm<H

m

v

n

m:

m2

a:

uHmmm

szov

moamHmmm\z

m<HHz

MmHn

st

ommm

com

.H<omo

.HmUmo

m

m:

m2

com

sz¢.onHmm

omzidmuomm

Hmommmuo<

.mHmcu

«

H

NH

HH

0H

m2

m:

m

mom

nm<o

HUmemmmm

H¢pzmz

muHoo

acomsnmooom

aoomN

m

ow

monHuomHmzH

moumuHucH

omonHmm

c5300

quo¢oH

app

.9

.mHm<o

mmHo

:H

«

:<

H

m

N

H

2H

=9

29

3

Z8OQT

MP10

Figure

H

2

6-1.

9000A-2800T

Intertace

9000A-Z8OQT-5071

Final

Pod

Assembly

ZSOQT

OI

INFO

le-‘HHHMNI-IQ

HOB

mmmSDZ

mmHMDBUthzmz

Bm<m

qum

mdmz

xvoam

mmbqh

NHaEmmmm

mum

H.Nlm

Hommmooum

ouaon

HH¢

wmm.

IIIII

mmNB

UHMmZmU

MOI

IMQOUI

IIOZII

nnnnnnnnnnnnnn

onamHmommouunlluin-ut«unm

N

rmmhvhmwmwom

Pmmhwhmvmmow

woNH~m>x.>mNHon|+.moH.o.mmu.m<umoNHKwoo.>ooH.onu+~mm0H~mmo~N«o

mmvomm

ommmwh

mmmmm

mmmmmwmmmmwmmmm

ommm¢>mmvomm

NNBOm.H<DQ~¢zomnoH~>o.o>u>m~Hm.maoHo

MNaom.¢zomNnoH~>mpn>m.Hm.mooHo

Mlommnwlﬂ

mnhoo

zHN

wN.uz<

BNHmaoooH.~3om

mmammm

MMHmwmommNHm

NHN

zHN

vmmwow

Mb0hom

vaNow

sz

me.oxovuv.mm¢mm.azm~omu<3m.mwo4Nm

om.meuomH..3om

ow

.Num

NHmmn<mm

H.mmommm

mHnma

~amxuom

ﬁHmHHNNI—IMMHHHNHHN

mmmmwh

Nmmowbovmwommuorom

mmmmmwmmmmmmmmmwmmmmwmmmw

memm

wONH.zmmomN.3mNH..am-+~x>.vszmmo.mmmwONHHSNNomNHSmNH..me+~zN.H.zmmo.mmm

mONH~=NNomN.3mNH..«mu+~mm.zmmu.mmm

HHHHHHHHHHHHH

BQNHHmAsz

HQVOMAVPZ

h¢>oam

wmmmm

hwhoammmmwwbmmmovhammov>ovwwom

chH.3mNH.‘xzzmo.o.:mMo~mmm

Hammvh

Hmvwwh

Hamwwh

vawvh

mONH.2mmomN.szH..»m|+~xN.zmmo.mmm

NONH.2mmomN.3mNH..wmu+.mm.zmmo.mmm

mmvmmm

mmmmwmmmmmmmwmw

wwvmmm

omzz<moomm

NuvaN

zommm

Qmmmqvhz

Nmmmmm

wmmmavmmwa

FHOHVP

meHv>

oHOmHuHma

QHOm.ma<u

mo

unma~m\m

uHom.mmemm>zH

aamzH

NmzmHDNS

mu

N

BHm

Hwoo.HaamH.oH

o<po~HaHmH.uH

xmm.HaHmH.UH

m.mozz.oH

BOﬂmNHmAvhz

Hamomavbz

vwmma«Nmmﬁvmmmﬁwmmmw

owmowbwhmovhNmmmmw

hrmovh

0Hom~ma<u

ozd

HnmzH

UHOm.mam

N

o<po.HHEmH.uH

o<20.HaamH.oH

HNHIZmemmxu

HOﬂvwmAvrm

Hawvwmg¢>z

HDVODUHAVF

Racehv>z

vmmma

uHom~ma<u

oHomHQNmmmmmmzp~mmamm>zH

oz¢z

aoNzH

N

o¢so.aaam~uH

xm:.mozu.0H

oaammm

wmmmw

Nm¢om

vawH

¢waﬁ

oaammw

mwhwwp

mmmovnmmmmomhmmmhh

NNHth

uHOm.m>ma

UHom.ume

oHOmHommZONH.zmm

uHom.m>mo

mzHH\mmmmom

uom+.m\m

mzHH

a

uHa<am

m

Haauo.HsamHm.oH

Hauo.qaemq.oH

Hmso.qaamH.oH

x

mN.uH

fil4<¥i¥iit¥f4li¥4l¥¥ili¥i

-VH

N

Hm

A11||mUHmmzpzlAml

In

~H

N

H

moa<onmmo

muzmmmmmm

0

u

N

moHmu

a

.m

.N

HmH

m2

mHm

mH

NH

um

m

¢

oN

m

~m

N

HN

m

p

a

mH

mN

~mH

w

.«H

.m

.h

.v

9

a

ama

NH

¢N

~HN

.NH

OH

2

ONDNH

NH

5

9

aHH9

ZBOQT

A.u:ouv

>HnEwmm<

mom

A.Nuw

uommwooum

wuzoﬁm

Hﬁc

mom.

.wum

magma

Iml

B

o

z

m

HHHHHH

OI

N

I»HO

NHHl-il—IHHHH

808

IIIII

mmMB

mmmZDz

UHmwsz

mummDBU<sz<2

m39v>me<¢FZm

HQoomHVFZ

Hm<m

m0!

ImQOUI

Mukm

mmhz

mmNHo

mxoqm

xuoem

mmmmmp

--oz--

«

oH0m~wma

uuuuuuuuuuuuu

oom+~m\m

a

onamHmummayulnuunun-uun-m

g¢euo.qeemg<.UH

QbNmAVFZ

mMmOVP

N¢vmmw

mmmmmwmmmm

mmmovn

~¢¢mmm

mmmovn

mmoﬁqn

oHom~me<w

UHOm.mazu

uHom.me4u

moz

sz

oz<z

mH

HomzH

xm

m

w

muzzmmwomm

moH>Ho

mquma.qaamq.uH

o<=o.qaama.uH

.qeamq.uH

«Aqu<m

moalmommAHowoalmovaHQwOHImwNmQHQ

HQmMHmQ¢nz

vmmmavawHvawH

mumo«h

uHom.mAm¢zm\3

owommv

Hon

mmmam

NwmmoNwmmowwmmo

.uumm

~m~m~¢

omomm¢

HN¢«m¢

Famwvw

o>ﬂuﬁmcmmloﬁuwum

Emuomwo

oHumenum

wwm

.muHmm

m

moon

mqu

sz

mm.uH~amxu0m

w-m.qaamg.uH

ov.uH.ammuom

mmumUHucﬁ

sz

s\mﬁuom~wm.ol+~N=zm~q<amwmu

canaou

om.uH~ammuom

~m.

Amy

ozu

ma

neumcoﬁmwv

:«

*

«

cé

wm

mm

AnilumuHMmznz-A<-

.mm

~m~

moe<zuHmma

mozmmmmmm

mw

pm

9

a

s

m

H

N

pm

am

om

ax

ox

a

w

.

mucwumuwu

mUSwHONWH

Hm

“H

muoz

6—6

I

mFmE-EE

II

IImII

a

BB

I

E

II

I

ml&

ZBOQT

O

rm

I

mg

3..

Hmam

a

H

I

mg

I

on

2

.

a

E

m:

Z

\LHUHthmI—w

O

3330

H

E

F

D

hum—dam

G

DHhckw

0

3

«a

ENE

wig

m

~33

2

1

5H“.

O

A11

6-2.

Figure

a,

Processor PCB

n.

gun».

:45

mu

Hun

an

@

ago

Assembly

9000A—

2800T'

1601

ZBOQT

Iml

H

2

o

m

OI

H

[who

FOR

IIIII

mmﬂh

mmmEDz

UHmmzmu

WMMMDﬁodez¢Z

Hmﬂm

Numm

mmhz

muoam

mxoqm

owwmwmvHmomwm

MOI

IMQOUI

mmmmm

ohmmmm

Hmommm

nuozu:

HHNHmI—IHHHNHHNHHMLD

OH

>omEVNNDmNI>NHIHNHmmm

ﬁdmmmooxmoanmmﬂ

ﬂmmUthOHUONMU

Smoaloooﬁlmﬂvm

H¢mHooxw0Hommﬂ

Nmmmmlle

mawwow

HMbhom

mmmwmb

mvvaH

wovam

hmHmHm

NNNvo

pmHmHm

bmHmHm

mHmeH

Hmmpov

mmwmmH

mmmwm

mmwwm

wmmmmwmmmm

mammﬁ

hmmmo

mMmmNm

mwmmom

oowm«m

MHmNow

Hmhnom

mmwomn

z¢mvaA¢v>2m

2vbmauzv>02

mommmml¢la

moowmmIVIH

Nxﬂmmlvlﬁ

ﬂammlvlﬁ

moomoa

¢maawm

wmwmw

mmNHo

Hmoom

mmmmm

Hmoom

HmoomHmoomwmmmm

Hmoom

moo¢oH

mbmHHv

wuvam

Hmvva

mahvo

bNmNHV

HHNpqw

vwmmmm

«mmHmm

r-II-(HI-l

HHHHHH

ZmMHmHvPZm

whvmmm

mmmmwm

mmmmw

mmNHo

memm

whvmmm

«mammm

mmmhov

«wmmmm

z<>wmma¢>2m

ZOVHWVFZm

«Nouﬁm

mmmmm

mmNHo

vmoNHm

oommmv

«memm

uma

HHnewmmm

mom

A.m-w

wumuuwucH

wuaon

«Hc

owmv

.mnm

mHnme

uuuuuuuuuuuuuu

HHsumHo

nmamma

onaomeomm

onamHmommolluu

Ace»

amN~>om.wo~u+.uo-.o.mmu.m¢o

~Hmm<

aHmmHm

..........

onmwx

<ooom

>mm.»0Hu+.maH~m9.m<o

m»x.>ooH~wo~-+.moHo.o~mmo.m¢u

>mH.«o~u+.mDOH.ma~m<u

m

uw

.NH

.v

.HH

v

A-l-«muHmmxbz-Acu

-H

‘m

moawonmmo

mozmmmhmm

m

<

u

c

mH

m

~mH

«H

0H

o

u

uou.>om.wmu+.mmooOH.mmo~m<u

mH

o

zzoom.mzomHnoH.>m>u>m.Hm.mooHo

H

m

-H

mu

men

sz

mz<

ow.mau°mH.o.mzm‘zom

ov~mauooH..zom

o.H\>Hm

zm~.o.wmu+.m~.H.mu.mmm

3m~.o.wmn+~x~.~.hu.mmm

3m.o.onu+.wm~ou.mmm

3m~.o\amu+.xH~mo~mmm

om.Hm.mooHo

N.amxuom

«.mmoamm

m

mu

.N

m

H

N

H

a

v

m

a

3m~.o.emu+.oom‘mu~mmm

p

.m

m

3m~.o~ama+.o~m.mu.mmm

m

sm~.o.wm-+~Hm.o~mo.mum

m

~m

.H

a

Haaoo.HHHmH<~uH

*

m

madam»M\s

wnm+.mamemnm\z

m>ux

mam

m\m

a

Hauo~mozo.uH

H

*

.w

.v

m

.m

a

mm>Hma

mm“

mammzm

mzHH

mnmczm\3

ooomuomamma.»mm<

az<z

moz\:

moon

mzHH

.o.H

m-n.HaamH~uH

onaomeomm

¢

.

h

0H

o

s

mwmaqo>~.o.s

anmzH

magnum

qum

2mm

w

muHma

Hmno~qsam.uH

xmz~HaamH.oH

om.>-.H.oH

amz

mum

{

*

¢

*

H

HH

mH

«H

m>

5

a

ZBOQT

Iml

H

o

z

m

OI

m

H

INHO

BOB

ItlllmeH

mmmzaz

UHmmsz

mummDhU¢mnz¢2

Bm<m

«00

xqmm

Imoool

mum:

xooam

mxaam

-uozus

H

wOHImONMRHQ

Qmm0<|mHN

mﬁQINhHOH

Nwmmo

womam

thFO

.uuwa

Hmvvmv

Hmvvmw

wmmmav

muﬁmhﬁ

..u:ou.>ansumw<

mom

A.m:w

oommuoucH

musuam

:1---:uu-u----onamHmummouuulu

sz

NH:

wmmv

.MIw

wanma

ou.vH.amxoom

.....

auuum

m>H¢HmcmmloHumum

m

m<a~eznoz

mmumo«@:«

sz

cﬁsﬁoo

mosmHmzmmB.mmu<mm

mH.oH.ameOm

‘m.

:H

a<

.w

.m

AnanlmonmzazuAm-

1H

moeaszmmo

muzmmmmmm

m

H

0H

m>x

ax

ox

ax

ZBOQT

N '1

r3.

<1

to

-

U

‘9 <1

>-

m>

‘5”:

2“2

In:

0(1-

:°B a?”

Us:

”a: .l

N’o':

3

J

U

®

:,

_

<1

O

5

.

N

3

O

‘5.’

4

‘1

.

E

.

ﬁe»

r0

3

2:.--

A12

Figure

6-3.

Interface

PCB

@—

9000A-280-1672

Assembly

ZBOQT

FIGURE

7-1.

7-2.

Processor PCB

All

Interface

A12

TABLE OF

Assembly

PCB

Assembly

Schematic

CONTENTS

TITLE

Diagrams

................................

.................................

Section

PAGE

7

7-2

7-8

7-1

Z8OQT

mwmdwwwwmi

E 3

2::asﬁéﬁ

MLVLSI‘IQ

23333329”

o

a

u n v u

:-

ZBOQT

QLVLSNXVI

Figure

7-1.

A11

Processor PCB

%’

.9

Assembly

ZBOQT

A0.

‘m«v

02¢

5:5.

mmmcaa

7-4

tho“

Nu

W

taxman

:th

XEH

35me

hww»m4mm

mu<

m«<

9;

uw<

m<

.v

V

ixu<m3m

Chum!

55¢:

V

0

H

u

ZBOQT

xzw<h<n

lag

taxmammahmmwzm

iku<xn

xx<m=n

lzmur

IkJ<I

*«x

thhKme

J_<L

zwzbu

22b:

Flgure

7-1.

A11

Processor

PCB

Assembly

(cont)

mzornu<l<u

Uu>

Iﬂl

W

ml“

«manna

mm(m>m

7-5

2800T

OUTPUTS

15

7-6

m

Flgure

1-1.

V

PAL

A11

Lﬂ

LOl‘

(U27)

Processor

INPUTS

LOGIC

PCB

[D

Assembly

(cont)

ZBOQT

DEVICE

6ND

14

PINS

Figure

7-1.

A11

Processor

PCB

Assembly (cont)

7—7

Z8OQT

SELF

7—8

LA

HOLD

LO

BUSAK

+5v

ﬁ

if?

C\,2,5,‘|

.22A;

-22L;

l

clz

Em.

+

00.463

0531

tzaF

EEF

L

_____________

_J

ZBOQT

wTﬁ

I.

was

“51510535

Au

ALL

CAPACITORS

OTHERWISE

ARE IN

SPECIFIED

OHMS,l/1w.5CL.

ARE

MICROFARADS

w

A‘E J,“

50>®bN—wu1

MM§9$

UDQ UDI UDZ

UDa U04 UDS

UDE UD‘I

UAqs

UA

UAZ UAS UA4

UAS

[Mb

UAY

UAB UA9

UAIO UAII

Ume UNI: UNA UA|5

I

"ALEZQ'J

ﬂ

Flgure

7-2.

A12

lnterlace

PCB

CIGIOOO

Assembly

9F

9000A-Z80-1072

7-10

7-9/

ZBOQT

Using

READING THE

A-1. The

ZSOQT

Mainframe. interface

the

from

the

POD

READING

A-2.

To

determine

the

From

key

arrow

TLI1

A-3. A-4.

Pod

The

following

SPACE

MEMORY

l/O

The

following

space:

program

end

Z8OQT

the

Pod

databaseiscontained

disk

The

the

of

rest

to

front

panel,

the

panel,

Then

press

softkey,

THE POD

Pod

NAME

front

(->).

PROGRAMMING

Address

Pod

address

TL/l

program

example

s

-

getspace

setspace

examplel

space

DATABASE

file

contains

the

system.

SETUP,

and

SOFTWARE

software

the

press

addressF00012

enter

Options

Space

space

1

space

5

Pod

from

VERSION NUMBER

inadisk

information

To

read

the

then the

the

ENTER

version,

READ

APPLICATIONS

options

segment

"I/O"

right

key.

VERSION

perform

you

the

key,

and

are

demonstrates

TL/1

that

version

arrow

a

SPECIAL

press

available:

Appendix

Programs

file

NUMBER

read

how

the

on

determines

numberofthe

at

special

a

softkey,

to

change

SOFT

key (-v),

ENTER.

9100-Series

Pod’s

the

database

KEYS,

address.

the

and

right

the Pod

A

A-5.

Pod-Specific Setup

Pod-specific defaults,

and

setup

ranges.

Information

information

is

listed in

Table

A-1,

along

with

data

values,

A-1

ZBOQT

The

following

podsetup

TL/

This with

IMPORTANT

podsetup podsetup

podsetup

setup

POD

LREG

*

The

setup

program Pod—specific

All

Standard arguments

Pod—specific

single-quoted

SETUP

LREG

program

end

microprocessor. register (interrupt

address

I

the

register

program

statement.

1

hexadecimal

is

NOTES:

character

(non

podsetup

podsetup podsetup

'enable ‘enable

'I_REG'

nnnn

setup

bus

during an

is

20000h and

demonstrates

data

an

example

setup

strings

Podaspecificl

and

double—quoted

'report

setups

argument

'intr_ack

‘BUSRQ'

‘WAIT'

SFF

Table

allows

This

vector

of

parameters.

are

intr'

either

'seq_reg

"off"

A-1.

ZSOQT

RANGE/

O-FF

users

is

only

register)

interruptacknowledge

it

may

requires

how

to

case

setups values,

“off"

use

followed

on'

SFBOO

ds'

Pod

KEY

to

set

useful

when

take

use

syntax

NOTE

“

$

a

the

use

insensitive.

use

e.g..

a

single

by a

non-quoted

Note,

Pod

are

!

these

so

l

These

!

Pod-specific.

Setup

DEFAULT

valueofthe

the

for

UUTs

it

is

echoed

cycle.

value

any

in

TL/

podsetup

syntax

character.

with

”prefix

single-quoted

though

even

specific,

the

use

examples

Parameters

00

that

use

the

on

The

special

from 0

1

commands

function

single~quoted

value,

'BUSRQ

"enable"

"built'in"

are

all

l

register

the

contents

eight

upper

pod

through

argument

e.q.,

and

is

2800?

NOTES

*

in

bits

address

FF.

for the

or

‘WAIT

not.

syntax.

the 280

of

the

of

the

for

a

|

A-6.

listofthe

A

A-2

List

of

NAME

Address

Data

Pod

Sync

Modes

Sync

Modes and the

I

\

mnemonic

MNEMONIC

ADDR

DATA

eachislisted below:

for

Z8OQT

A-7.

Pod

Calibration

and

Probe

sampled.

mode,

sync reference

Module delay,

another.

value.

default

or probe

labeled tcal

If

When

value.

PODSYNC

Eb

Sync

is

the

are adjusted

To

calibrate

are

you

on

edge

calibration

LATCHED

DATA

Figure

Calibration

process

prompted

that

relative

(as

A-1.

Data

which

by

to

correctly

Module

an

I/O

to

is

signal

shown

is

found

the internal

to

in

Figure

performed,

not

is

performed,

HERE

9000A-2800T Pod Address

the

align

probe

A}

internal

(in

time)

Probe

or

a signal

by

adjusting

PODSYNC

A-l)

default

a

the

measured

45

may

nS

lines

delay

the

clock and

Pod

a

on

the

vary

setting

value

the

delay

signal.

from

for

UUT.

to

r—__

it

tcal

A

‘

~

7

—SPECIFIED

Timing

Sync

in

a

The

one

is

used for

for

a.

I

the

/

signals

particular

The

lines

appropriate

sync

tcal

replaces

_.

Module

0

specified

in

the

mode

the real

EDGE

to

be

Pod

I/O

to

the

Once

in

where

A-l

Figure

offset

the for

address address positive reference

As the

can 9100-Series

is

offset

result

a

mode

sync

be used. See the

reference

time the

contains

listed

data

sync

best

captured

would

edge.)

the

of

in

TL/

is

edge

I

Module

/

0

example

an

in

Table

is

the

rising edge

when

indicate

calibration

If

other

use.

“setoffset”

1

Reference

found,

or

A—2

sampled

process,

offsets

Manual

offset

an

Probe

of

calibration

applies

1—1-5.

of

the address

that

the

required,

are

statement

for

is

applied

latches

for

real

to

The offset

45

before

ns

offset value

the

and

exact

syntax

that

to

data.

address

waveforms.

data

the

rising edge

should be

is

set

1

the

TL/

“getoffset”

and

determine

to

edge

shows how

that

sync

The reference shows

latched

that

to

“setoffset”statement

statement

details.

that

a_valid

of RD.

after

specified

in the

edge

A-3

(A

the

for

ZBOQT

A-2.

Table

SYNC MODE UUT SIGNAL EDGEOFSIGNAL OFFSET FROM EDGE

Pod

Sync

Calibration

Data

ADDR

DATA

A-8.

Available

The

following

Z80QT

QWK_F|LL This

Verify

test, describes

that

in

Arguments:

Pod.

program

test.

see

the

TL

the

mainframe’s

Section

ADDR

This values

UPTO

This

values

or

TL/1

describes

list

embodies

For

further information

3-16.

and

the

test

1

/

program

current

is

the

starting

for

ADDR

is

the

ending

for

UPTO

that of

to

equal

R_—Q

RD

Support

all

of

The

major

is

that

implemented allows

only

address

addressofthe

is

0

address

is

0

through

ADDR.

Rising Rising

Programs

the

available

functions

the

about

difference between the

the

space.

through

of

FFF

of

the

by

Quick

FFFF.

the

Quick

F. UPTO’s value

TL/l

support

the

Z80QT

of

usage

the

QWK_FILL

Fill

and

Fill

test.

Fill

test.

pod

the

Quick

test

Verify

The allowed

The

must

-45

ns

-45

ns

programs

Quick

Fill and

Section 3-16

that

1

TL

/

program

be

to

allowed

be

greater

for the

Fill and

Verify

executed

range

than

is

of

A-4

DATA

is

This

DATA

the

may

ADDRSTEP

is

This

the

address

the value increment.

zero,

ADDRSTEP

data

be

any

is

that

to

numeric value

increment

the

Quick

be

Fill

must

verified

the

for

test

not

or

between

Quick

will

be

greater

writtenbythe

0

and FF.

test.

than

If

to

a one byte

F.

Fill

default

Fill

Quick

ADDRSTEP

address

test.

has

FUNCTION

ZBOQT

This determines Quick

test

Faults:

tesLaborted:

Verify,

or a

respectively.

type,

reason consistency

program

reason argument

reason

conformtothe

reason consistency

program

reason argument

reason

this

test.

whether

“Illegal

and

“Illegal

does

“Illegal

and

“Illegal

does

“Illegal space”.

the

Fill and

Quick

All other values

address

with the

should

address

conform

not

data”.

restrictions

way

data

with

the

way

should

function

conform

not

neverbeseen

Fill

Quick

9000 series

increment".

The value

in

9000 series

The

program

The values

Verify.

illegal.

are

in

invocation”. This fault

testers

in normal

The

restrictions

the

to

the

of

detailed

invocation”.

type”.

above.

testers

in

The valueofthe

restrictions

the

to

current

performs

1,2,

handle the

operation.

value of

detailed

DATA

argument

This

faultisincluded for

handle

normal

address

operation.

detailed

space

Quick

a

3

and

specify

is

included Quick

the

ADDRSTEP

above.

the

Quick

FUNCTION

above.

is

not

does

legal

Fill,

the

FILL

not

FILL

for

a

for

reason does

not

reason does

not

reason conform

reason

the

during

be

never mainframe

“Illegal

conform

“Illegal

conform

data”. The valueofthe DATA

“Illegal

restrictions

the

to

command entered”. A

“New

execution of the

because the

raised

while

restrictions detailed

the

to

address”. The value of

stop

restrictions

the

to

detailed

is

it

program

executing.

address”.

start

The

Quick

valueofthe

the

detailed

above.

command

new

FILL

test.

is

in

complete

ADDR

above.

UPTO

above.

argument

This

argument

does

not

entered

was

should

fault

controlofthe

A—5

Z8OQT

test_failed:

Returns:

QWK_RAM This

For

3-14. test

program current

Arguments:

Nothing.

program

further

The

is

that

only

address

ADDR

reason mainframeisin

be raisedinnormal

never

reason the

data

Slots:

uut_address data_expected

data_read

embodies

information

difference

major

implemented

allows

space.

“Space

does

“Data

read back

all

of

about

between the

the

by

the

Quick

found”.

not

is

known

not

match”. The

not

during

—

The address

The

-

The

-

data

the

functionsof

the

usage

QWK.RAM

RAM

The

the

by

operation.

the

verify

at

that

data

that

was

the

of

that

test

TL/l

be

test

to

current

program.

data

cycle.

which

expected.

was read.

Z80QT pod

Quick

Section

program

executed

address

written

fault

the

RAM

3-14

in

space

This

fault

does

occurred.

RAM

Quick

see

test,

describes

is

that

mainframe’s

the

that

not

Section and

the

should

match

test.

the

TL/l

A-6

is

This

the

for

starting

ADDR

values

UPTO

is

This

the

for

ending

UPTO

to

values or equal

ADDRSTEP

is

This

the address increment

has the

value

increment.

ADDRSTEP

addressofthe

is

0

through

addressofthe

is

0

through

thatofADDR.

the

zero,

Quick

must

FFFF.

for

RAM

be

Quick

the

test

no

RAM

UPTO’s

Quick

will default

than

more

test.

value

RAM

The allowed

The

must

test. to

a one

F.

range

allowed

If

range

be

greaterthan

ADDRSTEP

address

byte

of

FUNCTION

ZSOQT

Faults:

determines

This

RAM

test

respectively.

test_aborted:

reason consistency

program

reason argument

reason consistency

program

reason argument

reason this

reason does

or a

test.

not

Quick

All

“Illegal

and

“Illegal

and

“Illegal

conform

“Illegal

conform

whether

other

does

the

Quick

Pattern

Verify.

values

are

addressininvocation”. the

with

with the

way

should

never

increment”.

address

conform

not

in

data

way

should

never

function

conform

not

space”.

address”.

start

the restrictions detailed

to

address”.

stop

the

to

RAM

program

The valuesIand

illegal.

This

fault

9000 series

be

seen

the restrictions

to

invocation”.

9000

series

be

seen

The value

type”.

the restrictions detailed above.

to

The

current

The valueofthe

The value of

restrictions detailed

testers

in

normal

The

testers

in

normal

address

handle

operation.

valueofthe

This

fault

handle

operation.

of

space

above.

the

above.

performs

2

the

are

is

included

the

Quick

ADDRSTEP

detailed

is

included

the

Quick

FUNCTION

the

is

not

ADDR

UPTO

a Quick

test

type,

RAM

above.

RAM

legal

argument

for

reason

during

never mainframe

reason

mainframe never

test_failed:

reason foundanincorrect

“New

executionofthe

the

be

raised

while

“Space

is

in

raised

be

“Pattern

command

because the

is

it

executing.

found”.

not

is

knownbythe

not

in

normal

Verify

data

pattern.

entered”.

Quick

program

The

current

operation.

Error”. The

A

new

RAM

is

in

program.

Quick

command

This

test.

complete

address

This fault

Pattern

entered

was

fault

control of

that

space

Verify

should

the

should

has

ZBOQT

Slots:

uut__address

data_expected data_read

bad_data__mask

The address

-

—

The

-

The

data

data that

The hex

which

at

that

was read

was

maskofthe

fault

the

expected

bad

occurred

data

bits

Returns:

QWK_RD This

program

further

For

Arguments:

ADDR

The range

Faults:

test_aborted:

See

the

9100-Series

Test

Fault

Nothing.

the

places

information

addressatwhich

values

of

reason to

reason

this

reason

isinis

in

the

specification

test.

not

normal

for

“Illegal

“Space

known

Conditions.

in

pod

Quick

about

Quick

to

perform

ADDR

address”.

detailed above.

space”.

not

by

operation.

TL/l

Looping

is

0

through

The

found”.

the

program.

Reference

the

Quick

The

ADDR

current

The

address

mode,

Looping

for

see

read. The

Manual

read modeatthe

read

FFFF.

argument

address

This

space

fault

space

that

should

list

ofthe

a

passed

Section

does

conform

not

is

not

the mainframe

be

never

RAM

address.

3-12.

allowed

for

legal

raised

Returns:

The value first

UUT

QWK_ROM This

program

further information

For

The

3-15. test

program current

A—B

that

address

major

is

implemented

only

is

that

access

embodies

difference

allows

the

space.

found

the

of

all

of

about the

between the

the

by

Quick

the

address

at

Quick

Looping

functionsof

the

usage

test

QWK_ROM TL/

ROM

test to

specified

read

the

of

that

be

the

by

argument

mode,

ZSOQT

pod

ROM

Quick

Section

3-15

1

program

executedinthe

ROM

Quick

see

test,

describes

is

that

mainframe’s

during

Section

and the

the

test.

TL/

the

1