900
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FLUKE 900
SERVICE MANUAL
NOTE: This manual documents FLUKE900 instruments S/N 4720000 and above.
It also documents any FLUKE 900 vnth the Simulation Option (900-001) installed.
Print Date: September 1992
MN-0004
FLUKE P/N 889691
(c) Copyright 1992
All rights reserved
ZTEST Electronics Inc.
1305 Matheson Blvd.
Mississauga, Ontario
Canada L4W1R1
Table of Contents
1 Service Manual Introduction.................................................................................................................. 1-1
1.1 Description of Operator, Service Manuals .................................................................................. 1-1
1.2 Basic Operation of Keyboard and Display
2 Theory of Operation................................................................................................................................ 2-1
2.1 General............................................................................................................................................. 2-1
2.2 Interface Buffer.............................................................................................................................. 2-2
2.3 Micro Board................................................................................................................................... 2-3
2.4 High Speed Board.........................................................................................................................
2.5 Test Clips........................................................................................................................................ 2-11
3 Selftest........................................................................................................................................................ 3-1
3.1 Reading Selftest Results................................................................................................................
3.1.1 General Selftest Results....................................................................................................... 3-2
3.1.2 Rag Results........................................................................................................................... 3-3
3.1.3 Chip Size LED Error Codes................................................................................................. 3-5
3.2 Running and Reading Individual Selftests................................................................................... 3-6
3.3 Individual Selftest Descriptions.................................................................................................... 3-6
TEST 0 SLFT_CLIP........................................................................................................................ 3 - 6
TESTS 1,2 PULLO_MON, PULLl_MON..................................................................................... 3 - 7
TESTS3,4PULL0_FLT,PULL1_FLT.............................................................................................. 3-7
TESTS5,6SYNCO_Hres_FLT,SYNCl_Hres_FLT
TESTS 7,8 SYNCO Lres FLT, SYNCl Lres_FLT........................................................................... 3 - 7
TESTS 9,10 PINDIS0_FET, PINDIS1_FLT
TESTS 11,12SLFrSTO_FLT,SLFTSTl_FLT................................................................................... 3-7
TESTS 13,14 VccON_FLT, GndON_FLT
TEST 15 PULLPOS FREQ............................................................................................................. 3 - 8
TESTS 16,17 TRIGOALO_EQUAL, TRIGQAL1_EQUAL.......................................................... 3 - 8
TESTS 18,19 QALO EQUAL, QALl EQUAL .............................................................................. 3 - 8
TESTS 20,21 TRIGiT EQUAL, TRIG1_EQUAL.......................................................................... 3 - 8
TESTS 22,23 PULLO_TRIG_EQUAL, PULL1_TRIG_EQUAL
TEST 24 PULL0_TRIGQAL.......................................................................................................... 3 - 8
TESTS 25,26 FM_STAT_NFLT, FM_STAT_FLT......................................................................... 3 - 9
TEST 27 FMASK_WB_TEST........................................................................................................ 3 - 9
TEST 28 FMASK CAL................................................................................................................... 3 - 9
TESTS 29,31,33,35,37,39 FMxx_FLT
TESTS 30,32,34,36,38,40 FMxx_NFLT......................................................................................... 3 - 9
TEST 41 ACT_DIS_CLR...............................................................................................................
TESTS 42,43 PULLO_ACT_TSTON, PULL1_ACT_TSTQN....................................................... 3 -10
TESTS 44,45 PULL0_ACT ACTSTR, PULL1_ACT_ACTSTR
TESTS 46,47 FREQ_BIAS_'§HORT, FREQ_BIAS_LONG
Interface Buffer shift register subtest.................................................................................... 3-10
Frequency HW subtest.......................................................................................................... 3-11
Threshold HW subtest........................................................................................................... 3-11
Reset HW subtest................................................................................................................... 3-11
Result bytes: ........................................................................................................................... 3-12
TEST 48 KEYBQARD OPEN........................................................................................................ 3 - 14
TEST49TEST_CYCLE................................................................................................................... 3-14
TEST50UART_TEST..................................................................................................................... 3-16
TEST 51 DGATE_TEST................................................................................................................ 3 -17
TEST 52 PULLO XTRIG
..............................................................................................................
.................................................................................. 1-1
2-6
3-1
.........................................................................
..................................................................................
.................................................................................... 3 - 7
..................................................
........................................................................................... 3 - 9
....................................................
.........................................................
3-7
3 - 7
3 - 8
3 - 9
3 -10
3-10
3 - 19
TEST 53 PULLl XTRIG................................................................................................................. 3 - 20
TEST 54 PULL_XEVENT.............................................................................................................
TEST55SHADINIT........................................................................................................................ 3-21
TEST E60 WALK_SIZELEDS....................................................................................................... 3 - 22
TESTE61 TESTMEMORY............................................................................................................ 3-22
TESTE62WALKMONLEDS......................................................................................................... 3-23
TEST E63 UPDATE VCC LIM..................................................................................................... 3 - 23
TEST E64 SHAD ADDR .7........................................................................................................... 3 - 24
TESTE70KEY_CLOSURE............................................................................................................. 3-24
TEST E71 DISP_RAM................................................................................................................... 3 - 24
TESTE74DISP_CHAR_SET
TESTE75CART_SLFT................................................................................................................... 3-25
TEST E76 TEST C ENG................................................................................................................. 3 - 25
TEST E77 ACT_CROSS................................................................................................................ 3 - 25
TESTE78TRG_CROSS................................................................................................................ 3-26
TESTE79FRQ_CROSS.................................................................................................................. 3-26
TEST E80 FLT_CROSS.................................................................................................................. 3 - 26
3.4 System Error Codes.................................................................................................................. 3-27
4 Troubleshooting....................................................................................................................................... 4-1
4.1 Test Result Interpretation............................................................................................................. 4-1
4.2 Selftest / Circuit Block Reference Table....................................................................................... 4-2
4.3 Selftest Circuit Block Diagrams
4.4 Failure Examples............................................................................................................................ 4-23
4.4.1 IB Reversal........................................................................................................................... 4-23
4.4.2 Static-blown HSB................................................................................................................ 4-24
4.4.3 Missing -5 V......................................................................................................................... 4 - 25
......................................................................................................... 3-25
...................................................................................................
3 - 21
4 - 4
5 Maintenance............................................................................................................................................. 5 -1
5.1 Performing a Complete System Checkout..................................................................................... 5-1
5.2 Performing Adjustments................................................................................................................. 5-2
5.2.1 Adjustment to Vcc................................................................................................................ 5-2
5.2.2 Adjustment to Display Contrast
5.2.3 Changing System Firmware ............................................................................................... 5 - 2
5.2.4 Fuses and 110/220 V Conversion........................................................................................ 5-3
5.3 Disassembly and Assembly Instructions........................................................................................ 5-3
5.3.1 Microprocessor Board.......................................................................................................... 5 - 3
5.3.2 Keyboard.............................................................................................................................. 5 - 4
5.3.3 Speaker................................................................................................................................. 5 - 5
5.3.4 Display Controller
5.3.5 Display.................................................................................................................................. 5 - 5
5.3.6 High Speed Board................................................................................................................ 5 - 6
5.3.7 Power Supply....................................................................................................................... 5-6
5.3.7.1 Fan.............................................................................................................................. 5 - 6
5.3.8 Interface Buffer Board......................................................................................................... 5 - 7
5.4 Calibration Procedures ................................................................................................................... 5-7
5.4.1 Interface Buffer Calibration................................................................................................ 5 - 7
5.4.2 High Speed Board Calibration
5.4.2.1 Calibration Data Format............................................................................................. 5-7
............................................................................................................... 5 - 5
.........................................................................................
............................................................................................ 5-7
5-2
5.42.2 Calibration Standards............................................................................................... 5-8
5.4.2.3 HSB Component Placement...................................................................................... 5 - 8
5.4.2.4 The Offset Shift (OS) Definition............................................................................... 5 - 9
5.4.2.4.1 Example 1 (for negative offsets)
..................................................................
5-9
u
5.4.2A2 Example 2 (for positive offsets)......................................................................... 5-10
5.4.2.5 The Correcting Component Definition
5.4.2.6 Calibration Procedure
5.4.2.6.1 Offsets Block
..............................................................................................
.................................................................................................. 5 -12
...................................................................
5-10
5-12
5.4.2.6.2 Limits Block.................................................................................................. 5-12
5.4.2.6.3 Selftest buffer and 86 gate related condition................................................. 5-13
5.4.2.6.4 LM360 comparator related condition
.............................................................
5-16
5.5 Board Revisions, Upgrades and ECOs.......................................................................................... 5-16
5.5.1 Modification to MB for 64k Cartridges.............................................................................. 5-16
5.5.2 900 System Firmware......................................................................................................... 5-17
6 Schematics................................................................................................................................................6-1
6.1 INTERFACE BUFFER - IB............................................................................................................ 6 - 1
6.2 MICRO BOARD - MB rev.2 (M2) ............................................................................................... 6 - 3
6.3 HIGH SPEED BOARD - HS rev.2/3 (H3)
...................................................................................
6 - 5
7 Fluke 900 Parts Lists................................................................................................................................ 7-1
7.1 900 Final Assembly........................................................................................................................ 7-2
7.2 A1 Interface Buffer IB................................................................................................................... 7-4
7.3 A2 Micro Board M2 ...................................................................................................................... 7-6
7.4A3 Highspeed H3
...........................................................................................................................
7-8
7.5 A4 Power Supply Module PA....................................................................................................... 7-11
7.6 900-001 Simulation Option......................................................................................................... 7-12
111
FLUKE 900 SERVICE MANUAL
Service Manual Introduction
1 Service Manual Introduction
1.1 Description of Operator, Service Manuals
Documentation for the FLUKE 900 Dynamic Troubleshooter includes the Service Manual,
Operator Manual and Training Manual. For the purposes of maintenance and repair relevant
sections of the Operator Manual are:
Section 1.2 on Specifications
Section 1.4 on Ship>ping, Unpacking, and Connection
Section 1.5 on Keyboard Operation
Section 1.6 on Option Setting
It is recommended that the reader become familiar with this information and peitiaps the section
on Technical Principles from the Operator Manual before undertaking service repair of the unit
While some tasks in the Maintenance section of this Service Manual are relatively simple,
calibration and most troubleshooting require a thorough imderstanding of the information
presented in sections 1,2 and 3 of this Service Manual.
1.2 Basic Operation of Keyboard and Display
The FLUKE 900 display has 4 major areas:
- Information area in the upper portion of the screen
- Status line reverse highli^ited in the middle of the screen
- Command line for entering instractions below the status line
- Function key labels reverse highlighted at the bottom of screen
There are 5 Function
Permanently labelled keys are represented
of levels and sub-levels with the Function Keys. (^, on the left of the Function Keys, moves
operation up one level of the menu tree, brings up more labels on the same level of the tree.
Data that is typed in appears on the command line, but is only acted upon after [ento») is
pressed. @ perfonns a backspace function on the command line; 1^™^) ii erases the last word;
[cNTRj gg erases the whole line.
The Debug mode is used for observing selftest results, running selftests and printing results. It
may be entered, after a successful selftest, by pressing ES(system) IH) EXdebug) from the main
screen of the initial level. Debug is accessible directly after a poweron selftest fails. The menu
tree for the Function Keys after a fail spears as:
Key labels and they are represented in this manual as: (ES(label).
as: l enter j. Operational modes progress down a tree
1 -1
Service Manual Introduction FLUKE 900 SERVICE MANUAL
©(restart) will re-execute the poweron selftest.
©(ignore) will bring up the main screen directly. If any of the failed selftests involve actual
testing circuitry (eg. FMxx), the operator will not be permitted to actually run a test cycle. File
manipulation, RD Test and System setting changes are possible, however.
Debug has three main keys: ©(run), ©(display), ©(prt_res). The last one means "print
results" and sends a formatted listing of all test results from the last test(s) executed to the serial
RS232 port, "display" brings to the screen, the characteristic 4 b)4e in^vidual result of the test
whose number was entered on the command line. This test must first have been run, either
explicitly or during the powerup.
The key labels under "run" are words that can be used to compose a command line instmction.
Some typical instmctions are:
Rim_test clip
Run test 0
Run test 40
Run_test 1 thm 40
Run test continuous
Run_test 46 continuous
until_fault
Run_test 1 looping
These two equivalent instructions run the clip continuity test.
A clip must be inserted in the Input Bufter and clipped onto
the Dummy Chip Module which must be plugged into the
ZIF socket. Results are shown on the screen.
Test 40 is executed and result bytes displayed in the case of a
failure.
Tests 1 through 40 are executed successively.
The series of poweron tests are executed repeatedly with the
number of passed and faUed cycles displayed on die screen.
will terminate it upon completion of the currently
executing test. This is a useful bumin procedure.
Test 46 is executed repeatedly while displaying the number of
passed cycles until the point at which a failure occurs.
Test 1 win execute repeatedly to facilitate signal tracing with
an oscilloscope.
1 -2
FLUKE 900 SERVICE MANUAL Service Manual Introduction
At any point in the menu tree or any operational mode of the tester, a hard or soft reset may be
executed. Pressing (shift] and (^) simultaneously causes a soft reset that returns the display to
the initial power-on screen. This action does not erase any files that are resident in volatile
system RAM. For service purposes a soft reset during selftest is a convenient way to truncate the
selftest and bring up the main screen immediately. Pressing
a hard reset that clears memory and restarts selftest.
There is a special keyboard mode used mainly for calibration called the "engineering menu". It
may be entered from the main poweron screen by simultaneously pressing (cisto) and an
unlabeled key found between and (testJ. Its use will be described in the section on
calibration.
(cnthj and simultaneously causes
1 -3
Service Manual Introduction
This page intentionally left blank.
FLUKE 900 SERVICE MANUAL
1 -4
FLUKE 900 SERVICE MANUAL
Theory of Operation
2 Theory of Operation
2.1 General
Major functional blocks of the tester correspond, in general, to physical modules. Shown below is
a diagram of the modules and their interconnections.
The Interface Buffer (IB) acquires and conditions signals from the board under test. It accepts 28
signal channels from an interchangeable clip and, by means of a single threshold setting,
translates them into ECL digital data for transmission to the High Speed Board.
The Micro Board (MB) controls the operating system, user interface and test parameter storage.
The Micro Board has a Z80 microprocessor running from about 320K of paged memory space.
The software is mainly comprised of interrapt routines that service four 8536 CIO devices. Two
CIOs are on the MB, the "Keyboard" and "Map" devices, while two CIOs are on the HSB, the
"Time" and "Frequency" devices.
The Micro Board sets up the High Speed Board (H3) with the proper configuration for a test
before letting it run at high speed without intervention. The setup of the test proceeds by loading
a series of shift registers with data impropriate for the test to be performed. Four 8 bit registers
are cascaded to make a set of 32 bits in length. Six such sets are located on the H3, two on the IB.
2-1
Theory of Operation
During the test phase, signals received by the H3 are routed immediately to a comparison circuit
to be matched against one of two possible signals. In the case of a signal extracted fix)m a DUT
input pin, the comparison is made with itself ( no failure should appear ). In the case of a DUT
output pin signal, the comparison is made with the identical RD pin signal. The RD pins are
continuously monitored by a resistive load to determine whether tiiey are input or output and
thus how to route the equivalent DUT signals. At each signal transition, the DUT/RD
discrepancy is timed to see if it exceeds a set FMASK value. If so, and if not overridden by a Gate
or Trigger setting, the faults are latched and displayed on the monitor LEDs and LCD Screen.
FLUKE 900 SERVICE MANUAL
2.2 Interface Buffer
Pages 3,4,S,6 of the IB schematics show the signal path for each of the 28 channels that can come
from a DUT. lOK resistors connect each channel to an output bit on the cascaded shift registers
shown on page 1. In actual usage, these are resistors pulled up to 5 volts by default to resolve
floating imconnected inputs on a UUT which could otherwise confuse test results. In addition,
the check for a low condition on a pin is made while attempting to pull it high; the high check is
made with the lOK resistor pulled down to ground.
After the impedance matching components and protection diodes, each chaimel feeds a
comparator referenced to a bias voltage. The ouqjuts are differential E(X levels for relative
noisefiee transmission to the High Speed Board.
The shift registers shown on page 2 are used to control the bias setting for threshold, the Reset
line setting and external frequency multiplexing. Eight bits drive a DAC which resolves a 0 to 5
volt range into 100 mV increments. Five bits control the polarity, voltage and status of the Reset
driver (Page 1). Three bits route one of several lines through an analog multiplexer to a
voltage-controlled oscillator (U25). The measurement of the VCO frequency on the HSB is used
to determine clip size ( from a characteristic voltage divider in each clip), threshold verification
and VCC accuracy.
2-2
FLUKE 900 SERVICE MANUAL
Theory of Operation
2.3 Micro Board
The Micro Board architecture is shown in the accompanying diagram. Note that, for
simplification, bus buffers are not shown and all chip select signals are shown as CS to a device
instead of the actual signal ( eg. CS for MAP CIO is actually MAPSEL ). The Z80 CPU runs at 6
MHz and operates with the Wait State Generator PAL (U69) to give the delayed control signals
WRD and RDD. The CPU signals WR and RD are thus modified for the timing requirements of
the Display Controller and the 8536 CIO chips. The four CIO devices are complex counterAimer
and parallel I/O ports. Two are located on the MB, two on the HSB, and they interrupt the CPU
for servicing of their particular function.
The MAP CIO sets up the memory map and paging scheme through PALs U58, U59, U72, U73.
Port A is configured as output for the PAL chip selects. Port B is output for the EPROM chip
selects. Port C is output for the RAM chip selects. The internal timer on this CIO is used for
general timeout purposes in such functions as cartridge operations and library loading.
The Decode Logic consists of the PALs referred to previously and it generates chip selects for all
peripheral devices and extends the 64K address range of the Z80 as shown in the memory mt^
diagram.
The first 16K is the power on
boot ROM space (ROM
SYSAF is part of it). The
next 8K of CPU address
space is used to access 14
pages of 8K in size residing
on the SYSAF and B ROMs.
The next 8K starting at
address 6(X)0 accesses 14
pages residing on SYSC and
D ROMs. The range 8000 to
COOO is 16K of static RAM.
The first RAM chip has a
battery and retains the
System Mode option
parameters. It also has 8
pages of cartridge memory
and 16 pages of library
ROM. The final 16 K is
overlayed with 4 pages
comprising the DRAM and
used for internal functions
and 48K of ":SYST"
sequences.
4000
6000
8000
AOOO
COOO
FFFF
16k
SYSAF
8k
OVERLAY
8k
OVERLAY
8k
SRAM
8k
SRAM
15k
DRAM
Ci;234S6iS9ABCiQ
C i:24436789A8GD
I N : i M M :; M pages SYSD
i|234S67aT234367a3ABGDEF g
j 15 pages library
23
4 pages rSYST
14 pages SYSAF
14 pages SYSB
14 pages SYSC
The Keyboard CIO outputs levels on port A which are read back on port B when a key is
depressed. Three internal timers designated "watchdog", "key_time" and "key" take care of
2-3
Theory of Operation
debouncing and repeating key actions. The itest) and inext) keys found on the Interface Buffer
are routed through the HSB and optocoupled on the MB to connect to the keyboard CIO. The
chip size LEDs are driven by a latch controlled by this CIO.
The dual UART located at Ull is used for two functions. First, the serial RS232 interface is
connected through a DTE/DCE selectable routing circuit so it can interface to various computers
and printers. Second, various standard frequencies are generated to drive a speaker providing
audible beep tones. The socket at U62 contains the battery and circuit for the real time clock
function.
FLUKE 900 SERVICE MANUAL
2-4
FLUKE 900 SERVICE MANUAL
MI CR D BOARD A RCHI TEC TU RE
Theory of Operation
□sc
CPU (1)
\/
(1)
INT
TESTDN
MDN BUS
(MSB)
CARTRIDGE
RS232
SPKR,
H I G H S P EED B E AR D
2-5
Theory of Operation FLUKE 900 SERVICE MANUAL
2.4 High Speed Board
The accompanying diagram shows one chamiel routing a signal from the test clip through the
Interface Buffer to the High Speed Board (H3) where it is processed by Dynamic Reference
Comparison. The Micro Board then receives indicators from the H3 to display a test result There
are 28 such channels in parallel. The circuit elements that are depicted as latches in the diagram
are implemented with shift registers that are first serial loaded, then clocked to a parallel ou^t
latch. The diagram’s latches are single bits of a 28 bit shift register comprised of four cascad^ 8
bit 74595s.
2-6
TEST
CLIP
INPUT BUFFER
MICRO BOARD
'f-
.-UPS
©
ACTIVITY
MONITDR
HIGH SPEED BGARD
BUFDATA
w
SYNCLÖAD
SYNCCLK
SYRCEN
° Q
RCK
SRCK
SYNC
_____
©
BUFDATA
SLPTLOAÖ
SLFTCLK
C
m
CO
o
o
CO
m
3J
<
o
DIFTEST
BUFFER
□UT <DC)
m
>
z
c
>
MGNBUS
EBUS.IN FAULT.IN
LATCHING
CIRCUIT
OUT
SELECT
\ /
OUT
FRAMING IN
CIRCUIT
CLEAR
vw— °
PIN-DIS
LATCH
SRCK
RCK
©
BUFDATA
öiSloaü
DISCLK
.TO TEST CYCLE
7 CONTROL
ro
•nI
(14)
(D
“O
O
O
O
CD
O
3
FREQUENCY
COUNTER
CMUX)
EXT-
I
GATE-
10)
Theory of Operation
The busses shown are as follows:
EBUS
External bus represents DUT signals after conversion to TTL levels using a single
threshold in the IB. EBUS is labelled on pages 2, 4, 6, 8, 9, 10, 11 of the H3
schematics.
RDBUS
Reference device bus carries EBUS input pin signals to the RD socket and RD
output pin signals to the DIFTEST circuit. RDBUS is labelled on pages 7, 8,9,10,
11 of the H3 schematics.
EBUS
Fault bus indicates on which pins the RDBUS and EBUS were different for longer
than the FMASK value. The FBUS consists of the op amp ouQ)ut signals labelled
Fxxon pages 8,9,10,11 of the H3 schematics.
SYNCBUS
Synchronizing bus is either the EBUS or a pattern from the device library,
depending on whether the Sync Vectors technique is employed to synchronize RD
and DUT. The SYNCBUS consists of the 74244 output signals found on the
extreme left side of pages 8,9,10,11 of the H3 schematics.
FLUKE 900 SERVICE MANUAL
MONBUS
Monitor bus is either the same as EBUS or FBUS, depending on which is selected
for display on the monitor LEDs. The Mon bus may be found at connector J3 on
the right side of pages 8,9,10,11, of the H3 schematics and on page 13 of the MB
schematics.
The 18 circuit blocks shown in the diagram on the previous page are the same ones listed across
the top of the Selftest/Circuit Block Reference Table (Section 4.2). Fifteen of the blocks
described below are found on the H3 Board.
1.
PuUups Latch
On the Interface Buffer, signals from the test clips are pulled up to VCC or down
to Gnd through a lOK resistor from the output of this shift register latch. It is found
on page 1 of the IB schematic, Ul, U2, U3, U4. The register at U24 of the BB drives
a DAC which sets the threshold.
Inbuf
These buffers found on pages 8,9,10, 11, of the H3 schematics (U186, U140, U95,
U42), feed the EBUS through to the SYNCBUS. They are tristated when the Sync
Latch is driving.
Sync Latch
Synchronizing patterns from the library data are shifted ink) the registers shown on
pages 8,9,10,11, (U182, U136, U91, U45) and then latched to the output as a test
vector. The stimulus for the RDTest ftmction is provided in the same way.
2-8
FLUKE 900 SERVICE MANUAL Theory of Operation
Diftest Buffers
This circuit uses one of two possible resistor values (Hi or Lo) to determine
whether the RDBUS can drive and therefore whether the pin is an output The
final output indicates the discrepancy between RDBUS and EBUS/SYNCBUS. It
may be foimd at the outputs of the exclusive OR gates on pages 8,9,10,11.
Self Test Latch
The shift register latch used to inject patterns onto the RDBUS during power-on
verification in earlier revison boards is incorporated into the Logic Cell Array at
U105, near the ZDF socket of the H3 Board. This is shown as circirit block 17 on the
block diagram. If a RD is inserted during the power-on test an t^arent failure will
result
RD Supply Relays
Certain ZIF socket pins are cormected to VCC or Gnd by closure of the relays
shown on page 7. The shift registers U155 and U102 control their selection.
Pin Dis Latch
These shift register latches can override the fault indication output from the Diftest
circuit to ignore a fault on a pin. They are shown on pages 8, 9, 10, 11, as U180,
U134, U89, U40.
8.
9.
10.
11.
FFCLK Line
The CPU can simulate a fault by asserting this line which is ORed with the pin fault
lines to produce FLTS, the master fault indicator (page 11, A-10). Shift register
U67 (page 3) provides data to a DAC which provides the FMASK reference
voltage used in the framing circuit. The charging of precision capacitors to this
voltage establishes an FMASK value. Note that ttie 74ALS09s driving the
capacitors are specially prescreened to be uniform.
Mon Mux
The latches at U198, U153, U112, U64 hold the individual pin faults. The PALs
driving them are also latches which accumulate faults for 40 ns after the first line
fails but no further. In this way, the results are frozen in a window around the first
fail for later reading by the CPU over the Mon Bus. When no faults are present,
the signal M/F selects U164, U122, U76, U43 (pages 8, 9, 10, 11) to route the
EBUS onto the MONBUS.
Freq Circuit
The 8536 CIO at U27 (page 4) controls the multiplexing and measurement of
signal frequency among the 29 channels (28 pins plus 1 external). Port A is
configured as output and used to drive the muxes at U55, U66, U124, U141. Port B
drives the FREQ PAL except for PBS which is an input flagging the occurrence of
Gate. Port C is an input to read the frequency count.
Trig Buf
These buffers U191, U154, U98, U81 on page 2 enable the EBUS to the trigger
comparator when TBEN signal is active.
2-9
Theory of Operation
12. Trig Data Latch
The shift register latches U166, U189, UlOO, U78 are loaded with data indicating Is
and Os of the Trigger word. The first word is serial shifted and latched followed by
the second word which is not latched until the occurrence of the first.
13. Trig Qual Latch
The shift register latches at U168, U188, U96, US6 are loaded with data indicating
which pins have a 1 or 0 and which have "don’t care" conditions. Two successive
words are loaded as in the Trig Data case.
14. Activity Circuit
This circuit on page 7 of the Micro Board schematics operates by latching the state
of all pins at the start of test and generating an exclusive OR pulse if the state ever
changes, hi this way, the PALs U32, U21, U16, U22 are alerted of active pins.
15. Mon Bus Readback
The Mon Bus which comes from the ffigh Speed Board to the Micro Board via the
connector J3 is shown on page 13 of the MB schematics. The latches and PALs on
page 7 use the Mon Bus to hold the state of all pins at the end of test (for the EoT
test result). The state of pins at the start of test is also latched here for the purpose
of checking H or L conditions on DUT pins.
FLUKE 900 SERVICE MANUAL
16,18. Shadow Ram and Delayed Gate Circuit
This circuit is implemented in the Logic CeU Array at U123 (page 6) and associated
PALs. Both of these functions affect the gating of comparison. Shadow RAM
inhibits comparison during reading of an uninitialized DUT memory cell. Delayed
gate inhibits the normal gate signal from going true for a fixed time interval after its
pin conditions are satisfied.
17. RD Emulation Circuit
This Logic Cell Array, located at U105 (page 12), simulates certain Reference
Devices instead of using an RD in the socket. If an H3 Board does not have the
Simulation Option instafied, U105 is still present to perform selftest functions.
Test cycle control is applied to all 28 channels together and is found on page 3 of the H3
schematics. The Time CIO at U26 is configured so РАО, 1,2 enable the Trigger flip flops and
GATE PAL. РАЗ is an output for enabling comparison during selftest. PA4 is an input that
detects whether gate occurred. PA5 is an input indicating a short in the RD socket. PA6, 7 are
inputs that detect whether trigger word 1 and 2 occurred.
Port В controls the Test Cycle PAL; PBl is an input which stops test after a fault has been
captured. PB2, 3, 4, 5 are inputs from a counter which acts as a prescaler for the time-to-fault
interval. An internal CIO timer converts it to a value in the proper range. PB6 is an output that
clears the fault under CPU control, while PB7 is an input indicating a fault is present Port C is
configured as an output and it selects which shift register will receive the data stream from the
register U36 on page 1 of the H3 schematics.
2-10
FLUKE 900 SERVICE MANUAL
Theory of Operation
2.5 Test Clips
The standard Test Clips have no active components, but the ribbon cable is temiinated at both
ends with a series 300 ohm resistor for impedance matching. There are 10 Kohm puUup resistors
in the Interface Buffer which are applied to the DUT through the 600 ohms of the Test Clip.
The High Impedence Test Clip has an active buffer at the clip head which presents 500 Kohm
impedence to the DUT. The clip head is powered from the VCC pin of the DUT.
2-11
Theory of Operation
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FLUKE 900 SERVICE MANUAL
2-12
FLUKE 900 SERVICE MANUAL
3 Selftest
3.1 Reading Selftest Results
Immediately after poweron, the tester executes a series of selftests that take about one minute.
The selftests may also be initiated at any time by simultaneously pressing (.cntrj and (^. The
tests are number^ 0 to 55 and all but a few are run automaticaUy. These few plus a number of
"extended tests" denoted by Exx (eg. E60), can be run by manually keying them in when analyzing
a problem. All the tests may be run individually in this way to produce "individual test results".
When a failure is encountered during poweron selftest, two rows of digits display "general results"
and sometimes a third and fourth row appear. Rows 1 and 2 indicate the failing test numbers;
rows 3 and 4 indicate fault flags that are tied to memory and shift registers. Flag failiues indicate
major functional problems and general test results indicate which tests are failing. "Individual test
results" are more detailed dispays of the failing tests and they indicate which channels (lines) ate
faulty.
In cases where a failure is severe and the LCD screen may not function, the LEDs around the
ZIF socket may indicate the problem.
Selftest
Hardware and software problems occasionally result in system crashes that present a message on
the command line. One cause of such a crash is a corrupted simulation library file. A summary of
these messages appears in Section 3.4.
3-1
Seiftest
FLUKE 900 SERVICE MANUAL
3.1.1 General Selftest Results
The general results on the first two lines are clustered in groups of five as shown in the
example below. The test numbers are shown above and below the digits. 0 indicates Pass, 1
indicates Fail and X indicates that a test result is not available.
0-4 5-9
XOOOO 00000
00000 01000 00011
30-34
The cross reference of test numbers to test names is listed below:
SLFT CLIP
0
PULLO_MON 30 FM40_NFLT
1
PULLl MON
2
PULLO.FLT 32 FM80_NFLT
3
PULLl FLT
4
SYNCO Hres FLT
5
SYNCl Hres FLT
6
SYNCO Lies FLT
7
SYNCl Lres.FLT
8
PINDISO FLT
9
PINDIS1_FLT 39
10
SLFTSTO FLT
11
SLFTSTl FLT
12
VccON FLT 42 PULLO ACT TSTON
13
GndON FLT
14
PULLPOS FREQ
15
TRIGQALO EQUAL
16
TRIGQALl EQUAL
17
qalo_equal 47
18
QALl EQUAL
19
TRIGO EQUAL
20
TRIGl EQUAL
21
PULLO TRIG EQUAL
22
PULLl TRIG EQUAL
23
PULLO TRIGQAL
24
FM_STAT_NFLT
25
FM STAT FLT
26
FMASK WB_TEST
27
FMASK CAL
28
35-39
10-14
mil
40-44
15-19 20-24
00000 00000 OXXll
XXX11
45-49 50-54
25-29
11100
XXXXX
55-59
29
FM40 FLT
FM80 FLT
31
33
FM120 FLT
34
FM120 NFLT
FM160_FLT
35
36
FM160 NFLT
37 FM200.FLT
FM200_NFLT
38
FM240 FLT
40 FM240 NFLT
41
ACT DIS CLR
PULLl ACT TSTON
43
44
PULLO ACT ACTSTR
45 PULLl ACT ACTSTR
46
FREQ_BIAS SHORT
FREQ_BIAS_LONG
48 KEYBOARD OPEN
49 TEST_CYCLE
50 UART.TEST
DGATE TEST
51
52
PULLO.XTRIG
53 PULLl XTRIG
54
PULL_XEVENT
SHAD.INTT
55
3-2
FLUKE 900 SERVICE MANUAL
Tests 0,47 and SO are not automatically run during the poweran selftest, but can be nin by
themselves explicitly. This is also the case for a group of tests known as "engineering" or
"extended" tests which are designated Exx as follows:
Seiftest
E60
E61
E62
E63
E64 SHAD ADDR
E70
E71
E74 DISP CHAR SET
E75
E76
E77
E78
E79
E80
2 Flag
Flags may ^pear on lines 3 and 4 of the general results screen. A 0 means "OK" and a 1
means "fault". At the present time, only the first row is used.
WALK SIZELEDS
TEST MEMORY
WALK MONLEDS
UPDATE_VCC_UM
KEY CLOSURE
DISP RAM
CART_SLFT
TEST C ENG
ACT_CROSS
TRG CROSS
FRQ_CROSS
FLT_CROSS
Results
BYTEO
I
00000000
00000000
BYTEl BYTE2
I I
00000000 00000000
00000000 00000000
BYTE3
I
00000000
00000000
11111111
BIT: 76543210
BYTEO: Indicates DRAM chip which failed memory test
B7: U86
B6: U82
B5: U87
B4: U83
B3: U88
B2:U84
Bl: U89
BO: U85
3-3
Seiftest
FLUKE 900 SERVICE MANUAL
BYTEl: Indicates shift register bank which failed
B7: INTERFACE BUFFER OB U1,U2,U3,U4)
B6: DELAYED GATE
B5: SELFTEST (HSB U38,U76,U115,U150)
B4: FMASK (HSB U72)
B3: TRIGGER QUALIFIER (HSB U57,U87,U142,U162)
B2: TRIGGER DATA (HSB U66,U91,U140,U163)
BLPIN DISABLE (HSB U41,U80,U119,U154)
BO: SYNC (HSB U46,U82,U121,U156)
BYTE2: General
B7; NVRAM bad
B6: NVRAM checksum error, rewritten with default data
B5: Not used
B4: Not used
B3: ROM bad (U77)
B2: ROM bad (U76)
Bl: ROM bad (U75)
BO: ROM bad (U74)
BYTE3: General
B7,6,5,4: Not used
B3: FMASK calibration error
B2: Threshold calibration error
Bl: FLTS line not readable
BO: Threshold setting error
3-4
FLUKE 900 SERVICE MANUAL Selftest
3.1.3 Chip Size LED Error Codes
If self test fails, on rare occasions, the chip size LEDs may light to indicate an error. In the list
below, the 8 LEDs are shown with a 0 for unlighted and a 1 for lighted.
00000001: KEYBOARD CIO PortA. CPU cannot communicate.
00000010: KEYBOARD CIO PortB
00000011: TIME QO PortA
00000100: TIME CIO PortB
00000101: FREQ CIO PortA
00000110: FREQ CIO PortB
00000111: Display not ready
00001000: ROM checksum error
00001001: SRAM error
00001010: Stack underflow
00001011: Unimplemented interrupt occurred
00001100: Invalid intermpt vector
00001101: Not used
00001110: Incorrect peripheral serviced
00001111: UART transmit error
00010000: UART other errors ( special receive conditions)
00010001: UART parity error
00010010: DRAM error
00010011 : Overlay error
00010100: Not used
00010101: MAP CIO PortA
00010110: MAP CIO PortB
00010111 : Display memory error
3-5
Seiftest
FLUKE 900 SERVICE MANUAL
3.2 Running and Reading Individual Selftests
The individual selftest results indicate which specific lines or channels are failing. A full printout
of all failing individual results may be printed out as explained in Section 1.2. Altemativdy, a
single individual result may be viewed on the display by pressing the following keys after the
general poweron seUtest fails: ED(debug) ©(display) "test #" ien^j. The individual result then
appears as £010* bytes with a 1 indicating a problem.
BYTEO
BYTEl
I
00000000 00000000
BIT: 76543210 76543210
BYTEO
b7:X
b6:X
b5:X
b4: EXT LEAD
b3: PIN 1
b2: PIN 28
bl: PIN 2
bO: PIN 27
Refer to the individual descriptions of Section 3.3 for any bit assignments that may differ fixm
those generaEy used above. In particular, bits 5,6,7 of BYTE 0, which are not used for most tests,
may have a meaning which is noted for a specific test
BYTEl
b7: PIN 3
b6: PIN 26
b5: PIN 4
b4: PIN 25
b3: PEST 5
b2: PEST 24
bl:PESr 6
bO: PIN 23
BYTE2 BYTE3
I I
00000000 00000000
76543210 76543210
BYTE2
b7: PEST 7
b6: PEST 22
b5: PESf 8
b4: PIN 21
b3: PEST 9
b2: PTN 20
bl: PEST 10
bO: PIN 19
BYTE3
b7:PIN 11
b6: PIN 18
b5: PIN 12
b4: PB4 17
b3: PEST 13
b2: PEST 16
bl: PIN 14
bO: Pm 15
3.3 Individual Selftest Descriptions
3-6
TEST 0 SLFT_CLIP
The SLFT_CLIP routine is used for verifying test clips. The test clip in question is inserted
into the Interface Buffer and the other end is inserted into the ZEF RD socket via the Test
Oip Verification Module. When the test is running, die size of the current test clip is
displayed. The failure information is displayed as follows (Only special bits are shown, all
others refer to tegular pin number):
BYTE 0 - B7 -
B6B5B4-
Not used
Not used
Clip size code invalid
Frequency reading invalid
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