Fairchild Semiconductor MM74HCT374MTC, MM74HCT374N, MM74HCT374SJ, MM74HCT374SJX, MM74HCT374WM Datasheet
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February 1984
Revised February 1999
MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
© 1999 Fairchild Semiconductor Corporation DS005367.prf www.fairchildsemi.com
MM74HCT373 • MM74HCT374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The MM74HCT373 octal D-type latches and
MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply
range, but are LS-TTL input and output characteristic &
pin-out compatible. The 3-STATE outputs are capable of
driving 15 LS-TTL loads. All inputs are protected from damage due to static dischar ge by internal diode s to V
CC
and
ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH
ENABLE goes LOW, data at the D inputs will be retained at
the outputs until LATCH ENABLE returns HIGH again.
When a high logic level is applied to t he OUTPUT CONTROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flo ps.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on po sitive
going transitions of the CLOC K (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go t o a high impe dance state, re gardless
of what signals are present at the other inputs and the state
of the storage elements.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to redu ce power consumption in
existing designs.
Features
■ TTL input characteristic compatible
■ Typical propagation delay: 20 ns
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum
■ Compatible with bus-oriented systems
■ Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.
Order Number Package Number Package Descriptions
MM74HCT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HCT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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MM74HCT373 • MM74HCT374
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT373
Top View
MM74HCT374
Truth Tables
MM74HCT373
H = HIGH Level
L = LOW Lev el
Q0 = Level of output before steady -s ta t e input conditions were est ablished.
Z = High Impedance
MM74HCT374
H = HIGH Level
L = LOW Level
X = Don’t Care
↑ = Transition from LOW-to-HIGH
Z = High Impedance State
Q
0
= The level of the outpu t before steady state input conditions were
established.
Output LE Data 373
Control Output
LHHH
LHLL
LLXQ
0
HXXZ
Output Clock Data Output
Control (374)
L ↑ HH
L ↑ LL
LLXQ
0
HXXZ
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MM74HCT373 • MM74HCT374
Logic Diagrams
MM74HCT373
MM74HCT374
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