Fairchild Semiconductor MM74HCT244SJ, MM74HCT244SJX, MM74HCT244WM, MM74HCT244WMX, MM74HCT244MTC Datasheet
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© 1999 Fairchild Semiconductor Corporation DS005365 www.fairchildsemi.com
February 1984
Revised July 1999
MM74HCT240 • MM74HCT244 Inverting Octal 3-STATE Buffer • Octal 3-STA TE Buffer
MM74HCT240 • MM74HCT244
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HCT240 and MM74HCT244 3-STATE buffers
utilize advanced silicon-gate CMOS technology and are
general purpose high speed inverting and non-inverting
buffers. They possess high drive current outputs which
enable high speed op eration even w hen driving l arge bus
capacitances. These circui ts achieve speeds comparable
to low power Schottky devices, while retaining the low
power consumption of CM OS. All three devices are TTL
input compatible and have a fanout of 15 LS -TTL equivalent inputs.
MM74HCT devices are in tended to interface b etween TT L
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power co nsumption in
existing designs.
The MM74HCT240 is an inverting buffer and the
MM74HCT244 is a non-invertin g buffer. Each device has
two active low enables (1G and 2G), and each enable independently controls 4 buffers.
All inputs are protected from damage due to static discharge by diodes to V
CC
and Ground.
Features
■ TTL input compatible
■ Typical propagation delay: 14 ns
■ 3-STATE outputs for connection to system buses
■ Low quiescent current: 80 µA
■ High output drive current: 6 mA (min)
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT240
Top View
MM74HCT244
Order Number Package Number Package Description
MM74HCT240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT240N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HCT244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
www.fairchildsemi.com 2
MM74HCT240 • MM74HCT244
Truth Tables
MM74HCT240 MM74HCT244
H = HIGH Level
L = LOW Level
Z = High Impedance
Logic Diagrams
MM74HCT240 MM74HCT244
1G
1A 1Y 2G 2A 2Y
LLHLLH
LHLLHL
HLZHLZ
HHZHHZ
1G 1A 1Y 2G 2A 2Y
LLLLLL
LHHLHH
HLZHLZ
HHZHHZ
3 www.fairchildsemi.com
MM74HCT240 • MM74HCT244
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ra tings are those valu es beyond w hich dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
V
CC
= 5V ±10% (unless otherwise specified)
Note 4: Measured pe r input. All other inputs at VCC or GND.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to V
CC
+1.5V
DC Output Voltage (V
OUT
) −0.5 to V
CC
+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current, per pin (I
OUT
) ±35 mA
DC V
CC
or GND Current, per pin (ICC) ±70 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Solderi ng 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)4.55.5V
DC Input or Output Voltage 0 V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) 500 ns
Symbol Parameter Conditions
TA = 25°CTA = −40 to 85°CTA = −55° to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0 2.0 2.0 V
Input Voltage
V
IL
Maximum LOW Level 0.8 0.8 0.8 V
Input Voltage
V
OH
Minimum HIGH Level V
IN-EE
= VIH or V
IL
Output Voltage |I
OUT
| = 20 µAV
CCVCC
−0.1 VCC−0.1 VCC−0.1 V
|I
OUT
| = 6.0 mA, V
CC
= 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| = 7.2 mA, V
CC
= 5.5V 5.2 4.98 4.84 4.7 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
Voltage |I
OUT
| = 20 µA 0 0.1 0.1 0.1 V
|I
OUT
| = 6.0 mA, V
CC
= 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| = 7.2 mA, V
CC
= 5.5V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input V
IN
= VCC or GND, ±0.05 ±0.5 ±1.0 µA
Current VIH or V
IL
I
OZ
Maximum 3-STATE V
OUT
= VCC or GND ±0.25 ±2.5 ±10 µA
Output Leakage
G = V
IH
Current G = V
IL
I
CC
Maximum Quiescent V
IN
= VCC or GND 4.0 40 160 µA
Supply Current I
OUT
= 0 µA
V
IN
= 2.4V or 0.5V (Note 4) 0.6 1.0 1.3 1.5 mA
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