The ML4800 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching
FETs, and results in a power supply that fully complies
with IEC1000-3-2 specification. Intended as a BiCMOS
version of the industry-standard ML4824, the ML4800
includes circuits for the implementation of leading edge,
average current, “boost” type power factor correction and
a trailing edge, pulse width modulator (PWM). It also
includes a TriFault Detect™ function to help ensure that no
unsafe conditions will result from single component failure
in the PFC. Gate-drivers with 1A capabilities minimize the
need for external driver circuits. Low power requirements
improve efficiency and reduce component costs.
An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section
also includes peak current limiting and input voltage
brownout protection. The PWM section can be operated in
current or voltage mode, at up to 250kHz, and includes an
accurate 50% duty cycle limit to prevent transformer
saturation.
FEATURES
■ Internally synchronized leading-edge PFC and trailing-
■ Reduced ripple current in storage capacitor between
PFC and PWM sections
■ Average current, continuous boost leading edge PFC
■ PWM configurable for current-mode or voltage mode
operation
■ Current fed gain modulator for improved noise immunity
■ Overvoltage and brown-out protection, UVLO, and soft
start
BLOCK DIAGRAM
VEAO
15
2
4
3
7
8
6
5
9
V
2.5V
I
AC
V
I
SENSE
RAMP 1
RAMP 2
V
SS
DC I
FB
RMS
DC
V
CC
LIMIT
VEA
-
+
25µA
MODULATOR
1.25V
V
REF
16
GAIN
1.6kΩ
1.6kΩ
1
IEAO
IEA
+
-
-
+
-
+
POWER FACTOR CORRECTOR
0.5V
+
-
+
-
OSCILLATOR
V
-
FB
2.45V
+
PULSE WIDTH MODULATOR
TRI-FAULT
DUTY CYCLE
VIN OK
LIMIT
2.75V
1.0V
-1V
PFC I
-
+
OVP
+
-
+
-
LIMIT
DC I
LIMIT
V
CC
V
CC
17V
SRQ
SRQ
SRQ
UVLO
13
7.5V
REFERENCE
Q
Q
Q
V
CC
V
PFC OUT
PWM OUT
REF
14
12
11
REV. 1.0.2 3/7/2001
ML4800
PIN CONFIGURATION
ML4800
16-Pin PDIP (P16)
16-Pin Narrow SOIC (S16N)
PIN DESCRIPTION
PINNAMEFUNCTION
1IEAOSlew rate enhanced PFC
transconductance error amplifier output
2I
AC
3I
SENSE
PFC AC line reference input to Gain
Modulator
Current sense input to the PFC Gain
Modulator
IEAO
I
AC
I
SENSE
V
RMS
V
DC
RAMP 1
RAMP 2
SS
1
2
3
4
5
6
7
8
TOP VIEW
16
VEAO
15
V
FB
14
V
REF
13
V
CC
12
PFC OUT
11
PWM OUT
10
GND
9
DC I
LIMIT
PINNAMEFUNCTION
9DC I
LIMIT
PWM cycle-by-cycle current limit
comparator input
10GNDGround
11PWM OUTPWM driver output
12PFC OUTPFC driver output
4V
RMS
PFC Gain Modulator RMS line voltage
compensation input
5SSConnection point for the PWM soft start
capacitor
6V
DC
PWM voltage feedback input
7RAMP 1Oscillator timing node; timing set
by R
TCT
8RAMP 2When in current mode, this pin
functions as the current sense input;
when in voltage mode, it is the PWM
modulation ramp input.
13V
14V
CC
REF
Positive supply
Buffered output for the internal
7.5V reference
15V
FB
PFC transconductance voltage
error amplifier input
16VEAOPFC transconductance voltage
error amplifier output
2REV. 1.0.2 3/7/2001
ABSOLUTE MAXIMUM RATINGS
ML4800
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.