Fairchild Semiconductor IRLW620A Datasheet

IRLW/I620A
BV
DSS
= 200 V
R
DS(on)
= 0.8
ID = 5 A
200
3.3
2.1 12
±
20
29
3.3
3.3
5
3.1 33
0.26
- 55 to +150
300
3.81 40
62.5
--
--
--
1
Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
150°C Operating Temperature
Lower Leakage Current: 10µA (Max.) @ V
DS
= 200V
Lower R
DS(ON)
: 0.609Ω (Typ.)
$GYDQF HG 3RZH U 026)(7
Thermal Resistance
Junction-to-Case Junction-to-Ambient Junction-to-Ambient
R
θJC
R
θ
JA
R
θ
JA
°C/W
Characteristic Max. UnitsSymbol Typ.
FEATURES
D2-PAK
1. Gate 2. Drain 3. Source
1
3
2
1
2
3
I2-PAK
*
*
When mounted on the minimum pad size recommended ( PC B Mount).
Absolute Maximum Ratings
Drain-to-Source Voltage Continuous Drain Current (T
C
=25°C)
Continuous Drain Current (T
C
=100°C)
Drain Current-Pulsed
(1)
Gate-to-Source Volta ge Single Pulsed Avalanche Energy
(2)
Avalanche Current
(1)
Repetitive Avalanche Energy
(1)
Peak Diode Recovery dv/dt
(3)
Total Power Dissipation (TA=25°C) Total Power Dissipation (T
C
=25°C) Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8
from case for 5-seconds
Characteristic Value UnitsSymbol
I
DM
V
GS
E
AS
I
AR
E
AR
dv/dt
P
D
I
D
T
J
, T
STG
T
L
A V
mJ
A
mJ
V/ns
W W
W/°C
A
°C
V
DSS
V
*
©1999 Fairchild Semiconductor Corporation
Rev. B
IRLW/I620A
200
--
1.0
--
--
--
--
--
0.18
--
--
--
--
--
55 25
8 6
24
6
10.3
2.0
4.4
--
--
2.0
100
-100 10
100
0.8
--
430
70 30 25 20 60 20 15
--
--
3.3
330
--
--
--
140
0.59
5
18
1.5
--
--
Notes;
(1) Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature (2) L=2mH, I
AS
=5A, VDD=50V, RG=27Ω, Starting TJ =25 °C
(3) I
SD
5A, di/d t ≤ 180A/µs, V
DD
BV
DSS
, Starting TJ =25 °C (4) Pulse Test : Pulse Width = 250µs, Duty Cycl e ≤ 2% (5) Essent ially Independent of Operati ng Temperature
2
1&+$11(/
32:(5 026)(7
Electrical Characteristics
(TC=25°C unless otherwise specified)
Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coeff. Gate Threshold Voltage Gate-Source Leakage , Forwar d Gate-Source Leakage , Revers e
CharacteristicSymbol
Max. UnitsTyp.Min. Test Condition
Static Drain-Source On-State Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain (
Miller ) Charge
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
BV
DSS
∆BV/∆T
J
V
GS(th)
R
DS(on)
I
GSS
I
DSS
V
V/°C
V
nA
µ
A
pF
ns
nC
--
--
--
--
--
--
--
--
--
--
--
--
--
V
GS
=0V,ID=250µA
I
D
=250µA
See Fig 7
VDS=5V,ID=250µA V
GS
=20V
V
GS
=-20V
V
DS
=200V
V
DS
=160V,TC=125°C
V
GS
=5V,ID=2.5A
(4)
VDS=40V,ID=2.5A
(4)
VDD=100V,ID=5A, R
G
=9
See Fig 13
(4) (5)
VDS=160V,VGS=5V, I
D
=5A
See Fig 6 & Fig 12
(4) (5)
Drain-to-Source Leakage Current
V
GS
=0V,VDS=25V,f =1MHz
See Fig 5
Source-Drain Diode Ratings and Characteristics
Continuous Source Current Pulsed- S o u rce Curren t
(1)
Diode Forward Voltage
(4)
Reverse Recove ry Tim e Reverse Recovery Ch arge
I
S
I
SM
V
SD
t
rr
Q
rr
CharacteristicSymbol Max. UnitsTyp.Min. Test Condition
--
--
--
--
--
A V
ns
µ
C
Integral reverse pn-diode in the MOSFET T
J
=25°C,IS=5A,VGS=0V
T
J
=25°C,IF=5A
di
F
/dt=100A/µs
(4)
IRLW/I620A
10
-1
10
0
10
1
10
-1
10
0
10
1
@ Notes :
1. 250 µs Pulse Tes t
2. TC = 25 oC
V
GS
Top : 7 .0 V 6 .0 V 5 .5 V 5 .0 V 4 .5 V 4 .0 V 3 .5 V Bot to m : 3 .0 V
I
D
, Drain Current [A]
VDS , Drain -Source Voltage [V]
0 3 6 9 12 15 18
0.0
0.5
1.0
1.5
2.0
@ Note : TJ = 25 oC
VGS = 10 V
VGS = 5 V
R
DS(on)
, [
]
Drain-So urce On-Resistance
ID , Drain Current [A]
024681012
0
2
4
6
VDS = 160 V
VDS = 100 V
VDS = 40 V
@ Notes : ID = 5 A
V
GS
, Gate-Source Voltage [V]
QG , Total Gate Charge [nC]
0246810
10
-1
10
0
10
1
25 oC
150 oC
- 55 oC
@ Note s :
1. V
GS
= 0 V
2. V
DS
= 40 V
3. 2 50
µ
s Puls e Test
I
D
, Drain Current [A]
VGS , Gate-Source Voltage [V]
0.40.60.81.01.21.41.61.8
10
-1
10
0
10
1
150 oC
25 oC
@ Notes :
1. V
GS
= 0 V
2. 250
µ
s Pulse Test
I
DR
, Reverse Drain Current [A]
VSD , Source-Drain Voltage [V]
10
0
10
1
0
100
200
300
400
500
C
iss
= Cgs+ Cgd ( Cds= shorted )
C
oss
= Cds+ C
gd
C
rss
= C
gd
@ Notes :
1. V
GS
= 0 V
2. f = 1 MHz
C
rss
C
oss
C
iss
Capacita nce [pF]
VDS , Drain -Source Voltage [V ]
3
1&+$11(/
32:(5 026)(7
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drai n-Source Voltage
Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Curr ent
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