Fairchild Semiconductor FIN1028 Datasheet

March 2001
Revised June 2003

FIN1028

3.3V LVDS 2-Bit High Speed Differential Receiver

FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver

General Description

This dual receiver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol­ogy. The receiver translates LVDS levels, with a typical dif­ferential input thre shold of 100 m V, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.

The FIN1028 can be paired with its companion dr iver, the
FIN1027, or any other LVDS driver.

Features

■ Greater than 400Mbs data rate

■ 3.3V power supply operation

■ 0.4ns maximum differential pulse skew

■ 2.5ns maximum propagation delay

■ Low power dissipation

■ Power-Off protection

■ Fail safe protection for open-circuit, shorted and

terminated conditions

■ Meets or exceeds the TIA/EIA-644 LVDS standard

■ Flow-through pinout simpli f ies PCB layout

■ 8-Lead SOIC and 8-terminal MLP packages save space

Ordering Code:

Order Number Package Number Package Description

FIN1028M
(Note 1)

FIN1028MPX
(Preliminary)

Note 1: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Pin Descriptions

Pin Name Description

, R

R

OUT1

R

, R

IN1+

R

, R

IN1−

V

CC

GND Ground

M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MLP08C 8-Terminal Molded Leadless Package (MLP) Dual, JEDEC MO-229, 2mm Square

[TAPE and REEL]

Connection Diagrams

Pin Assignment for SOIC

OUT2
IN2+
IN2−

LVTTL Data Outputs
Non-inverting LVDS Inputs
Inverting LVDS Inputs
Power Supply

Function Table

Input Outputs

R

IN+

LH L

HL H

Fail Safe Condition H

H = HIGH Logic Le v el
L = LOW Logic Level
Fail Safe = Open, Shorted, Terminated

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R

IN+

R

OUT

(Top View)

Terminal Assignmen ts for MLP

(Top Through View)

Absolute Maximum Ratings(Note 2) Recommended Operating

Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (R

FIN1028

DC Output Voltage (R
DC Output Current (I
Storage Temperature Range (T
Max Junction Temperature (T
Lead Temperature (T

, R

INx+

) −0.5V to +4.7V

INx−

) −0.5V to +6V

OUTx

)16 mA

O

)

L

) −65°C to +150°C

STG

)150°C

J

(Soldering, 10 seconds) 260
ESD (Human Body Model)
ESD (Machine Model)

≥ 6500V

≥ 300V

Conditions

Supply Voltage (V
Input Voltage (V
Magnitude of Differential Voltage

|) 100 mV to V

(|V

ID

Common-mode Input Voltage

(V

) 0.05V to 2.35V

°C

IC

Operating Temperature (T

Note 2: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperatur e and output/input loading va riables. Fairchild
does not recommend operation of circu it s o ut s ide databook specific ation.

) 3.0V to 3.6V

CC

) 0 to V

IN

) −40°C to +85°C

A

DC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Symbol Parameter Test Conditions

V

TH

V

TL

I

IN

I

I(OFF)

V

OH

V

OL

V

IK

I

CC

C

IN

C

OUT

Note 3: All typical values are at TA = 25°C and with VCC = 3.3V .

Differential Input Threshold HIGH See Figure 1 and Table 1 100 mV
Differential Input Threshold LOW See Figure 1 and Table 1 −100 mV
Input Current VIN = 0V or V
Power-OFF Input Current VCC = 0V, VIN = 0V or 3.6V ±20 µA
Output HIGH Voltage IOH = −100 µAV

Output LOW Voltage IOH = 100 µA0.2

Input Clamp Voltage IIK = −18 mA −1.5 V
Power Supply Current (R

Input Capacitance 4pF
Output Capacitance 6pF

IOH = −8 mA 2.4

I

OL

(R

CC

= 8 mA 0.5

= 1V and R

IN+

= 1.4V and R

IN+

= 1.4V) or

IN−

= 1V)

IN−

Min Typ Max

(Note 3)

−0.2

CC

CC

CC

Units

±20 µA

V

V

9mA

AC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Symbol Parameter Test Conditions

t

PLH

t

PHL

t

TLH

t

THL

t

SK(P)

t

SK(LH)

t

SK(HL)

t

SK(PP)

Note 4: All typical values are at TA = 25°C and with VCC = 3.3V .
Note 5: t

tion.
Note 6: t
(either LOW-to-HI GH or HIGH-to-LOW) w hen both devices operate with the same supply voltage, same te m perature, and have id ent ic al test circuits.

Differential Propagation Delay
LOW-to-HIGH
Differential Propagation Delay
HIGH-to-LOW
Output Rise Time (20% to 80%) |VID| = 400 mV, CL = 10 pF, 0.5 ns
Output Fall Time (80% to 20%) See Figure 1 and Figure 2 0.5 ns
Pulse Skew |t

, Channel-to-Channel Skew

(Note 5)
Part-to-Part Skew (Note 6) 1.0 ns

, t

SK(LH)

SK(HL)

is the magnitude of t he difference in propagation delay tim es between any spec ified terminals of t w o devices switching in the sam e di re c ti on

SK(PP)

- t

| 0.4 ns

PLH

PHL

is the skew between speci fie d outputs of a s ingle device w hen the outputs have identical loads and are switching in t he same direc-

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Min Typ Max

(Note 4)

0.9 2.5 ns

0.9 2.5 ns

0.3 ns

Units

Note A: All input pulses have frequ ency = 10 MHz, tR or tF = 1 ns

includes all probe and fixture capacitances

Note B: C

L

FIGURE 1. Differential Driver Propagation Delay and Transition Time Test Circuit

TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages

Applied Voltages (V)

V

IA

1.25 1.15 100 1.2

1.15 1.25 −100 1.2

2.4 2.3 100 2.35

2.3 2.4 −100 2.35

0.1 0 100 0.05

00.1−100 0.05

1.5 0.9 600 1.2

0.9 1.5 −600 1.2

2.4 1.8 600 2.1

1.8 2.4 −600 2.1

0.6 0 600 0.3

00.6−600 0.3

V

FIN1028

Resulting Differential

Input Voltage (mV)

IB

V

ID

Resulting Common Mode

Input Voltage (V)

V

IC

FIGURE 2. AC Waveforms

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