Fairchild Semiconductor FIN1019 Datasheet

April 2001
Revised September 2001

FIN1019

3.3V LVDS High Speed Differential Driver/Receiver

FIN1019 3.3V LVDS High Speed Differential Driver/Receiver

General Description

This driver and receiver pai r are designed for high speed
interconnects utilizing Low Voltage Differential Signaling
(LVDS) technology. The driver translates LVTTL signals to
LVDS levels with a typical differential output swing of
350mV and the receiver transl ates LVDS signals, with a
typical differential input threshold of 100mV, into LVTTL
levels. LVDS technology provides low EMI at ultra low
power dissipation even at high freq uencies. Thi s device is
ideal for high speed clock or data transfer.

Features

■ Greater than 400Mbs data rate

■ 3.3V power supply operation

■ 0.5ns maximum differential pulse skew

■ 2.5ns maximum propagation delay

■ Low power dissipation

■ Power-Off protection

■ 100mV receiver input sensitivity

■ Fail safe protection ope n-circu it, shorted and ter minated

conditions

■ Meets or exceeds the TIA/EIA-644 LVDS standard

■ Flow-through pinout simpli f ies PCB layout

■ 14-Lead SOIC and TSSOP packages save space

Ordering Code:

Order Number Package Number Package Description

FIN1019M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1019MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.

Function Table

Inputs Outputs

R

IN+

LHL L
HLL H
XXH Z

Fail Safe Condition L H

Open

−Circuit or Z H L H

H = HIGH Logic Le v el L = LOW Logic Level X = Don’t Care
Z = High Impedance Fail Safe = Open, Shorted, Terminated

R

IN−

D

IN

LHLH
HHHL
XLZZ

RE

DE D

R

OUT

OUT+DOUT−

Connection Diagram

Pin Descriptions

Pin Name Description

D

D

OUT+

D

OUT−

DE Driver Enable (LVTTL, Active HIGH)
R
R

R

OUT

RE
V

GND Ground

NC No Connect

LVTTL Data Input

IN

Non-inverting LVDS Output
Inverting LVDS Output

Non-Inverting LVDS Input

IN+

Inverting LVDS Input

IN−

LVTTL Receiver Output
Receiver Enable (LVTTL, Active LOW)

Power Supply

CC

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Absolute Maximum Ratings(Note 1) Recommended Operating

Supply Voltage (V
LVTTL DC Input Voltage (D

FIN1019

LVDS DC Input Voltage (R
LVTTL DC Output Voltage (R
LVDS DC Output Voltage (D
LVDS Driver Short Circuit Current (I
LVTTL DC Output Current (I
Storage Temperature Range (T
Max Junction Temperature (T
Lead Temperature (T

) −0.5V to +4.6V

CC

, DE, RE) −0.5V to +6V

IN

, R

) −0.5V to 4.7V

IN+

IN−

) −0.5V to +6V

OUT

, D

OUT+

) 16 mA

O

)150°C

J

)

L

) −0.5V to 4.7V

OUT−

) Continuous

OSD

) −65°C to +150°C

STG

(Soldering, 10 seconds) 260
ESD (Human Body Model)
ESD (Machine Model)

≥ 6500V

≥ 300V

Conditions

Supply Voltage (V
Input Voltage (V
Magnitude of Differential Voltage

|) 100 mV to V

(|V

ID

Common-Mode Input Voltage (VIC) 0.05V to 2.35V
Operating Temperature (T

Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be

°C

met, without exception, to ensure that the system design is reliable over its
power supply, temperatur e and output/input loading va riables. Fairchild
does not recommend operation of circu it s o ut s ide databook specific ation.

) 3.0V to 3.6V

CC

) 0 to V

IN

) −40°C to +85°C

A

DC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Symbol Parameter Test Conditions

LVDS Differential Driver Characteristics

V

OD

∆V

V

OS

∆V

I

OZD

I

OFF

I

OS

LVTTL Driver Characterist ics

V

OH

V

OL

I

OZ

LVDS Receiver Characteristics

V

TH

V

TL

I

IN

I

I(OFF)

LVTTL Driver and Control Signals Characteristics

V

IH

V

IL

I

IN

I

I(OFF)

V

IK

Output Differential Voltage 250 350 450 mV
VOD Magnitude Change from

OD

Differential LOW-to-HIGH RL = 100Ω, See Figure 1
Offset Voltage 1.125 1.25 1.375 V
Offset Magnitude Change from

OS

Differential LOW-to-HIGH
Disabled Output Leakage Current V
Power Off Output Current VCC = 0V, V
Short Circuit Output Current V

Output HIGH Voltage IOH = −100 µA, RE = 0V,

Output LOW Voltage IOL = 100 µA, RE = 0V, VID = −400 mV

Disabled Output Leakage Current V

Differential Input Threshold HIGH See Figure 6 and Table 1 100 mV
Differential Input Threshold LOW See Figure 6 and Table 1 −100 mV
Input Current VIN = 0V or V
Power-OFF Input Current VCC = 0V, VIN = 0V or 3.6V ±20 µA

Input HIGH Voltage 2.0 V
Input LOW Voltage GND 0.8 V
Input Current VIN = 0V or V
Power-OFF Input Current VCC = 0V, VIN = 0V or 3.6V ±20 µA
Input Clamp Voltage IIK = −18 mA −1.5 V

= VCC or GND, DE = 0V ±20 µA

OUT

OUT

VOD = 0V, DE = V

See Figure 6 and Table 1
IOH = −8 mA, RE = 0V, VID = 400 mV

VID = 400 mV, VIC = 1.2V, see Figure 6

See Figure 6 and Table 1
IOL = −8 mA, RE = 0V, VID = −400 mV

VID = −400 mV, VIC = 1.2V, see Figure 6

OUT

= 0V or 3.6V ±20 µA

OUT

= 0V, DE = V

= VCC or GND, RE = V

CC

CC

CC

CC

CC

Min Typ Max

(Note 2)

VCC −0.2

2.4

Units

25 mV

25 mV

−8
±8

0.2

0.5

±20 µA

±20 µA

±20 µA

mA

CC

CC

CC

V

V

V

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DC Electrical Characteristics (Continued)

Device Characteristics

I

CC

Power Supply Current Driver Enabled, Driver Load: RL = 100 Ω

Receiver Disabled, No Receiver Load

12.5 mA

Driver Enabled, Driver Load: RL = 100 Ω,

or (R

= 1.4V and R

IN+

= 1V and R

IN+

= 1V)

OUT−

IN−

= 1.4V)

12.5 mAReceiver Enabled, (R

Driver Disabled, Receiver Enabled,

= 1V and R

IN+

(R

= 1.4V and R

IN+

= 1.4V) or

IN−

IN−

= 1V)

7.0 mA(R

Driver Disabled, Receiver Disabled 7.0 mA

C

IN

C

OUT

Note 2: All typical values are at TA = 25°C and with VCC = 3.3V.

Input Capacitance Any LVTTL or LVDS Input 4 pF
Output Capacitance Any LVTTL or LVDS Output 6 pF

AC Electrical Characteristics

Over supply voltage and operating temperature ranges, unless otherwise specified

Symbol Parameter Test Conditions

Driver Timing Characteristics

t

PLHD

Differential Propagation Delay
LOW-to-HIGH

t

PHLD

Differential Propagation Delay
HIGH-to-LOW RL = 100 Ω, CL = 10 pF,

t

TLHD

t

THLD

t

SK(P)

t

SK(PP)

t

ZHD

t

ZLD

t

HZD

t

LZD

Differential Output Rise Time (20% to 80%) See Figure 2 and Figure 3 0.4 1.0 ns
Differential Output Fall Time (80% to 20%) 0.4 1.0 ns
Pulse Skew |t

- t

| 0.5 ns

PLH

PHL

Part-to-Part Skew (Note 4) 1.0 ns
Differential Output Enable Time from Z to HIGH RL = 100Ω, CL = 10 pF, 5.0 ns
Differential Output Enable Time from Z to LOW See Figure 4 and Figure 5 5.0 ns
Differential Output Disable Ti me fro m HIGH to Z 5.0 ns
Differential Output Disable Time from LOW to Z 5.0 ns

Receiver Timing Characteristics

t

PLH

t

PHL

t

TLH

t

THL

t

SK(P)

t

SK(PP)

t

ZH

t

ZL

t

HZ

t

LZ

Note 3: All typical values are at TA = 25°C and with VCC = 5V.
Note 4: t

(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.

Propagation Delay LOW-to-HIGH 0.9 2.5 ns
Propagation Delay HIGH-to-LOW 0.9 2.5 ns
Output Rise time (20% to 80%) |VID| = 400 mV, CL = 10 pF, 0.5 ns
Output Fall time (80% to 20%) See Figure 6 and Figure 7 0.5 ns
Pulse Skew | t

- t

| 0.5 ns

PLH

PHL

Part-to-Part Skew (Note 4) 1.0 ns
LVTTL Output Enable Time from Z to HIGH 5.0 ns
LVTTL Output Enable Time from Z to LOW RL = 500 Ω, CL = 10 pF, 5.0 ns
LVTTL Output Disable Time from HIGH to Z See Figure 8 5.0 ns
LVTTL Output Disable Time from LOW to Z 5.0 ns

is the magnitude of t he difference in propagation delay tim es between any sp ec if ied terminals of two devices switching in the same direction

SK(PP)

Min Typ Max

(Note 3)

0.5 1.5 ns

0.5 1.5 ns

FIN1019

Units

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FIN1019

FIGURE 1. Differential Driver DC Test Circuit

Note A: Input pulses have frequency = 10 MHz, tR or tF = 2 ns
Note B: C

includes all probe and fixture capacitances

L

FIGURE 2. Differential Driver Propagation Delay and

Transition Time Test Circuit

FIGURE 3. AC Waveforms for Differential Driver

FIGURE 5. Enable and Disable AC Waveforms

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Note B: Input pulses have the fre quency = 10 MHz , tR or tF = 2 ns
Note A: C

includes all probe and fixture capacitances

L

FIGURE 4. Differential Driver Enable and

Disable Test Circuit

Note A: Input pulses have frequ ency = 10 MHz, tR or tF = 1ns

includes all probe and fixture capacitance

Note B: C

L

FIGURE 6. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit

TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages

Applied Voltages (V) Resulting Differential Resulting Common Mode

V

IA

V

IB

1.25 1.15 100 1.2

1.15 1.25 −100 1.2

2.4 2.3 100 2.35

2.3 2.4 −100 2.35

0.1 0 100 0.05

00.1 −100 0.05

1.5 0.9 600 1.2

0.9 1.5 −600 1.2

2.4 1.8 600 2.1

1.8 2.4 −600 2.1

0.6 0 600 0.3

00.6 −600 0.3

Input Voltage (mV) Input Voltage (V)

V

ID

V

IC

FIN1019

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