Fairchild Semiconductor FIN1018 Datasheet
March 2001
Revised April 2002
FIN1018
3.3V LVDS 1-Bit High Speed Differential Receiver
FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver
General Description
This single receiver is de signed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS)
technology. The receiver translates LVDS levels, with a typical differential input th reshold of 1 00 mV, to LVTTL signal
levels. LVDS provides low EMI at ultra low power dissipation even at high frequen cies. This device is ideal for high
speed transfer of clock or data.
The FIN1018 can be paired with its companion dr iver, the
FIN1017, or with any other LVDS driver.
Features
■ Greater than 400Mbs data rate
■ 3.3V power supply operation
■ 0.4ns maximum pulse skew
■ 2.5ns maximum propagation delay
■ Low power dissipation
■ Power-Off protection
■ Fail safe protection for ope n-circuit, shorted and termi-
nated conditions
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ Flow-through pinout simpli f ies PCB layout
■ 8-Lead SOIC and US-8 packages save space
Ordering Code:
Order Number Package Number Package Description
FIN1018M M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1018MX M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1018K8X MAB08A 8-Lead US8, JEDEC MO-187, Variation CA 3. 1mm Wide
Pin Descriptions
Pin Name Description
R
OUT
R
IN+
R
IN−
V
CC
GND Ground
NC No Connect
LVTTL Data Output
Non-inverting Driver Input
Inverting Driver Input
Power Supply
[TUBE]
[TAPE and REEL]
[TAPE and REEL]
Connection Diagrams
8-Lead SOIC
Function Table
Input Outputs
R
IN+
LH L
HL H
Fail Safe Condition H
H = HIGH Logic Le v el
L = LOW Logic Level
Fail Safe = Open, Shorted, Terminated
© 2002 Fairchild Semiconductor Corporation DS500502 www.fairchildsemi.com
R
IN−
R
OUT
Pin Assignment for US-8 Package
TOP VIEW
Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (R
FIN1018
DC Output Voltage (D
DC Output Current (I
Storage Temperature Range (T
Max Junction Temperature (T
Lead Temperature (T
, R
) −0.5V to +4.7V
IN+
IN−
) −0.5V to +6V
OUT
)16 mA
O
)
L
) −65°C to +150°C
STG
)150°C
J
(Soldering, 10 seconds) 260
ESD (Human Body Model)
ESD (Bus Pins R
to GND) ≥ 9500V
IN−/RIN+
ESD (Machine Model)
≥ 6500V
≥ 300V
Conditions
Supply Voltage (V
Input Voltage (V
Magnitude of Differential Voltage
|) 100mV to V
(|V
ID
Common-mode Input Voltage (VIC) 0.05V to 2.35V
Operating Temperature (T
°C
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperatur e and output/input loading va riables. Fairchild
does not recommend operation of circu it s o ut s ide databook specific ation.
) 3.0V to 3.6V
CC
) 0 to V
IN
) −40°C to +85°C
A
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol Parameter Test Conditions
V
TH
V
TL
I
IN
I
I(OFF)
V
OH
V
OL
V
IK
I
CC
C
IN
C
OUT
Note 2: All typical values are at TA = 25°C and with VCC = 3.3V .
Differential Input Threshold HIGH See Figure 1 and Table 1 100 mV
Differential Input Threshold LOW See Figure 1 and Table 1 −100 mV
Input Current VIN = 0V or V
Power-OFF Input Current VCC = 0V, VIN = 0V or 3.6V ±20 µA
Output HIGH Voltage IOH = −100 µAV
IOH = −8 mA 2.4 V
Output LOW Voltage IOH = 100 µA0.2V
IOL = 8 mA 0.5 V
Input Clamp Voltage IIK = −18 mA −1.5 V
Power Supply Current Inputs Open, (R
or (R
Input Capacitance 4pF
Output Capacitance 6pF
= 1.4V and R
IN+
CC
IN+
= 1V and R
IN−
= 1V)
IN−
= 1.4V),
Min Typ Max
(Note 2)
−0.2 V
CC
CC
CC
Units
±20 µA
7mA
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol Parameter Test Conditions
t
PLH
t
PHL
t
TLH
t
THL
t
SK(P)
t
SK(PP)
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V .
Note 4: t
(either LOW-to-HI GH or HIGH-to-LOW) w hen both devices operate with the same supply voltage, same te m perature, and have id ent ic al test circuits.
Propagation Delay LOW-to-HIGH 0.9 2.5 ns
Propagation Delay HIGH-to-LOW 0.9 2.5 ns
Output Rise Time (20% to 80%) |VID| = 400 mV, CL = 10 pF 0.5 ns
Output Fall Time (80% to 20%) See Figure 1 and Figure 2 0.5 ns
Pulse Skew |t
Part-to-Part Skew (Note 4) 1.0 ns
is the magnitude of t he difference in propagation delay tim es between any specified terminals of t w o devices switching in the sam e di re c ti on
SK(PP)
- t
| 0.4 ns
PLH
PHL
www.fairchildsemi.com 2
Min Typ Max
(Note 3)
Units
Note A: All input pulses have frequ ency = 10MHz, tR or tF = 1ns
Note B: C
includes all probe and fixture capacitances
L
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
V
IA
1.25 1.15 100 1.2
1.15 1.25 −100 1.2
2.4 2.3 100 2.35
2.3 2.4 −100 2.35
0.1 0 100 0.05
00.1−100 0.05
1.5 0.9 600 1.2
0.9 1.5 −600 1.2
2.4 1.8 600 2.1
1.8 2.4 −600 2.1
0.6 0 600 0.3
00.6−600 0.3
V
IB
Resulting Differential
Input Voltage (mV)
V
ID
Resulting Common Mode
Input Voltage (V)
V
IC
FIN1018
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
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