Fairchild Semiconductor FIN1002 Datasheet
FIN1002
LVDS 1-Bit High Speed Differential Receiver
FIN1002 LVDS 1-Bit High Speed Differential Receiver
February 2002
Revised February 2002
General Description
This single receiver is de signed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS)
technology. The receiver translates LVDS levels, with a typical differential input th reshold of 1 00 mV, to LVTTL signal
levels. LVDS provides low EMI at ultra low power dissipation even at high frequen cies. This device is ideal for high
speed transfer of clock or data.
The FIN1002 can be paired with its companion dr iver, the
FIN1001, or with any other LVDS driver.
Features
■ Greater than 400Mbs data rate
■ 3.3V power supply operation
■ 0.4ns maximum pulse skew
■ 2.5ns maximum propagation delay
■ Bus pin ESD (HBM) protection exceeds 10kV
■ Power-Off over voltage tolerant input and output
■ Fail safe protection for open-circuit and non-driven,
shorted or terminated conditions
■ High impedance output at V
■ Meets or exceeds the TIA/EIA-644 LVDS standard
■ 5-Lead SOT23 package saves space
CC
< 1.5V
Ordering Code:
Order Number Package Number Package Description
FIN1002M5 MA05B 5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel]
FIN1002M5X MA05B 5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel]
Pin Descriptions
Pin Name Description
R
OUT
R
IN+
R
IN−
V
CC
GND Ground
NC No Connect
LVTTL Data Output
Non-inverting Driver Input
Inverting Driver Input
Power Supply
Connection Diagram
Pin Assignment for SOT package
Function Table
Input Outputs
R
IN+
LH L
HL H
Fail Safe Condition H
H = HIGH Logic Le v el
L = LOW Logic Level
Fail Safe = Open, Shorted, Terminated
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R
IN−
R
OUT
Top View
Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (R
FIN1002
DC Output Voltage (D
DC Output Current (I
Storage Temperature Range (T
Max Junction Temperature (T
Lead Temperature (T
, R
) −0.5V to +4.6V
IN+
IN−
) −0.5V to +6V
OUT
)16 mA
O
)
L
) −65°C to +150°C
STG
)150°C
J
(Soldering, 10 seconds) 260
Conditions
Supply Voltage (V
Input Voltage (V
Magnitude of Differential
Voltage (|V
Common-mode Input
Voltage (V
°C
Operating Temperature (T
ESD (Human B ody Model)
LVDS pins to GND 10kV
ESD (Machine Model) 400V
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperatur e and output/input loading va riables. Fairchild
does not recommend operation of circu it s o ut s ide databook specific ation.
) 3.0V to 3.6V
CC
) 0 to V
IN
|) 100mV to V
ID
)(0V + |VID| /2) to (2.4 − |VID|/2)
IC
) −40°C to +85°C
A
All Pins 8kV
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol Parameter Test Conditions
V
TH
V
TL
I
IN
I
I(OFF)
V
OH
V
OL
V
IK
I
CC
C
IN
C
OUT
Note 2: All typical values are at TA = 25°C and with VCC = 3.3V .
Differential Input Threshold HIGH See Figure 1; VIC = +0.05V, 1.2V, or 2.35V 100 mV
Differential Input Threshold LOW See Figure 1; VIC = +0.05V, 1.2V, or 2.35V −100 mV
Input Current VIN = 0V or V
Power-OFF Input Current VCC = 0V, VIN = 0V or 3.6V ±20 µA
Output HIGH Voltage IOH = −100 µAV
I
Output LOW Voltage IOH = 100 µA0.00.2
Input Clamp Voltage IIK = −18 mA −1.5 0.8 V
Power Supply Current (R
Input Capacitance VCC = 3.3V 2.3 pF
Output Capacitance VCC = 0V 2.8 pF
OH
I
OL
(R
CC
= −8 mA 2.4 3.1
= 8 mA 0.16 0.5
= 1V and R
IN+
= 1.4V and R
IN+
= 1.4V), or
IN−
= 1V)
IN−
Min Typ Max
(Note 2)
− 0.2 3.3
CC
CC
CC
Units
±20 µA
V
V
47mA
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol Parameter Test Conditions
t
PLH
t
PHL
t
TLH
t
THL
t
SK(P)
t
SK(PP)
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V .
Note 4: t
(either LOW-to-HI GH or HIGH-to-LOW) w hen both devices operate with the same supply voltage, same te m perature, and have id ent ic al test circuits.
Propagation Delay LOW-to-HIGH 0.9 1.5 2.5 ns
Propagation Delay HIGH-to-LOW 0.9 1.5 2.5 ns
Output Rise Time (20% to 80%) |VID| = 400 mV, CL = 10 pF 0.6 ns
Output Fall Time (80% to 20%) See Figure 1 and Figure 2 0.5 ns
Pulse Skew |t
Part-to-Part Skew (Note 4) 1.0 ns
is the magnitude of t he difference in propagation delay tim es between any spec ified terminals of t w o devices switching in the sam e di re c ti on
SK(PP)
- t
| 0.02 0.4 ns
PLH
PHL
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Min Typ Max
(Note 3)
Units
Note A: All input pulses have frequ ency = 10MHz, tR or tF = 1ns
Note B: C
includes all probe and fixture capacitances
L
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
FIN1002
FIGURE 2. LVDS Input to LVTTL Output AC Waveforms
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