Fairchild Semiconductor FDW258P Datasheet

January 2002

FDW258P

P-Channel 1.8V Specified PowerTrench



MOSFET

FDW258P

General Description

This P-Channel 1.8V specified MOSFET is a rugged
gate version of Fairchild Semiconductor’s advanced
PowerTrench process. It has been optimized for power
management applications with a wide range of gate

Features

• –9 A, –12 V. R

R

R

= 11 mΩ @ VGS = –4.5 V

DS(ON)

= 14 mΩ @ VGS = –2.5 V

DS(ON)

= 20 mΩ @ VGS = –1.8 V

DS(ON)

drive voltage (1.8V – 8V).

• Rds ratings for use with 1.8 V logic

Applications

• Load switch

• Motor drive

• DC/DC conversion

• Power management

• Low gate charge

• High performance trench technology for extremely

DS(ON)

low R

• Low profile TSSOP-8 package

D

S

S

D

TSSOP-8

Pin 1

G

S

S

D

Absolute Maximum Ratings T

o

=25

C unless otherwise noted

A

5

6

7

8

4

3

2

1

Symbol Parameter Ratings Units

V

Drain-Source Voltage –12 V

DSS

V

Gate-Source Voltage

GSS

±8

ID Drain Current – Continuous (Note 1) –9 A

– Pulsed –50

PD Power Dissipation (Note 1a) 1.3 W

TJ, T

STG

Operating and Storage Junction Temperature Range –55 to +150

(Note 1b)

0.6

V

°C

Thermal Characteristics

R

θJA

Thermal Resistance, Junction-to-Ambient

(Note 1a) 87

(Note 1b)

114

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity

258P FDW258P 13’’ 12mm 3000 units

2002 Fairchild Sem iconductor Corporation

°C/W

FDW258P Rev D (W)

FDW258P

Electrical Characteristics T

= 25°C unless otherwise noted

A

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

BV

Drain–Source Breakdown Voltage

DSS

∆BVDSS
∆T

I

Zero Gate Voltage Drain Current VDS = –10 V, VGS = 0 V –1

DSS

I

GSSF

I

GSSR

Breakdown Voltage Temperature
Coefficient

J

Gate–Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA

Gate–Body Leakage, Reverse VGS = –8 V. VDS = 0 V –100 nA

V

= 0 V, ID = –250 µA

GS

= –250 µA, Referenced to 25°C

I

D

–12 V

–3

mV/°C

µA

On Characteristics (Note 2)

V

Gate Threshold Voltage

GS(th)

∆VGS(th)
∆TJ

R

DS(on)

Gate Threshold Voltage
Temperature Coefficient

Static Drain–Source

On–Resistance

I

On–State Drain Current VGS = –4.5 V, VDS = –5 V –50 A

D(on)

V

= VGS, ID = –250 µA

DS

= –250 µA, Referenced to 25°C

I

D

VGS = –4.5 V, ID = –9 A
V

= –2.5 V, ID = –8 A

GS

= –1.8 V, ID = –6.5 A

V

GS

=–4.5 V, ID = –9A, TJ=125°

V

GS

–0.4 –0.6 –1.5 V

3

8.6

10.6

13.8

11.2

11
14
20
14

mV/°C

mΩ

gFS Forward Transconductance VDS = –5 V, ID = –9 A 50 S

Dynamic Characteristics

C

Input Capacitance 5049 pF

iss

C

Output Capacitance 1943 pF

oss

C

Reverse Transfer Capacitance

rss

= –5 V, V

V

DS

f = 1.0 MHz

= 0 V,

GS

1226 pF

Switching Characteristics (Note 2)

t

Turn–On Delay Time 17 31 ns

d(on)

tr Turn–On Rise Time 23 37 ns

t

Turn–Off Delay Time 201 322 ns

d(off)

tf Turn–Off Fall Time

Qg Total Gate Charge 61 73 nC

Qgs Gate–Source Charge 8 nC

Qgd Gate–Drain Charge

= –6 V, ID = –1 A,

V

DD

= –4.5 V, R

V

GS

= –6 V, ID = –9 A,

V

DS

V

= –4.5 V

GS

GEN

= 6 Ω

148 237 ns

16 nC

Drain–Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain–Source Diode Forward Current –1.25 A

VSD Drain–Source Diode Forward

VGS = 0 V, IS = –1.25 A (Note 2) –0.6 –1.2 V

Voltage

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of

θJA

the drain pins. R

is guaranteed by design while R

θJC

is determined by the user's board design.

θCA

a) 87°C/W when

mounted on a 1in2 pad
of 2 oz copper.

b) 114°C/W when mounted

on a minimum pad of 2 oz
copper.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%

FDW258P Rev . D (W)