Fairchild Semiconductor FDW2508P Datasheet

December 2001
FDW2508P
Dual P-Channel 1.8 V Specified PowerTrench

FDW2508P
General Description
This P-Channel –1.8V specified MOSFET uses Fairchild’s advanced low voltage PowerTrench process. It has been optimized for battery power management applications.
Applications
Power management
Load switch
Battery protection
Features
–6 A, –12 V. R
R
R
Low gate charge(26nC typical)
High performance trench technology for extremely
DS(ON)
low R
Low profile TSSOP-8 package
= 18 m @ VGS = –4.5 V
DS(ON)
= 22 m @ VGS = –2.5 V
DS(ON)
= 30 m @ VGS = –1.8 V
DS(ON)
G
2
S
2
S
2
D
2
S
D
1
TSSOP-8
Pin 1
Absolute Maximum Ratings T
G
1
S
1
1
o
=25
C unless otherwise noted
A
1
2
3
4
8
7
6
5
Symbol Parameter Ratings Units
V
Drain-Source Voltage –12 V
DSS
V
Gate-Source Voltage
GSS
ID Drain Current – Continuous (Note 1) –6 A
Pulsed –30
PD Power Dissipation for Single Operation (Note 1a) 1.3 W
TJ, T
STG
(Note 1b)
Operating and Storage Junction Temperature Range –55 to +150
±8
1
V
°C
Thermal Characteristics
R
θJA
Thermal Resistance, Junction-to-Ambient
(Note 1b)
(Note 1a) 100
125
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
2508P FDW2508P 13’’ 12mm 2500 units
2001 Fairchild Sem iconductor Corporation
°C/W
FDW2508P Rev . E (W)
FDW2508P
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
Drain–Source Breakdown Voltage
DSS
BVDSS T
I
Zero Gate Voltage Drain Current VDS = –10 V, VGS = 0 V –1
DSS
I
GSSF
I
GSSR
Breakdown Voltage Temperature Coefficient
J
Gate–Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA
Gate–Body Leakage, Reverse VGS = –8 V, VDS = 0 V –100 nA
V
= 0 V, ID = –250 µA
GS
I
= –250 µA, Referenced to 25°C
D
–12 V
–2
mV/°C
µA
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
VGS(th)TJ
R
DS(on)
Gate Threshold Voltage Temperature Coefficient
Static Drain–Source
On–Resistance
I
On–State Drain Current VGS = –4.5 V, VDS = –5 V –30 A
D(on)
V
= VGS, ID = –250 µA
DS
I
= –250 µA, Referenced to 25°C
D
VGS = –4.5 V, ID = –6 A V
= –2.5 V, ID = –5 A
GS
= –1.8 V, ID = –4 A
V
GS
= –4.5 V, ID = –6A, TJ=125°C
V
GS
–0.4 –0.5 –1.5 V
2.7
14
17 22 18
18 22 30 25
mV/°C
m
gFS Forward Transconductance VDS = –5 V, ID = –6 A 32 S
Dynamic Characteristics
= –6 V, V
V
C
Input Capacitance 2644 pF
iss
C
Output Capacitance 987 pF
oss
C
Reverse Transfer Capacitance
rss
DS
f = 1.0 MHz
= 0 V,
GS
602 pF
Switching Characteristics (Note 2)
V
= –6 V, ID = –1 A,
t
Turn–On Delay Time 14 25 ns
d(on)
tr Turn–On Rise Time 9.1 18 ns
t
Turn–Off Delay Time 122 195 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 26 36 nC
Qgs Gate–Source Charge 4 nC
Qgd Gate–Drain Charge
DD
= –4.5 V, R
V
GS
V
= –6 V, ID = –6 A,
DS
= –4.5 V
V
GS
GEN
= 6
89 142 ns
7 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current –1.1 A
VSD Drain–Source Diode Forward
VGS = 0 V, IS = –1.1 A (Note 2) –0.59 –1.2 V
Voltage
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
a) R
is 100°C/W (steady state) when mounted on a 1 inch² copper pad on FR-4.
θJA
is 125°C/W (steady state) when mounted on a minimum copper pad on FR-4.
b) R
θJA
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
is guaranteed by design while R
θJC
is determined by the user's board design.
θCA
FDW2508P Rev . E (W)
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