FDS8958A
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description Features
June 1998
These dual N- and P -Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
SuperSOTTM-6
D2
D2
D1
D1
FDS
8958A
G2
S2
SO-8
pin 1
G1
S1
N-Channel 7.0 A,30 V, R
R
P-Channel -5.0 A,-30 V,R
R
High density cell design for extremely low R
=0.028 Ω @ VGS=10 V
DS(ON)
=0.040 Ω @ VGS= 4.5 V.
DS(ON)
=0.052 Ω @ VGS=-10 V
DS(ON)
=0.080Ω @ VGS=-4.5 V.
DS(ON)
.
DS(ON)
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
Drain-Source Voltage 30-30V
Gate-Source Voltage20-20V
Drain Current - Continuous (Note 1a)7-5A
- Pulsed20-20
Power Dissipation for Dual Operation 2W
Power Dissipation for Single Operation (Note 1a)1.6
(Note 1b)1
(Note 1c)0.9
Operating and Storage Temperature Range-55 to 150°C
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
JA
θ
design while R
Turn - On Delay TimeV
= 10 V, I D = 1 A N-Ch816ns
DS
VGS = 10 V , R
GEN
= 6 Ω
P-Ch1120
Turn - On Rise TimeN-Ch1425ns
P-Ch1018
Turn - Off Delay TimeV
= -10 V, I D = -1 A N-Ch2337ns
DS
VGS = -10 V , R
GEN
= 6 Ω
P-Ch90125
Turn - Off Fall TimeN-Ch918ns
P-Ch5580
Total Gate Charge
VDS = 10 V, I D = 7 A,
VGS = 10 V
N-Ch1826nC
P-Ch1927
Gate-Source ChargeN-Ch3.2nC
VDS = -10 V, I D = -5 A,P-Ch3.5
Gate-Drain Charge
VGS = -10 V
N-Ch4.3nC
P-Ch3.6
Maximum Continuous Drain-Source Diode Forward CurrentN-Ch1.3A
P-Ch-1.3A
Drain-Source Diode Forward VoltageVGS = 0 V, IS = 1.3 A
VGS = 0 V, IS = -1.3 A
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R