Fairchild Semiconductor FDS8936A Datasheet

May 1998

FDS8936A
Dual N-Channel Enhancement Mode Field Effect Transistor

General Description Features

SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance
and provide superior switching performance. These devices
are particularly suited for low voltage applications such as
notebook computer power management and other battery
powered circuits where fast switching, low in-line power loss,
and resistance to transients are needed.

6 A, 30 V. R
R

High density cell design for extremely low R

= 0.028 Ω @ VGS = 10 V,

DS(ON)

= 0.040 Ω @ VGS = 4.5 V.

DS(ON)

DS(ON)

.

High power and current handling capability in a widely
used surface mount package.

Dual MOSFET in surface mount package.

SOT-23

D1

D1

D2

SuperSOTTM-6

D2

FDS

SuperSOTTM-8

SO-8 SOT-223

5
6

SOIC-16

4

3

8936A

7

8

SO-8

pin 1

S1

Absolute Maximum Ratings T

G2

S2

G1

= 25oC unless otherwise noted

A

Symbol Parameter FDS8936A Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) 6 A

- Pulsed 20

P

D

Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6

(Note 1b) 1
(Note 1c) 0.9

TJ,T

Operating and Storage Temperature Range -55 to 150 °C

STG

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

2

1

© 1998 Fairchild Semiconductor Corporation

FDS8936A Rev.B

Electrical Characteristics (T

= 25 OC unless otherwise noted )

A

Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS

BV

∆BV

I

DSS

I

GSSF

I

GSSR

DSS

DSS

Drain-Source Breakdown Voltage VGS = 0 V, I D = 250 µA 30 V
Breakdown Voltage Temp. Coefficient

/∆T

J

Zero Gate Voltage Drain Current

ID = 250 µA, Referenced to 25oC
VDS = 24 V, V

GS

= 0 V

32

1 µA

TJ = 55°C
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse

VGS = -20 V, V

DS

= 0 V

mV/ oC

10 µA

-100 nA

ON CHARACTERISTICS (Note 2)

V

∆V

R

GS(th)

GS(th)

DS(ON)

Gate Threshold Voltage V
Gate Threshold Voltage Temp. Coefficient

/∆T

J

Static Drain-Source On-Resistance

= VGS, ID = 250 µA 1 1.7 3 V

DS

ID = 250 µA, Referenced to 25oC
VGS = 10 V, I D = 6 A

-4

0.023 0.028

mV/oC

Ω

TJ =125°C 0.036 0.048

0.034 0.004

19 S

I
g

D(ON)

FS

VGS = 4.5 V, I D = 4.8 A
On-State Drain Current VGS = 10 V, VDS = 5 V 20 A
Forward Transconductance

VDS = 5 V, I D = 6 A

DYNAMIC CH ARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance VDS = 15 V, VGS = 0 V,
Output Capacitance 345 pF

f = 1.0 MHz

650 pF

Reverse Transfer Capacitance 95 pF

SWITCHING CHARACTERISTICS (Note 2)

t
t

t
t
Q
Q
Q

D(on)

r

D(off)

f

Turn - On Delay Time
Turn - On Rise Time

V

= 10 V, I D = 1 A

DS

VGS = 10 V , R

GEN

= 6 Ω

Turn - Off Delay Time 23 37
Turn - Off Fall Time 9 18

g

gs

gd

Total Gate Charge
Gate-Source Charge
Gate-Drain Charge 4.3

VDS = 10 V, I D = 6 A,

VGS = 10 V

8 16 ns

14 25

19 27 nC

3.2

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1. R
design while R

JA

θ

Maximum Continuous Drain-Source Diode Forward Current 1.3 A
Drain-Source Diode Forward Voltage

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

is determined by the user's board design.

CA

θ

VGS = 0 V, I S = 1.3 A

(Note 2)

0.7 1.2 V

is guaranteed by

JC

θ

a. 78OC/W on a 0.5 in

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

pad of 2oz copper.

2

b. 125OC/W on a 0.02 in

pad of 2oz copper.

2

c. 135OC/W on a 0.003 in

pad of 2oz copper.

2

FDS8936A Rev.B