Fairchild Semiconductor FAN4803-2 Datasheet

www.fairchildsemi.com

REV. 1.2.2 5/20/02

Features

• Internally synchronized PFC and PWM in one 8-pin IC

• Patented one-pin voltage error ampliﬁer with advanced input current shaping technique

• Peak or average current, continuous boost, leading edge PFC (Input Current Shaping Technology)

• High efﬁciency trailing-edge current mode PWM

• Low supply currents; start-up: 150µA typ., operating: 2mA typ.

• Synchronized leading and trailing edge modulation

• Reduces ripple current in the storage capacitor between the PFC and PWM sections

• Overvoltage, UVLO, and brownout protection

• PFC V

OVP with PFC Soft Start

General Description

The FAN4803 is a space-saving controller for power factor corrected, switched mode power supplies that offers very low start-up and operating currents.

Power Factor Correction (PFC) offers the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply fully compliant to IEC1000-3-2 speciﬁcations. The FAN4803 includes circuits for the implementation of a leading edge, average current “boost” type PFC and a trailing edge, PWM.

The FAN4803-1’s PFC and PWM operate at the same frequency, 67kHz. The PFC frequency of the FAN4803-2 is automatically set at half that of the 134kHz PWM. This higher frequency allows the user to design with smaller PWM components while maintaining the optimum operating frequency for the PFC. An overvoltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting for enhanced system reliability.

Block Diagram

SENSE

VEAO

LIMIT

GND

PWM OUT

PFC OUT

–

COMP

35µA

16.2V

17.5V

–

COMP

–

–1V

SOFT START

PFC/PWM UVLO

DUTY CYCLE

LIMIT

OSCILLATOR

PFC – 67kHz

PWM – 134kHz

REF

1.2V

26k

40k

R1 C1

30pF

PWM

CONTROL

LOGIC

–

1.5V

DC I

LIMIT

PFC I

LIMIT

PWM COMPARATOR

VCC OVP

PFC OFF

ONE PIN ERROR AMPLIFIER

LEADING

EDGE PFC

TRAILING

EDGE PWM

–

COMP

–

COMP

–1

–4

REF

PFC

CONTROL

LOGIC

FAN4803

8-Pin PFC and PWM Controller Combo

FAN4803 PRODUCT SPECIFICATION

REV. 1.2.2 5/20/02

Pin Conﬁguration

Pin Description

PFC OUT

GND

SENSE

VEAO

PWM OUT

LIMIT

TOP VIEW

8-Pin SOIC (S08)

8-Pin PDIP (P08)

FAN4803

PIN NAME FUNCTION

1 PFC OUT PFC driver output

2 GND Ground

SENSE

Current sense input to the PFC current limit comparator

4 VEAO PFC one-pin error amplifier input

PWM voltage feedback input

LIMIT

PWM current limit comparator input

Positive supply (may require an external shunt regulator)

8 PWM OUT PWM driver output

Absolute Maximum Ratings

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.

Operating Conditions

Parameter Min Max Unit

Current (average) 40 mA

MAX 18.3 V

SENSE

Voltage -5 1 V

Voltage on Any Other Pin GND – 0.3 V

+ 0.3 V

Peak PFC OUT Current, Source or Sink 1 A

Peak PWM OUT Current, Source or Sink 1 A

PFC OUT, PWM OUT Energy Per Cycle 1.5 µJ

Junction Temperature 150 °C

Storage Temperature Range -65° 150 °C

Lead Temperature (Soldering, 10 sec) 260 °C

Thermal Resistance ( θ

)

Plastic DIP 110 °C/W

Plastic SOIC 160 °C/W

Temperature Range

FAN4803CS-X 0°C to 70°C

FAN4803CP-X 0°C to 70°C

PRODUCT SPECIFICATION FAN4803

REV. 1.2.2 5/20/02

Electrical Characteristics

Unless otherwise speciﬁed, V

= 15V, T

= Operating Temperature Range (Note 1)

Note:

1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.

Symbol Parameter Conditions Min TYP MAX UNITS

One-pin Error Ampliﬁer

EAO

Output Current T

= 25°C, V

EAO

= 6V 31.5 34.0 36.5 µA

EAO

Output Current FAN4803-1

= 25°C, V

EAO

= 6V

34.0 36.5 39.0 µA

Line Regulation 10V < V

< 15V, V

EAO

= 6V 0.1 0.3 µA

OVP Comparator

Threshold Voltage 15.5 16.3 16.8 V

PFC I

LIMIT

Comparator

Threshold Voltage -0.9 -1 -1.15 V

Delay to Output 150 300 ns

DC I

LIMIT

Comparator

Threshold Voltage 1.4 1.5 1.6 V

Delay to Output 150 300 ns

Oscillator

Initial Accuracy T

= 25°C 60 67 74 kHz

Voltage Stability 10V < V

< 15V 1 %

Temperature Stability 2 %

Total Variation Over Line and Temp 60 67 74.5 kHz

Dead Time PFC Only 0.3 0.45 0.65 µs

PFC

Minimum Duty Cycle V

EAO

> 7.0V,I

SENSE

= -0.2V 0 %

Maximum Duty Cycle V

EAO

< 4.0V,I

SENSE

= 0V 90 95 %

Output Low Impedance 8 15

Ω

Output Low Voltage I

OUT

= –100mA 0.8 1.5 V

OUT

= –10mA, V

= 8V 0.7 1.5 V

Output High Impedance 8 15

Ω

Output High Voltage I

OUT

= 100mA, V

= 15V 13.5 14.2 V

Rise/Fall Time C

= 1000pF 50 ns

PWM

Duty Cycle Range FAN4803-2 0-41 0-47 0-50 %

FAN4803-1 0-49.5 0-50 %

Output Low Impedance 8 15

Ω

Output Low Voltage I

OUT

= –100mA 0.8 1.5 V

OUT

= –10mA, V

= 8V 0.7 1.5 V

Output High Impedance 8 15

Ω

Output High Voltage I

OUT

= 100mA, V

= 15V 13.5 14.2 V

Rise/Fall Time C

= 1000pF 50 ns

Supply

Clamp Voltage (V

CCZ

= 10mA 16.7 17.5 18.3 V

Start-up Current V

= 11V, C

= 0 0.2 0.4 mA

Operating Current V

= 15V, C

= 0 2.5 4 mA

Undervoltage Lockout Threshold 11.5 12 12.5 V

Undervoltage Lockout Hysteresis 2.4 2.9 3.4 V

FAN4803 PRODUCT SPECIFICATION

REV. 1.2.2 5/20/02

Functional Description

The FAN4803 consists of an average current mode boost Power Factor Corrector (PFC) front end followed by a synchronized Pulse Width Modulation (PWM) controller. It is distinguished from earlier combo controllers by its low pin count, innovative input current shaping technique, and very low start-up and operating currents. The PWM section is dedicated to peak current mode operation. It uses conventional trailing-edge modulation, while the PFC uses leadingedge modulation. This patented Leading Edge/Trailing Edge (LETE) modulation technique helps to minimize ripple current in the PFC DC buss capacitor.

The FAN4803 is offered in two versions. The FAN4803-1 operates both PFC and PWM sections at 67kHz, while the FAN4803-2 operates the PWM section at twice the frequency (134kHz) of the PFC. This allows the use of smaller PWM magnetics and output ﬁlter components, while minimizing switching losses in the PFC stage.

In addition to power factor correction, several protection features have been built into the FAN4803. These include soft start, redundant PFC over-voltage protection, peak current limiting, duty cycle limit, and under voltage lockout (UVLO). See Figure 12 for a typical application.

Detailed Pin Descriptions

EAO

This pin provides the feedback path which forces the PFC output to regulate at the programmed value. It connects to programming resistors tied to the PFC output voltage and is shunted by the feedback compensation network.

SENSE

This pin ties to a resistor or current sense transformer which senses the PFC input current. This signal should be negative with respect to the IC ground. It internally feeds the pulseby-pulse current limit comparator and the current sense feedback signal. The I

LIMIT

trip level is –1V. The I

SENSE

feedback is internally multiplied by a gain of four and compared against the internal programmed ramp to set the PFC duty cycle. The intersection of the boost inductor current downslope with the internal programming ramp determines the boost off-time.

This pin is typically tied to the feedback opto-collector. It is tied to the internal 5V reference through a 26k Ω resistor and to GND through a 40k Ω resistor.

LIMIT

This pin is tied to the primary side PWM current sense resistor or transformer. It provides the internal pulse-by-pulse current limit for the PWM stage (which occurs at 1.5V) and the peak current mode feedback path for the current mode

control of the PWM stage. The current ramp is offset internally by 1.2V and then compared against the opto feedback voltage to set the PWM duty cycle.

PFC OUT and PWM OUT

PFC OUT and PWM OUT are the high-current power drivers capable of directly driving the gate of a power MOSFET with peak currents up to ±1A. Both outputs are actively held low when V

is below the UVLO threshold level.

is the power input connection to the IC. The V

start-

up current is 150µA . The no-load I

current is 2mA. V

quiescent current will include both the IC biasing currents and the PFC and PWM output currents. Given the operating frequency and the MOSFET gate charge (Qg), average PFC and PWM output currents can be calculated as I

OUT

= Qg x F. The average magnetizing current required for any gate drive transformers must also be included. The V

pin is also assumed to be proportional to the PFC output voltage. Internally it is tied to the V

OVP comparator (16.2V) providing redundant high-speed over-voltage protection (OVP) of the PFC stage. V

also ties internally to the

UVLO circuitry, enabling the IC at 12V and disabling it at

9.1V. V

must be bypassed with a high quality ceramic bypass capacitor placed as close as possible to the IC. Good bypassing is critical to the proper operation of the FAN4803.

is typically produced by an additional winding off the boost inductor or PFC Choke, providing a voltage that is proportional to the PFC output voltage. Since the V

OVP max

voltage is 16.2V, an internal shunt limits V

overvoltage to an acceptable value. An external clamp, such as shown in Figure 1, is desirable but not necessary.

Figure 1. Optional V

Clamp

is internally clamped to 16.7V minimum, 18.3V maxi-

mum. This limits the maximum V

that can be applied to

the IC while allowing a V

which is high enough to trip the

OVP. The max current through this zener is 10mA. External series resistance is required in order to limit the current through this Zener in the case where the V

voltage

exceeds the zener clamp level.

GND

1N4148

1N5246B

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