Fairchild Semiconductor DM9374N Datasheet

March 1989
Revised March 2000

DM9374
7-Segment Decoder/Driver/Latch

with Constant Current Sink Outputs

General Description

The DM74 is a 7-segment decoder driver incorporating
input latches and output circ uits to directly drive comm on
anode LED displays.

Ordering Code:

Order Number Package Number Package Description

DM9374N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram Logic Symbol

DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs

VCC = Pin 16
GND = Pin 8

Pin Descriptions

Pin

Names

A0–A3 Address (Data Inputs)
LE
RBI
RBO

–g Constant Current Outputs (Active LOW)

a

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Latch Enable Input (Active LOW)
Ripple Blanking Input (Active LOW)
Ripple Blanking as Output (Active LOW)
as Input (Active LOW)

Description

Truth Table

Binary Inputs Outputs

DM9374

State LE

— H (Note 1) X X X X STABLE H Stable

0 L L L L L L HHHHHHH L Blank
0 L H L L L L LLLLLLH H 0
1 L X LLLHHLLHHHH H 1

2L X LLHLLLHLLHL H 2
3 L X L L H H LLLLHHL H 3
4 L X L H L L HLLHHLL H 4
5L X LHLHLHLLHLL H 5

6 L X L H H L LHLLLLL H 6
7 L X LHHHLLLHHHH H 7
8 L X H L L L LLLLLLL H 8
9 L X H L L HLLLLHLL H 9

10 L X H L H L HHHHHHL H —

11 L X H L H HLHHLLLL H E
12 L X H H L L HLLHLLL H H
13 L X H H L H HHHLL LH H L
14 L X H H H L LLHHLLL H P
15 L X H H H H HHHHHHH H BLANK

X X X X X X X HHHHHHHL (Note 2) BLANK

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Note 1: The RBI
Note 2: RBO

will blank the display only if a binary zero is stor ed in the latches.

used as an input overrides all other input conditions.

RBI A3 A2 A1 A0 a b c d e f g RBO

Display

Numerical Designations

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Functional Description

The DM9374 is a 7-segment decoder/driver with latches on
the address inputs and active LO W constant current out­puts to drive LEDs directly. This device accepts a 4-bit
binary code and produce s output drive to the appro priate
segments of the 7-segment display. It has a decode format

which produces nu meric codes “0” through “ 9” and other
codes.

Latches on the four data in puts a re cont rolle d by a n acti ve
LOW Latch Enable, LE
outputs is determined b y the input data. When LE
HIGH, the last data present at the i nputs is stored in the
latches and the outputs remain sta ble. The LE
necessary to accept and store data is typically 50 ns, which
allows data to be strobe d into the DM9374 at normal TTL
speeds. This feature means that data can be routed
directly from high speed counters and frequency dividers
into the display without slowing down the system clock or
providing intermediate data storage.

The latch/decoder combinatio n is a simple system which
drives LED displays with multiplexed data inputs from MOS
time clocks, DVMs, calculator chips, etc. Data inputs are
multiplexed while the displays are in static mode. This low­ers component and insertion costs, since several circuits—
seven resistors per display, strobe drivers, a se parate dis­play voltage source, and clock failure detect circuits—tradi­tionally found in multiplexed display systems are

. When LE is LOW, the state of the

goes

pulse width

Logic Diagram

eliminated. It also allows low strobing rates to be used with­out display flicker.

Another DM9374 feature is the reduced loading on the
data inputs when the Latch Enable is HIGH (only 1 0 µA
typ). This allows many DM937 4s to be driven fro m a MOS
device in multiplex mod e without the need for drivers on
the data lines. The DM9374 also provides automatic blank­ing of the leading a nd /or trailing-edge zeroes in a mu l tidi g it
decimal number, resulting in an easily readable decimal
display conforming to no rmal writing p ractice. In a n 8-digit
mixed integer fraction decimal representation, using the
automatic blanking capability 0060.0300 would be dis­played as 60.03. Leading-edge zero suppression is
obtained by connecting the Ripple Bl anking Output (RBO
of a decoder to the Ri pple Bl anking Input (RBI
lower stage device. The most significant decoder stage
should have the RIB
sion of the least significa nt integ er zero in a n umber is no t
usually desired, the RBI
be left open. A si m ilar procedure for th e fra cti on al p ar t o f a
display will provide automatic suppression of trailing-edge
zeroes. The RBO
with a modulating signal via an isolating buffer to achieve
duration intensity modulation. A suitable signal can be gen­erated for this purpose by forming a variable frequency
multivibrator with a cross coupled pair of TTL or DTL gates.

input grounded; an d since suppres-

input of this decoder sta ge should

terminal of t he decoder can be OR-tied

) of the next

DM9374

)

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