Fairchild Semiconductor DM74S299N Datasheet
August 1986
Revised May 2000
DM74S299
3-STATE 8-Bit Universal Shift/Storage Register
DM74S299 3-STATE 8-Bit Universal Shift/Storage Register
General Description
This Schottky TTL eigh t-bit universal reg ister fe atu re s m ultiplexed inputs/outputs to ac hieve full eight bit data handling in a single 20-pin package. Two function-select inputs
and two output-control inputs can be used to choose the
modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking
both function-sele ct lines, S0 and S1, HIG H. This places
the 3-STATE outputs in a high-impedance state, which permits data that is applied on the input/output lines to be
clocked into the register. Reading out of the register can be
accomplished while th e outputs ar e enable d in any mod e.
A direct overriding input is provided to clear the register
whether the outputs are ENABLED or OFF.
Features
■ Multiplexed inputs/outputs provide improved bit density
■ Four modes of operation:
Hold (Store) Shift Left
Shift Right Load Data
■ 3-STATE outputs drive bus lines directly
■ Can be cascaded for N-bit word lengths
■ Operates with outputs enabled or at high Z
■ Guaranteed shift (clock) frequency 50 MHz
■ Typical power dissipation 700 mW
Ordering Code:
Order Number Package Number Package Description
DM74S299N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006485 www.fairchildsemi.com
Function Table
Inputs Inputs/Outputs Outputs
Mode Function Output
A/Q
DM74S299
Clear Select Control Clock Serial
1
S1 S0
G
(Note 1)G2(Note 1)
SL SR
B/QBC/QCD/QDE/QEF/QFG/QG H/QHQA′Q
A
Clear L X L L L X X X L L L L L L L L L L
LLX L L XXXL LLLLL L LLL
Hold H L L L L X X X Q
A0QB0QC0QD0QE0QF0QG0QH0QA0QH0
HXX L L LXXQA0QB0QC0QD0QE0QF0QG0QH0QA0Q
Shift
HLH L L ↑ XH HQAnQBnQCnQDnQEnQFnQGnHQ
Right
HLH L L ↑ XL L QAnQBnQCnQDnQEnQFnQGnLQ
Shift
HHL L L ↑ HXQBnQCnQDnQEnQFnQGnQHnHQBnH
Left
HHL L L ↑ LXQ
BnQCnQDnQEnQFnQGnQHn
LQBnL
Load H H H X X ↑ XX a b c d e f g h ah
a...h = The level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop outputs are isolated
from the input/output terminals.
H = HIGH Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
...QH0 = The output logic level of QX before the indicate d input conditions were established.
Q
A0
...QHn = The output logic level before the active transition (↑) of the clock input.
Q
An
Note 1: When one or both output controls are HIGH the eight input/output terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the regis t er is not affected
Logic Diagram
H′
H0
Gn
Gn
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