Fairchild Semiconductor DM74S163N, DM74S161N Datasheet

DM74S161 • DM74S163 Synchronous 4-Bit Binary Counters

August 1986 Revised April 2000

General Description

These synchronous, pres ettable counters fe ature an internal carry look-ahead for a ppl ica ti on in hi gh -sp eed co unt ing designs. They are 4-bit binary counters. The carry output is decoded by means of a NOR ga te, thus pre venting sp ikes during the normal cou nting mode of operation. Synchronous operation is provi ded by having all flip- flops clocked simultaneously so t hat the out puts change coincident wi th each other when so instru cted by the count en able inputs and internal gating. Thi s mode of operation elim inates the output counting spikes w hich are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positivegoing) edge of the clock input waveform.

These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a LOW level at the load input disables the counter and causes th e outputs to agree with the setup data after the next clock pulse regard less of the levels of the enable input.

The carry look-ahead circuitry provides for cascading counters for n-bit synchro nous applications without additional gating. Instrumental in accomplishing this function are two count-enable inpu ts and a ripple carry output. Both count-enable inputs (P and T) must be H IGH to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a HIGH-level output pulse with a duration approximately equal to the HIGH-level portion of the Q

flow ripple carry pu lse can be used to en able successive cascaded stages.

output. This HIGH-le vel ov er-

Features

■ Synchronously programmable

■ Internal look-ahead for fast counting

■ Carry output for n-bit cascading

■ Synchronous counting

■ Load control line

■ Diode-clamped inputs

Ordering Code:

Order Number Package Number Package Description

DM74S161N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74S163N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram

Logic Diagram

DM74S161 • DM74S163

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Timing Diagram

DM74S161 • DM74S163

Sequence:

1. Clear outputs to zero

2. Preset to binary twelve

3. Count to thirteen, fourteen, fifteen, zero, one and two

4. Inhibit

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