Fairchild Semiconductor DM74ALS874BWMX, DM74ALS874BWM, DM74ALS874BNT Datasheet

© 2000 Fairchild Semiconductor Corporation DS006244 www.fairchildsemi.com

April 1984
Revised February 2000

DM74ALS874B Dual 4-Bit D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs

DM74ALS874B
Dual 4-Bit D-Type Edge-Triggered Flip-Flop

with 3-STATE Outputs

General Description

This dual 4-bit register fea tures totem-pole 3-STATE out­puts designed specifically for driving highly-capacitive or
relatively low-impedance loads. The hig h-impedance stat e
and increased high-logic-level drive provide this register
with the capability of being connected directly to and driv­ing the bus lines in a bus- organized system without ne ed
for interface or pull-up compon ents. It is parti cularly a ttrac­tive for implementing buffer registers, I/O ports, bidirec­tional bus drivers, and working registers.

The eight flip-flops of the DM74ALS874B are edge-trig­gered D-type flip-flops. On the positive transition of the
clock, the Q outputs will be set to the logic states that were
set up at the D inputs.

A buffered output control input ca n be used to place the
eight outputs in either a normal l ogic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped­ance state the outputs ne ither load nor dr ive the bus lines
significantly.

The output control does not affect the i nternal oper ation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

CC

range

■ Advanced oxide-isolated, ion-implanted Schottky TTL
process

■ 3-STATE buffer-type outputs drive bus lines directly

■ Space saving 300 mil wide package

■ Asynchronous clear

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Order Number Package Number Package Description

DM74ALS874BWM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS874BNT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

www.fairchildsemi.com 2

DM74ALS874B

Function Table

L = LOW State
H = HIGH State
X = Don’t Care
↑ = Positive Edge Transition
Z = High Impedance State
Q

0

= Previous Condit ion of Q

Logic Diagram

Inputs Output

CLR

DCLKOC Q

XXXHZ
LXXLL
HH↑ LH
HL↑ LL
HXLLQ

0