Fairchild Semiconductor DM74ALS74ASJX, DM74ALS74ASJ, DM74ALS74AN, DM74ALS74AMX, DM74ALS74AM Datasheet
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© 2000 Fairchild Semiconductor Corporation DS006109 www.fairchildsemi.com
September 1986
Revised February 2000
DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74ALS74A
Dual D Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS74A contains two independent positive
edge-triggered flip-flops. Each flip-flop has individual D,
clock, clear and prese t inputs, and also comp lementary Q
and Q
outputs.
Information at input D is transf erred to the Q ou tput o n the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to t he transition time of the p ositive going
pulse. When the clock in put is at eith er the HIGH or LOW
level, the D input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full tempera-
ture and V
CC
range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
process
■ Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
■ Improved AC performa nce over LS74 at approxim ately
half the power
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram Function Table
L = LOW State
H = HIGH State
X = Don't Care
↑ = Positive Edge Transition
Q0 = Previous Condit ion of Q
Note 1: This condition is nonstable; it will not persist when preset and cl ear
inputs return to their inac tive (HIGH) level. The output levels in this condition are not guaranteed to meet the V
OH
specification.
Order Number Package Number Package Description
DM74ALS74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS74ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
PR
CLR CLK D Q Q
LHXX H L
HLXX L H
L L X X H (Note 1) H (Note 1)
HH↑ HH L
HH↑ LL H
HHLX Q
0
Q
0
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DM74ALS74A
Logic Diagram
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DM74ALS74A
Absolute Maximum Ratings(Note 2)
Note 2: The “Absolute M aximu m R atin gs” are t hose valu es b eyo nd w hich
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.
Recommended Operating Conditions
Note 3: The (↑) arrow indicates t he positive edge of the Clo c k is us ed for reference.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Typical θ
JA
N Package 87.0°C/W
M Package 117.0°C/W
Symbol Parameter Min Nom Max Units
V
CC
Supply Voltage 4.5 5 5 .5 V
V
IH
HIGH Level Input Voltage 2 V
V
IL
LOW Level Input Voltage 0.8 V
I
OH
HIGH Level Output Current −0.4 mA
I
OL
LOW Level Output Current 8 mA
f
CLK
Clock Frequency 0 34 MHz
t
W(CLK)
Width of Clock Pulse HIGH 14.5 ns
LOW 14.5 ns
t
W
Pulse Width
LOW 14.5 ns
Preset & Clear
t
SU
Data Setup Time Data 15↑ (Note 3)
PRE or CLR
10↑ (Note 3)
ns
Inactive
t
H
Data Hold Time 0↑ (Note 3) ns
T
A
Free Air Operating Temperature 0 70 °C
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