Fairchild Semiconductor DM74ALS109AM, DM74ALS109AN, DM74ALS109AMX Datasheet

DM74ALS109A

DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear

April 1984 Revised February 2000

Dual J-K

Positive-Edge-Triggered Flip-Flop

with Preset and Clear

General Description

The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K and also complementary Q and Q

Information at input J o r K the positive going edge of the clock pulse. Cl ock trigg ering occurs at a voltage level of the clock pulse and is not directly related to t he transition time of the p ositive going pulse. When the clock in put is at eith er the HIGH or LOW level, the J, K

Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal.

The J-K J and K

input signal has no effect.

design allows operation as a D flip-flop by tying the inputs together.

, clock, clear and preset inputs,

outputs.

is transferred to th e Q outp ut on

Ordering Code:

Order Number Package Number Package Description

DM74ALS109AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS109AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.

Connection Diagram Function Table

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V

■ Advanced oxide-isolated, ion-implanted Schottky TTL process

■ Functionally and pin for pin compatible with Schottky and LS TTL counterpart

■ Improved AC performance over LS 109 at a pproxim ately half the power

LHXXX H L HLXXX L H L L X X X H (Note 1) H (Note 1) HH↑ LL L H HH↑ H L TOGGLE HH↑ LH Q HH↑ HH H L HHLXX Q

L = LOW State H = HIGH State X = Don't Care ↑ = Positive Edge Transition,

= Previous Condit ion of Q

Note 1: This condition is nonstable; it will not persist when presen t and clear inputs return to th eir inactive (HIGH) lev el. The output leve ls in this condition are not guaranteed to meet the V

range

Inputs Outputs

CLR CK J K QQ

specification.

Logic Diagram

DM74ALS109A

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