Fairchild Semiconductor 74LVTH16646MTDX, 74LVTH16646MTD, 74LVTH16646MEAX, 74LVTH16646MEA Datasheet
© 2000 Fairchild Semiconductor Corporation DS012023 www.fairchildsemi.com
January 2000
Revised January 2000
74LVTH16646 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
74LVTH16646
Low Voltage 16-Bit Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH16646 contains sixteen non-inverting bidirectional registered bus transceivers providing multiplexed
transmission of data d irectly from the in put b us or fr om the
internal storage registe rs. Each byte has separate control
inputs which can be shorte d together for full 16-bit operation. The DIR inputs de termine the direction of data flow
through the device. The CPAB and CPBA inputs load data
into the registers on the LOW-to-HIGH transition (see
Functional Description).
The LVTH16646 data inputs includ e bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These transceivers are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environ ment. The LVTH16646 is fabricated with an advanced BiCMOS technology to achieve
high speed opera tion similar to 5V ABT while maintaining
low power dissipation.
Features
■ Input and output interface capability to systems at
5V V
CC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction per mitt ed
■ Power Up/Down high impedance provides
glitch-free bus loading
■ Outputs source/sink −32 mA/+64 mA
■ Functionally compatible with the 74 series 16646
■ Latch-up performance exceeds 500 mA
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74LVTH16646MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16646MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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74LVTH16646
Connection Diagram Pin Descriptions
Truth Table
(Note 1)
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
= LOW-to-HIGH Transitio n.
Note 1: The data o utput fu nctions may be en abled or disabl ed by vario us sig nals at th e OE
and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus p ins wil l be store d on eve ry LO W-to-H IGH trans itio n of th e a pprop ria te cloc k in puts. Als o appl ies t o dat a I/O ( A and B: 8- 15 ) and # 2 co ntrol
pins.
Pin Names Description
A
0–A15
Data Register A Inputs/3-STATE Outputs
B
0–B15
Data Register B Inputs/3-STATE Outputs
CPAB
n
, CPBAnClock Pulse Inputs
SAB
n
, SBAnSelect Inputs
OE
1
, OE
2
Output Enable Inputs
DIR
n
Direction Control Inputs
Inputs Data I/O
Output Operation Mode
OE
1
DIR1CPAB1CPBA1SAB1SBA1A
0–7B0–7
H X H or L H or L X X Isolation
HX
X X X Input Input C lock An Data into A Register
HXX
X X Clock Bn Data Into B Register
LHXXLX A
n
to Bn—Real Time (Transparent Mode)
LH
X L X Input Output Clock An Data to A Register
L H H or L X H X A Register to B
n
(Stored Mode)
LH
X H X Clock An Data into A Register and Output to B
n
LLXXXL Bn to An—Real Time (Transparent Mode)
LLX
X L Output Input Clock Bn Data into B Register
L L X H or L X H B Register to A
n
(Stored Mode)
LLX
X H Clock Bn into B Register and Output to A
n
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74LVTH16646
Functional Description
In the transceiver mode , data present a t the HIGH impe dance port may be sto red in either the A or B register or
both. The select (SAB
n
, SBAn) controls can multiplex
stored and real-time. The examples sh own below demo nstrate the four fundamental bus-management functions
that can be performed.
The direction control (DIR
n
) determines which bus will
receive data when OE
n
is LOW. In the isolation mode (OE
n
HIGH), A data may be stored in one reg ister and /or B data
may be stored in the other re gister. When an ou tput function is disabled, the input fu nction is still e nabled and may
be used to store and tr ansmit data. Only one of the two
busses, A or B, may be driven at a time.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
Transfer Storage
Data to A or B
Storage
OE
DIR CPAB CPBA SAB SBA
LL X X X L
OE DIR CPAB CPBA SAB SBA
LH X X L X
OE DIR CPAB CPBA SAB SBA
LL XH or LX H
LHH or LX H X
OE DIR CPAB CPBA SAB SBA
LH
XLX
LL X
XL
HX
XXX
HX X
XX
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