Fairchild Semiconductor 74F112SJX, 74F112SJ, 74F112SCX, 74F112SC, 74F112PC Datasheet
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© 1999 Fairchild Semiconductor Corporation DS009472 www.fairchildsemi.com
April 1988
Revised July 1999
74F112 Dual JK Negative Edge-Triggered Flip-Flop
74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 74F112 contains two indepen dent, high -spee d JK flipflops with Direct S et and Clear inputs. Sy nchronous state
changes are in itiated by the fa lling edg e o f the c lock . Triggering occurs at a voltage level of th e clock and is not
directly related to t he transition time. The J and K i nputs
can change when the clock is in either state w ithout affecting the flip-flop, provided that the y are in the desired st ate
during the recommen ded setup and hold ti mes relative to
the falling edge of the clock. A LOW signal on S
D
or C
D
prevents clocki ng and forces Q or Q HIGH, respectivel y.
Simultaneous LOW signals on S
D
and CD force both Q and
Q
HIGH.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and SD makes both Q
and Q
HIGH
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F112SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F112PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
74F112
Unit Loading/Fan Out
Tr uth Table
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW Clock Transition
Q
0(Q0
) = Before HIGH-to-LOW Transition of C lock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be use d to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH/IIL
HIGH/LOW
Output I
OH/IOL
J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP
1
, CP
2
Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 µA/−2.4 mA
C
D1
, C
D2
Direct Clear Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA
S
D1
, S
D2
Direct Set Inputs (Active LOW) 1.0/5.0 20 µA/−3.0 mA
Q
1
, Q2, Q1, Q2Outputs 50/33.3 −1 mA/20 mA
Inputs Outputs
S
D
C
D
CP JKQ Q
LHXXXHL
HLXXXLH
LLXXXHH
HH
hhQ0Q
0
HH
lhL H
HH
hlH L
HH
llQ0Q
0
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