Fairchild Semiconductor 74F109SJX, 74F109SJ, 74F109SCX, 74F109SC, 74F109PC Datasheet
© 1999 Fairchild Semiconductor Corporation DS009471 www.fairchildsemi.com
April 1988
Revised November 1999
74F109 Dual JK Positive Edge-Triggered Flip-Flop
74F109
Dual JK
Positive Edge-Triggered Flip-Flop
General Description
The F109 consists of two high-spe ed, com pletel y indepe ndent transition clocked JK
flip-flops. The clocking operat i on
is independent of rise and fal l tim es o f th e cl oc k wave for m.
The JK
design allows operati on as a D-type f lip-flop ( refer
to F74 data sheet) by connecting the J and K
inputs.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and SD makes
both Q and Q
HIGH
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending su ffix let te r “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74F109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide
74F109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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74F109
Truth Table
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
Q0 (Q0) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
Unit Loading/Fan Out
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Outputs
S
D
C
D
CP J K QQ
LHXXXHL
HLXXXLH
LLXXXHH
HH
IILH
HH
hI Toggle
HH
IhQQ
HH
hhHL
HHLXXQQ
Pin Names Description
U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
J1, J2, K1, K2Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP
1
, CP
2
Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
C
D1
, C
D2
Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA
S
D1
, S
D2
Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA
Q
1
, Q2, Q1, Q2Outputs 50/33.3 −1 mA/20 mA
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74F109
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired . Functional operation
under these conditions is not implied.
Note 2: Either voltage lim it or c urrent limit is sufficient to pro te c t in puts.
DC Electrical Characteristics
Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +175°C
V
CC
Pin Potential to
Ground Pin −0.5V to +7.0V
Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
cc
= 0V)
Standard Output −0.5V to V
CC
3-STATE Output −0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambient Temperature 0°C to +70°C
Supply Voltage +4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
V
OH
Output HIGH Voltage 10% V
CC
2.5
VMin
IOH = −1 mA
5% V
CC
2.7 IOH = −1 mA
V
OL
Output LOW Voltage 10% V
CC
0.5 V Min IOL = 20 mA
I
IH
Input HIGH Current 5.0 µAMaxVIN = 2.7V
I
BVI
Input HIGH Current Breakdown Test 7.0 µAMaxVIN = 7.0V
I
CEX
Output HIGH Leakage Current 50 µAMaxV
OUT
= V
CC
V
ID
Input Leakage Test
4.75 V 0.0
IID = 1.9 µA
All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current −0.6 mA Max VIN = 0.5V (Jn, Kn)
−1.8 mA Max VIN = 0.5V (CDn, SDn)
I
OS
Output Short-Circuit Current −60 −150 mA Max V
OUT
= 0V
I
CC
Power Supply Current 11.7 17.0 mA Max CP = 0V
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