Fairchild Semiconductor 74ALVCH16244 Datasheet
September 2001
Revised February 2002
74ALVCH16244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
74ALVCH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold
General Description
The ALVCH16244 contains sixteen non-inverting buffers
with 3-STATE outputs to be empl oyed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH16244 data inputs include acti ve bushold circuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74ALVCH16244 is designed for low volta ge (1.65V to
3.6V) V
The 74ALVCH16244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
applications with output capability up to 3.6V.
CC
Features
■ 1.65V to 3.6V VCC supply operation
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs elimin atin g the nee d for exte rnal
pull-up/pull-down resistors
■ t
PD
3 ns max for 3.0V to 3.6V V
3.7 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V V
■ Uses patented noise/EMI reductio n circuitr y
■ Latch-up conforms to JEDEC JED78
■ ESD performance:
Human body model
Machine model
> 200V
CC
CC
> 2000V
Ordering Code:
Order Number
74ALVCH16244T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.
Package
Number
Package Descript ion
Logic Symbol Pin Descriptions
Pin Names Description
OE
I
0–I15
O
n
0–O15
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2002 Fairchild Semiconductor Corporation DS500625 www.fairchildsemi.com
Connection Diagram Truth Tables
OE
1
LL L
74ALVCH16244
LH H
HX Z
OE
3
LL L
LH H
HX Z
OE
2
LL L
LH H
HX Z
OE
4
LL L
LH H
HX Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Inputs Outputs
I0–I
3
O0–O
Inputs Outputs
I8-I
11
O8–O
Inputs Outputs
I4-I
7
O4-O
Inputs Outputs
I12-I
15
O12-O
3
11
7
15
Functional Description
The 74ALVCH16244 contains sixteen non -i nv ert in g b uffers
with 3-STATE outputs. The devi ce is nibble (4 bits) controlled with each nibbl e fun ctioning identically, but independent of each other. The control pins may be shorted
together to obtain full 16- bit operation.The 3-STATE out-
Logic Diagram
www.fairchildsemi.com 2
puts are controlled by an Output Enable (OE
is LOW, the outputs are in the 2-state mode. When
OE
n
OE
is HIGH, the standard outputs ar e in the high imped-
n
) input. When
n
ance mode but this does not interfere with entering new
data into the inputs.
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