Fairchild Semiconductor 74ALVCH16240 Datasheet

September 2001
Revised February 2002

74ALVCH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with Bushold

General Description

The ALVCH16240 contains sixteen inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.

The ALVCH16240 data inputs include acti ve bushold cir­cuitry, eliminating the need for external pull-up resistors to
hold unused or floating inputs at a valid logic level.

The 74ALVCH16240 is designed for low volta ge (1.65V to

3.6V) V
The 74ALVCH16240 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain­ing low CMOS power dissipation.

applications with output capability up to 3.6V.

CC

Features

■ 1.65V to 3.6V VCC supply operation

■ 3.6V tolerant control inputs and outputs

■ Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

■ t

PD

3.9 ns max for 3.0V to 3.6V V

5.3 ns max for 2.3V to 2.7V VCC

6.0 ns max for 1.65V to 1.95V V

■ Uses patented noise/EMI reductio n circuitr y

■ Latch-up conforms to JEDEC JED78

■ ESD performance:

Human body model
Machine model

> 2000V

> 200V

74ALVCH16240 Low Voltage 16-Bit Inverting Buffer/Line Driver

CC

CC

Ordering Code:

Order Number

74ALVCH16240T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.

Package

Number

Package Descript ion s

Logic Symbol Pin Descriptions

Pin Names Description

OE

n

I

0–I15

O

0–O15

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Output Enable Input (Active LOW)

Bushold Inputs
Outputs

Connection Diagram Truth Tables

OE

LL H

74ALVCH16240

LH L
HX Z

Inputs Outputs
OE

2

LL H
LH L
HX Z

Inputs Outputs
OE

3

LLH
LHL
HXZ

Inputs Outputs
OE

4

LLH
LHL
HXZ

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance

Inputs Outputs

I4–I

I8–I

I12–I

I0–I

3

7

11

15

O4–O

O8–O

O12–O

1

7

11

15

O0–O

3

Functional Description

The 74ALVCH16240 contains sixteen inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble funct ioning ide ntically, but independent of
each other. The control pins may be shor ted together to
obtain full 16-bit ope ration.The 3-STATE outputs are con-

Logic Diagram

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trolled by an Output Enable (OEn) input. When OEn is
LOW, the outputs are in the 2-state mode. When OE

is

n

HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the inputs.