Fairchild Semiconductor 74ALVC16841 Datasheet

74ALVC16841
Low Voltage 20-Bit Transparent Latch

with 3.6V Tolerant Inputs and Outputs

74ALVC16841 Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Output s

November 2001
Revised November 2001

General Description

The ALVC16841 contains twenty non-inverting latches with
3-STATE outputs and is intended for bus orie nted applica­tions. The device is byte controlled . The flip-flops appe ar
transparent to the data when the Latch enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE
a high impedance state.

The 74ALVC16841 is designed for low voltage (1.65V to

3.6V) V
The 74ALVC16841 is fabricated w ith an advanc ed CMOS

technology to achieve high speed operation while maintain­ing low CMOS power dissipation.

) is LOW. When OE is HIGH, the outputs are in

applications with I/O compatibility up to 3.6V.

CC

Features

■ 1.65V–3.6V VCC supply operation

■ 3.6V tolerant inputs and outputs

(Dn to On)

■ t

PD

3.5 ns max for 3.0V to 3.6V V

3.9 ns max for 2.3V to 2.7V V

6.8 ns max for 1.65V to 1.95V V

■ Power-off high impedance inputs and outputs

■ Supports live insertion and withdrawal (Note 1)

■ Uses patented noise/EMI reductio n circuitr y

■ Latchup conforms to JEDEC JED78

■ ESD performance:

Human body model
Machine model

Note 1: To ensure the high-impedance state d uring power up or power
down, OE

should be tied to VCC through a pull-up r esistor; the min imum
value of the res istor is d eter mine d by the cu rre nt-sou rcin g ca pa bility of t he
driver.

> 200V

CC
CC

CC

> 2000V

Ordering Code:

Order Number Package Number Package Description

74ALVC16841MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol Pin Descriptions

Pin Names Description

OE

D

0–D19

O

0–O19

LE

n

n

Output Enable Input (Active LOW)

Latch Enable Input

Inputs

Outputs

© 2001 Fairchild Semiconductor Corporation DS500690 www.fairchildsemi.com

Connection Diagram Truth Tables

74ALVC16841

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance

= Previous O0 before HIGH-to-LOW of Latch Enable

O

0

Functional Description

The 74ALVC16841 contains twenty D-type latches with
3-STATE outputs. The device is byte controlled with ea ch
byte functioning iden tically, but independent of the othe r.
Control pins can be shorted tog ether to obtain full 20-bit
operation. The following description applies to each byte.
When the Latch Enable (LE

) input is HIGH, data on the D

n

enters the latches. I n this condition the latch es are trans­parent, i.e., a latch output will chan ge states each time its

D-type input changes. Wh en LE
information that was presen t on the D-type inputs a setup

time preced ing the HIGH-to-LOW transi tion on LE
3-STATE outputs are controlled by the Output Enable

(OE

) input. When OEn is LOW the standard outputs are in

n

n

the 2-state mode. When OE
are in the high i mpe da nce mo de bu t th i s do es not interfere

with entering new data into the latches.

Inputs Outputs

LE

OE

1

D0–D

1

O0–O

9

9

XHXZ
HLL L
HLHH
LLXO

0

Inputs Outputs

LE

OE

2

D10–D19O10–O

2

19

XHXZ
HLL L
HLHH
LLXO

is LOW, the latches store

n

is HIGH, the standard outputs

n

0

. The

n

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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