Fairchild Semiconductor 74ALVC16373 Datasheet
74ALVC16373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
74ALVC16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
October 2001
Revised October 2001
General Description
The ALVC16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is l atched. Data appe ars on the bus wh en
the Output Enable (OE
outputs are in a high impedance state.
The 74ALVC16373 is designed for low voltage (1.1V to
3.6V) V
The 74ALVC16373 is fabricated w ith an advanc ed CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
applications with I/O compatibility up to 3.6V.
CC
) is LOW. When OE is HIGH, the
Features
■ 1.1V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
(In to On)
■ t
PD
3.5 ns max for 3.0V to 3.6V V
3.9 ns max for 2.3V to 2.7V V
6.8 ns max for 1.65V to 1.95V V
■ Power-off high impedance inputs and outputs
■ Support live insertion and withdrawal (Note 1)
■ Uses patented noise/EMI reductio n circuitr y
■ Latchup conforms to JEDEC JED78
■ ESD performance:
Human body model
Machine model
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state d uring power up or power
should be tied to VCC through a pull-up r esistor; the min imum
down, OE
value of the res istor is d eter mine d by the cu rre nt-sou rcin g ca pa bility of t he
driver.
> 200V
Ordering Code:
Order Number Package Number Package Description
74ALVC16373GX
(Note 2)
74ALVC16373MTD
(Note 3)
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
BGA54A
(Preliminary)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
CC
CC
CC
> 2000V
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500687 www.fairchildsemi.com
Connection Diagrams
Pin Descriptions
74ALVC16373
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Names Description
I
O
OE
n
LE
n
0–I15
0–O15
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
NC No Connect
FBGA Pin Assignments
123456
A O
B O
C O
D O
E O
F O
G O
H O
J O
NC OE1LE1NC I
0
O1NC NC I
2
O3V
4
6
8
10
12O11VCCVCCI11
14O13
15
CCVCCI3
O5GND GND I
O7GND GND I
O9GND GND I
NC NC I
NC OE2LE2NC I
1
5
7
9
13I14
Truth Tables
Inputs Outputs
LE
1
XHXZ
HLLL
HLHH
LLXO
LE
2
XHXZ
HLLL
HLHH
LLXO
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
= Previous O0 before HIGH-to-LOW of Latch Enable
O
0
OE
1
I0–I
7
O0–O
Inputs Outputs
OE
2
I8–I
15
O8–O
0
I
2
I
4
I
6
I
8
I
10
I
12
15
7
0
15
0
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Functional Description
The 74ALVC16373 contains sixteen edge D -type latches
with 3-STATE outputs. The dev ice is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be sh orted together to obtain full
16-bit operation. The foll owing description ap plies to each
byte. When the Latch Enable (LE
enters the latches. In this condit ion the latches are
the I
n
transparent, i.e., a latch output will change state each time
) input is HIGH, data on
n
Logic Diagram
its I input changes. When LE
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LE
3-STATE outputs are controlled by the Output Enable
(OE
) input. When OEn is LOW the standard outputs are in
n
the 2-state mode. When OE
are in the high i mp eda nce m ode bu t th i s d oes no t i nt erf ere
with entering new data into the latches.
is LOW, the latches store
n
. The
n
is HIGH, the standard outputs
n
74ALVC16373
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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