Fairchild Semiconductor 74ALVC162835 Datasheet

74ALVC162835
Low Voltage 18-Bit Universal Bus Driver

with 3.6V Tolerant Inputs/Outputs
and 26

Ω Series Resistors in Outputs

September 2001
Revised February 2002

74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tol erant Inputs/Outputs and 26

Resistors in Outputs

General Description

The ALVC162835 low voltage 18-bit un iversal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.

Data flow is controll ed b y ou tpu t-enable (OE
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog­gled. Data transfer s f rom the In pu ts (I

a Positive Edge Transition of the Clock. When OE
the output data is enabl ed. When OE
port is in a high impedance state.

The ALVC162835 is designed w ith 26
the outputs. This design reduces noise in applications such
as memory address drivers, clo ck drivers, and bus trans­ceivers/transmitters.

The 74ALVC162835 is designed for l ow voltage (1.6 5V to

3.6V) V
The 74ALVC162835 is fabricated with an adva nce d CMOS

technology to achieve high speed operation while maintain­ing low CMOS power dissipation.

applications with I/O capability up to 3.6V.

CC

), latch-enable

) to Outputs (On) on

n

is HIGH the output

Ω series resistors in

is LOW,

Features

■ Compatible with PC100 DIMM module specifications

■ 1.65V to 3.6V V

■ 3.6V tolerant inputs and outputs

Ω series resistors in outputs

■ 26

■ t

(CLK to On)

PD

5.4 ns max for 3.0V to 3.6V V

6.3 ns max for 2.3V to 2.7V V

9.2 ns max for 1.65V to 1.95V V

■ Power-off high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ Latchup conforms to JEDEC JED78

■ ESD performance:

Human body model
Machine model

Note 1: To ensure the high impedance state during power up or power
down, OE

should be tied to VCC through a pulldown res istor; the minimu m
value of the resistor is dete rmined by the curren t sourcing capabilit y of the
driver.

specifications provided

CC

CC
CC

> 2000V

>200V

CC

Ordering Code:

Order Number

74ALVC162835T MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also availab le in Tape and Reel. Specify by appending the suffix letter “X” to the o rdering code.

Package

Number

Package Description

© 2002 Fairchild Semiconductor Corporation DS500646 www.fairchildsemi.com

Ω

Series

Connection Diagram Pin Descriptions

Pin Names Descriptio n

OE
LE Latch Enable Input
CLK Clock Input
I

74ALVC162835

- I

1

18

- O

O

1

18

Truth Table

OE

H = Logic HIGH
L = Logic LOW
X = Don’t Care, but not floating

Z = High Impedance
↑ = LOW-to-HIGH Clock Transition

Note 2: Output level be fore the indicated steady-s tate input conditions
were established provided that CLK wa s HIGH before LE went L OW.

Note 3: Output level be fore the indicated steady-s tate input conditions
were established.

LE CLK I

HXXX Z
LHXL L
LHXH H
LL
LL
LLHXO
LLLXO

Output Enable Input (Active LOW)

Data Inputs
3-STATE Outputs

Inputs Outputs

n

O

n

↑ LL
↑ HH

(Note 2)

0

(Note 3)

0

Logic Diagram

www.fairchildsemi.com 2

Absolute Maximum Ratings(Note 4) Recommended Operating

Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (V
Output Voltage (V
DC Input Diode Current (I

V

< 0V −50 mA

I

DC Output Diode Current (I

< 0V −50 mA

V

O

) −0.5V to +4.6V

I

) (Note 5) −0.5V to VCC + 0.5V

O

)

IK

)

OK

DC Output Source/Sink Current

(I

) ±50 mA

OH/IOL

or Ground Current per

DC V

CC

Supply Pin (I

Storage Temperature Range (T

or Ground) ±100 mA

CC

) −65°C to +150°C

STG

Conditions

Power Supply

Operating 1.65V to 3.6V
Input Voltage 0V to V
Output Voltage (VO)0V to V
Free Air Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (

= 0.8V to 2.0V, VCC = 3.0V 10 ns/V

V

IN

Note 4: The “Absolute Maximum Ratings” are those value s beyond which
the safety of the d evice cannot b e guaranteed . The device sh ould not be
operated at these limit s. The parametric values defi ned in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat­ings. The Recommended Operating C onditions tables will define the condi­tions for actual device oper ation.

Absolute Maximum Rating must be observed.

Note 5: I

O

Note 6: Floating or unused pin (inputs or I/O's) must b e held HIGH or LOW.

(Note 6)

∆t/∆V)

DC Electrical Characteristics

V

Symbol Parameter Conditions

V

IH

V

IL

V

OH

V

OL

I

I

I

OZ

I

CC

∆I

HIGH Level Input Voltage 1.65 - 1.95 0.65 x V

LOW Level Input Voltage 1.65 - 1.95 0.35 x V

HIGH Level Output Voltage IOH = −100 µA 1.65 - 3.6 VCC - 0.2

LOW Level Output Voltage IOL = 100 µA 1.65 - 3.6 0.2

Input Leakage Current 0 ≤ VI ≤ 3.6V 3.6 ±5.0 µA
3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 3.6 ±10 µA
Quiescent Supply Current VI = VCC or GND, IO = 0 3.6 40 µA
Increase in ICC per Input VIH = VCC − 0.6V 3 - 3.6 750 µA

CC

IOH = −2 mA 1.65 1.2
I

= −4 mA 2.3 1.9

OH

= −6 mA 2.3 1.7

I

OH

I

= −8 mA 2.7 2

OH

= −12 mA 3.0 2

I

OH

I

= 2 mA 1.65 0.45

OL

= 4 mA 2.3 0.4

I

OL

IOL = 6 mA 2.3 0.55

IOL = 8 mA 2.7 0.6
IOL = 12 mA 3 0.8

CC

(V)

2.7 - 3.6 2.0

2.7 - 3.6 0.8

3.0 2.4

3.0 0.55

Min Max Units

CC

74ALVC162835

CC
CC

V2.3 - 2.7 1.7

CC

V2.3 - 2.7 0.7

V

V

3 www.fairchildsemi.com