Fairchild Semiconductor 74ABT273CSJX, 74ABT273CSJ, 74ABT273CSC, 74ABT273CMTCX, 74ABT273CMTC Datasheet

74ABT273
Octal D-Type Flip-Flop

74ABT273 Octal D-Type Flip-Flop

January 1993
Revised November 1999

General Description

The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outp uts. The common buffered
Clock (CP) and Master Reset (MR
(clear) all flip-flops simultaneously.

The register is fully edge-t riggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi­tion, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW indepe ndently of Clock or
Data inputs by a LOW voltage level on the MR
device is useful for a pplic ations where the true outpu t only
is required and the Clock and Master Reset are common to
all storage elements.

) inputs load and reset

input. The

Features

■ Eight edge-triggered D-typ e flip-fl o ps

■ Buffered common clock

■ Buffered, asynchronous Master Reset

■ See ABT377 for clock enable version

■ See ABT373 for transparent latch version

■ See ABT374 for 3-STATE version

■ Output sink capability of 64 mA, source capability of

32 mA

■ Guaranteed latchup protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

■ Disable time less than ena ble time to avoi d bus conten-

tion

Ordering Code:

Order Number Package Number Package Description

74ABT273CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT273CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering co de.

Connection Diagram Pin Descriptions

Pin Names Description

D

0–D7

MR
CP Clock Pulse Input (Active Rising Edge)
Q

0–Q7

Data Inputs
Master Reset (Active LOW)

Data Outputs

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Truth Table

74ABT273

Operating Mode Inputs Output

MR

CP D

Q

n

n

Reset (Clear) L X X L
Load “1” H
Load “0” H

H = HIGH Voltage Level stead y stat e
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L = LOW Voltage Level steady sta te
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X = Immaterial



= LOW-to-HIGH clock transition



hH



lL

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1) Recommended Operating

Storage Temperature −65°C to +150°C
Ambient Temperature under Bias −55°C to +125°C
Junction Temperature under Bias −55°C to +150°C
V

Pin Potential to Ground Pin −0.5V to +7.0V

CC

Input Voltage (Note 2) −0.5V to +7.0V
Input Current (Note 2) −30 mA to +5.0 mA
Voltage Applied to Any Output

in the Disabled or
Power-Off State −0.5V to +4.75V
in the HIGH State −0.5V to V

Current Applied to Output

in LOW State (Max) twice the rated I

OL

DC Latchup Source Current −500 mA

(Across Comm Operating Range)

Over Voltage Latchup V

CC

Conditions

Free Air Ambient Temperature −40°C to +85°C
Supply Voltage +4.5V to +5.5V
Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns
Enable Input 20 mV/ns

CC

(mA)

Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired . Functional operation
under these conditions is not implied.

Note 2: Either voltage lim it or c urrent limit is sufficient to protect inputs.

+ 4.5V

DC Electrical Characteristics

74ABT273

Symbol Parameter Min Typ Max Units

V

IH

V

IL

V

CD

V

OH

V

OL

I

IH

I

BVI

I

IL

V

ID

I

OS

I

CEX

I

CCH

I

CCL

I

CCT

I

CCD

Note 3: Guaranteed but not tested.
Note 4: For 8 bits toggling, I

Input HIGH Voltage 2.0 V Recognized HIGH Signal
Input LOW Voltage 0.8 V Recognized LOW Signal
Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA
Output HIGH Voltage 2.5

Output LOW Voltage 0.55 V Min IOL = 64 mA
Input HIGH Current 1

Input HIGH Current
Breakdown Test
Input LOW Current −1

Input Leakage Test 4.75 V 0.0 IID = 1.9 µA

Output Short-Circuit Current −100 −275 mA Max V
Output HIGH Leakage Current 50 µAMaxV
Power Supply Current 50 µA Max All Outputs HIGH
Power Supply Current 30 mA Max All Outputs LOW
Maximum ICC/Input Outputs Enabled 1.5 mA Max VI = VCC − 2.1V

Dynamic I

CC

No Load 0.3 mA/

< 0.5 mA/MHz.

CCD

2.0 IOH = −32 mA

1V

7 µAMaxVIN = 7.0V

−1V

V

CC

VMin

µAMax

µAMax

MHz One Bit Toggling, 50% Duty Cycle

Max

Conditions

IOH = −3 mA

VIN = 2.7V (Note 3)

= V

IN

CC

VIN = 0.5V (Note 3)

= 0.0V

IN

All Other Pins Grounded

= 0.0V

OUT

= V

OUT

CC

Data Input VI = VCC − 2.1V
All Others at VCC or GND
Outputs Open (Note 4)

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