Fairchild NC7WBD3125 service manual
NC7WBD3125
2-Bit Low Power Bus Switch with Level Shifting
NC7WBD3125 2-Bit Low Power Bus Switch with Level Shifting
May 2000
Revised December 2005
General Description
The NC7WBD3125 is a 2-bit ultra high-speed CMOS FET bus
switch with enhanced level shifting circuitry and with TTL-compatible active LOW control inputs. The low On Resistance of the
switch allows inputs to be connected to outputs with minimal
propagation delay and without generating additional ground
bounce noise. The device is organized as a 2-bit switch with
independent bus enable (OE
switch is ON and Port A is connected to Port B. When OE
HIGH, the switch is OPEN and a high-impedance state exists
between the two ports. Reduced voltage drive to the gate of the
FET switch permits nominal level shifting of 5V to 3V through
the switch. Control inputs tolerate voltages up to 5.5V independent of V
CC
.
) controls. When OE is LOW, the
is
Features
O
Space saving US8 surface mount package
O
MicroPak¥ Pb-Free leadless package
O
Typical 3: switch resistance at 5.0V VCC, VIN 0V
O
Level shift facilitates 5V to 3.3V interfacing
O
Minimal propagation delay through the switch
O
Power down high impedance input/output
O
Zero bounce in flow through mode
O
TTL compatible active LOW control inputs
O
Control inputs are overvoltage tolerant
O
Bus switch replacement for x125 logic part
Ordering Code:
Package
Package Description Supplied AsOrder Package Code
Number Number Top Mark
NC7WBD3125K8X MAB08A WB5D 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
NC7WBD3125L8X
(Preliminary)
Pb-Free package per JEDEC J-STD-020B.
MAC08A T9 Pb-Free 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and Reel
MicroPak¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation DS500374 www.fairchildsemi.com
Logic Diagram
NC7WBD3125
Connection Diagrams
Pin Assignments for US8
Pin Descriptions
Pin Name Description
A Bus A Switch I/O
B Bus B Switch I/O
OE
Function Table
Bus Enable Input
(OE
)
L B Connected to A
H Disconnected
H HIGH Logic Level
L LOW Logic Level
Bus Enable Input
Function
(Top View)
Pin One Orientation Diagra m
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top product
code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
(Top Through View)
www.fairchildsemi.com 2
NC7WBD3125
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Switch Voltage (V
DC Output Voltage (V
)
S
) (Note 2)
IN
DC Input Diode Current
) VIN 0V
(I
IK
DC Output (I
or Ground Current
DC V
CC
(I
CC/IGND
Storage Temperature Range (T
) Current 128 mA
OUT
)
STG
Junction Temperature under Bias (T
Lead Temperature (T
)
L
(Soldering, 10 Seconds)
Power Dissipation (P
) @ 85qC 250 mW
D
)
)
J
0.5V to 7.0V
0.5V to 7.0V
0.5V to 7.0V
65q
C to 150qC
50 mA
r
100 mA
150qC
260qC
Recommended Operating
Conditions
Supply Operating (V
Control Input Voltage (V
Switch Input Voltage (V
Switch Output Voltage (V
Operating T emperature (T
Input Rise and Fall Time (t
Control Input 0 ns/V to 5 ns/V
Switch I/O 0 ns/V to DC
Thermal Resistance (
Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety
of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not
guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if the input
and output diode current ratings are observed.
Note 3: Unused logic inputs must be held HIGH or LOW. They may not float.
(Note 3)
) 4.5V to 5.5V
CC
)0V to 5.5V
IN
)0V to 5.5V
IN
)0V to 5.5V
OUT
)
A
, tf)
r
T
) 250qC/W
JA
DC Electrical Characteristics
V
Symbol Parameter
V
IK
V
IH
V
IL
V
OH
I
IN
I
OFF
R
ON
I
CC
'
I
CC
Note 4: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the
voltages on the two (A or B) pins.
Note 5: Per TTL driven input (VIN 3.4V, control input only). A and B pins do not contribute to ICC.
Clamp Diode Voltage 4.5
HIGH Level Input Voltage 4.5 to 5.5 2.0 V
LOW Level Input Voltage 4.5 to 5.5 0.8 V
HIGH Level Output Voltage 4.5 to 5.5 See Figure 3 V VIN V
Input Leakage Current 5.5
Power OFF Leakage Current 5.5
Switch On Resistance 4.5 3.0 7.0
(Note 4) 4.5 3.0 7.0 VIN 0V, IIN 30 mA
Quiescent Supply Current 5.5 VIN VCC or GND, I
Increase in ICC per Input
(Note 5) Other OE V
CC
(V) Min Typ Max
4.5 15.0 50.0 V
5.5 1.0 2.5 mA
TA 40qC to 85qC
1.2 V IIN 18 mA
r
1.0
r
1.0
1.1 1.5 mA OE1 OE2 GND
10.0
Units Conditions
P
A0 d VIN d 5.5V
P
A0 d A, B d V
:
P
AOE
CC
VIN 0V, IIN 64 mA
VIN 3.4V, One OE Input only,
CC
2.4V, IIN 15 mA
IN
OE2 V
1
CC
CC
40q
OUT
C to 85qC
0
3 www.fairchildsemi.com
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