Features at +2.7V
•80µA supply current per channel
• 1.2MHz gain bandwidth product
• Output voltage range: 0.01V to 2.69V
• Input voltage range: -0.25V to +1.5V
• 1.5V/µs slew rate
• LMV321 directly replaces other industry standard LMV321
amplifiers; available in SC70-5 and SOT23-5 packages
• LMV358 directly replaces other industry standard LMV358
amplifiers; available in MSOP-8 and SOIC-8 packages
• LMV324 directly replaces other industry standard LMV324
amplifiers; available in TSSOP-14 and SOIC-14 packages
• Fully specified at +2.7V and +5V supplies
• Operating temperature range: -40°C to +125°C
Applications
• Low cost general purpose applications
• Cellular phones
• Personal data assistants
• A/D buffer
• DSP interface
• Smart card readers
• Portable test instruments
• Keyless entry
• Infrared receivers for remote controls
•Telephone systems
• Audio applications
• Digital still cameras
• Hard disk drives
• MP3 players
Description
The LMV321 (single), LMV358 (dual), and LMV324 (quad)
are a low cost, voltage feedback amplifiers that consume only
80µA of supply current per amplifier. The LMV3XX family
is designed to operate from 2.7V (±1.35V) to 5.5V (±2.75V)
supplies. The common mode voltage range extends below the
negative rail and the output provides rail-to-rail performance.
The LMV3XX family is designed on a CMOS process and
provides 1.2MHz of bandwidth and 1.5V/µs of slew rate at a
low supply voltage of 2.7V. The combination of low power,
rail-to-rail performance, low voltage operation, and tiny package options make the LMV3XX family well suited for use in
personal electronics equipment such as cellular handsets,
pagers, PDAs, and other battery powered applications.
LMV321, LMV358, LMV324
General Purpose, Low Voltage, Rail-to-Rail Output Amplifiers
www.fairchildsemi.com
Rev. 1 November 2002
Typical Application
查询LMV321AP5NL供应商
Frequency Response vs. C
CL = 200pF
= 0
R
s
CL = 50pF
= 0
R
s
CL = 20pF
R
s
+
R
10kΩ
Frequency (MHz)
s
0.1
C
2kΩ
L
Magnitude (1dB/div)
10kΩ
0.01
= 0
L
CL = 200pF
R
CL = 100pF
R
CL = 10pF
R
1
= 225Ω
s
= 0
s
= 0
s
CL = 2pF
= 0
R
s
10
+In
R
g
+V
s
+
LMV3XX
-
6.8µF
+
0.01µF
R
f
Out
DATA SHEET LMV321/LMV358/LMV324
2 Rev. 1 November 2002
LMV321
SC70-5
LMV358
MSOP-8
SOIC-8
LMV324
TSSOP-14
SOT23-5
Pin Assignments
SOIC-14
+In
-V
s
-In
Out1
-In1
+In1
-V
s
1
2
3
1
2
3
4
+
–
-
+
+V
5
4
8
7
6
-
+
5
s
Out
+V
s
Out2
-In2
+In2
Out1
-In1
+In1
+In
-V
-In
-V
1
+
2
s
–
3
1
2
-
+
3
4
s
-
+
+V
5
4
8
7
6
5
s
Out
+V
s
Out2
-In2
+In2
Out1
-In1
+In1
+V
s
+In2
-In2
Out2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Out4
-In4
+In4
-V
s
+In3
-In3
Out3
Out1
-In1
+In1
+V
+In2
-In2
Out2
1
2
3
4
s
5
6
7
14
13
12
11
10
9
8
Out4
-In4
+In4
-V
s
+In3
-In3
Out3
LMV321/LMV358/LMV324 DATA SHEET
Rev. 1 November 2002 3
Absolute Maximum Ratings
Parameter Min. Max. Unit
Supply Voltages 0+6V
Maximum Junction Temperature – +175 °C
Storage Temperature Range -65 +150 °C
Lead Temperature, 10 seconds – +260 °C
Input Voltage Range -
Vs-0.5 +Vs+0.5
V
Electrical Specifications
(Tc= 25°C, Vs= +2.7V, G = 2, RL= 10kΩ to Vs/2, Rf= 10kΩ, V
o (DC)
= Vcc/2; unless otherwise noted)
Parameter Conditions Min. Typ. Max. Unit
AC Performance
Gain Bandwidth Product CL= 50pF,RL=2kΩ to Vs/2 1.2 MHz
Phase Margin 52 deg
Gain Margin 17 dB
Slew Rate Vo= 1V
pp
1.5 V/µs
Input Voltage Noise >50kHz 36 nV/√Hz
Crosstalk: LMV358 100kHz 91 dB
LMV324 100kHz 80 dB
DC Performance
Input Offset Voltage
1
1.7 7 mV
Average Drift 8 µV/°C
Input Bias Current
2
<1 nA
Input Offset Current
2
<1 nA
Power Supply Rejection Ratio
1
DC 50 65 dB
Supply Current (Per Channel)
1
80 120 µA
Input Characteristics
Input Common Mode Voltage Range1LO 0 -0.25 V
HI 1.5 1.3 V
Common Mode Rejection Ratio
1
50 70 dB
Output Characteristics
Output Voltage Swing RL= 10kΩ to Vs/2; LO
1
0.1 0.01 V
RL= 10kΩ to Vs/2; HI
1
2.69 2.6 V
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes:
1. Guaranteed by testing or statistical analysis at +25°C.
2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
Recommended Operating Conditions
Parameter Min. Max. Unit
Operating Temperature Range -40 +125 °C
Power Supply Operating Range 2.5 5.5 V
DATA SHEET LMV321/LMV358/LMV324
4 Rev. 1 November 2002
Electrical Specifications
(Tc= 25°C, Vs= +5V, G = 2, RL= 10kΩ to Vs/2, Rf= 10kΩ, V
o (DC)
= Vcc/2; unless otherwise noted)
Parameter Conditions Min. Typ. Max. Unit
AC Performance
Gain Bandwidth Product CL= 50pF,RL=2kΩ to Vs/2 1.4 MHz
Phase Margin 73 deg
Gain Margin 12 dB
Slew Rate 1.5 V/µs
Input Voltage Noise >50kHz 33 nV/√Hz
Crosstalk: LMV358 100kHz 91 dB
LMV324 100kHz 80 dB
DC Performance
Input Offset Voltage
1
17mV
Average Drift 6 µV/°C
Input Bias Current
2
<1 nA
Input Offset Current
2
<1 nA
Power Supply Rejection Ratio
1
DC 50 65 dB
Open Loop Gain
1
50 70 dB
Supply Current (Per Channel)
1
100 150 µA
Input Characteristics
Input Common Mode Voltage Range1LO 0 -0.4 V
HI 3.8 3.6 V
Common Mode Rejection Ratio
1
50 75 dB
Output Characteristics
Output Voltage Swing RL= 2kΩ to Vs/2; LO/HI 0.036 to 4.95 V
RL= 10kΩ to Vs/2; LO
1
0.1 0.013 V
RL= 10kΩ to Vs/2; HI
1
4.98 4.9 V
Short Circuit Output Current
1
sourcing; Vo= 0V 5 +34 mA
sinking; Vo= 5V 10 -23 mA
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes:
1. Guaranteed by testing or statistical analysis at +25°C.
2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
Package Thermal Resistance
Package θ
JA
5 lead SC70 331.4°C/W
5 lead SOT23 256°C/W
8 lead SOIC 152°C/W
8 lead MSOP 206°C/W
14 lead TSSOP 100°C/W
14 lead SOIC 88°C/W
LMV321/LMV358/LMV324 DATA SHEET
Rev. 1 November 2002 5
Typical Operating Characteristics
(Tc= 25°C, Vs= +5V, G = 2, RL= 10kΩ to Vs/2, Rf= 10kΩ, V
o (DC)
= Vcc/2; unless otherwise noted)
Non-Inverting Freq. Response Vs = +5V
G = 2
G = 10
G = 5
G = 1
Normalized Magnitude (1dB/div)
0.01
0.1
1
Frequency (MHz)
Non-Inverting Freq. Response Vs = +2.7V
G = 1
G = 2
G = 10
G = 5
Normalized Magnitude (1dB/div)
0.01
0.1
1
Frequency (MHz)
Inverting Frequency Response Vs = +5V
G = -2
G = -1
G = -10
G = -5
Normalized Magnitude (1dB/div)
10
0.01
0.1
1
10
Frequency (MHz)
Inverting Freq. Response Vs = +2.7V
G = -1
G = -2
G = -10
G = -5
Normalized Magnitude (1dB/div)
10
0.01
0.1
1
10
Frequency (MHz)
Frequency Response vs. C
CL = 200pF
= 0
R
s
CL = 50pF
= 0
R
s
CL = 20pF
= 0
R
s
+
R
Magnitude (1dB/div)
10kΩ
0.01
s
10kΩ
0.1
C
2kΩ
L
1
Frequency (MHz)
Small Signal Pulse Response
0.25
0.2
0.15
0.1
Output (V)
0.05
0
-0.05
02024681012141618
Time (µs)
L
CL = 200pF
= 225Ω
R
s
CL = 100pF
= 0
R
s
CL = 10pF
= 0
R
s
CL = 2pF
= 0
R
s
Frequency Response vs. R
RL = 1kΩ
RL = 10kΩ
Magnitude (1dB/div)
10
0.01
RL = 2kΩ
0.1
L
RL = 100kΩ
1
10
Frequency (MHz)
Large Signal Pulse Response
2.5
2
1.5
0.1
Output (V)
0.5
0
-0.5
02024681012141618
Time (µs)
DATA SHEET LMV321/LMV358/LMV324
6 Rev. 1 November 2002
Typical Operating Characteristics
(Tc= 25°C, Vs= +5V, G = 2, RL= 10kΩ to Vs/2, Rf= 10kΩ, V
o (DC)
= Vcc/2; unless otherwise noted)
Input Voltage Noise
100
80
70
60
50
nV/√Hz
40
30
20
1
10
100
Frequency (kHz)
Open Loop Gain & Phase vs. Frequency
0
-45
-90
-135
-180
-225
Open Loop Phase (deg)
-270
10
100
Phase
|Gain|
100k10k1k
Frequency (Hz)
RL = 2kΩ
CL = 50pF
1M
1000
100
Open Loop Gain (dB)
80
60
40
20
0
-20
10M
Total Harmonic Distortion
0.6
Vo = 1V
0.5
0.4
0.3
THD (%)
0.2
0.1
0
0.1
pp
1
Frequency (kHz)
10
100
LMV321/LMV358/LMV324 DATA SHEET
Rev. 1 November 2002 7
Application Information
General Description
The LMV3XX family are single supply, general purpose,
voltage-feedback amplifiers that are pin-for-pin compatible
and drop in replacements with other industry standard
LMV321, LMV358, and LMV324 amplifiers. The LMV3XX
family is fabricated on a CMOS process, features a rail-to-rail
output, and is unity gain stable.
The typical non-inverting circuit schematic is shown in
Figure 1.
Figure 1: Typical Non-inverting configuration
Power Dissipation
The maximum internal power dissipation allowed is directly
related to the maximum junction temperature. If the maximum
junction temperature exceeds 150°C, some performance
degradation will occur. If the maximum junction temperature
exceeds 175°C for an extended time, device failure may occur.
Driving Capacitive Loads
The Frequency Response vs CLplot on page 4, illustrates the
response of the LMV3XX family. A small series resistance (Rs)
at the output of the amplifier, illustrated in Figure 2, will improve
stability and settling performance. R
s
values in the Frequency
Response vs CLplot were chosen to achieve maximum band-
width with less than 1dB of peaking. For maximum flatness,
use a larger Rs. As the plot indicates, the LMV3XX family
can easily drive a 200pF capacitive load without a series
resistance. For comparison, the plot also shows the LMV321
driving a 200pF load with a 225Ω series resistance.
Driving a capacitive load introduces phase-lag into the output
signal, which reduces phase margin in the amplifier. The
unity gain follower is the most sensitive configuration. In a
unity gain follower configuration, the LMV3XX family
requires a 450Ω series resistor to drive a 200pF load. The
response is illustrated in Figure 3.
Figure 2: Typical Topology for driving a
capacitive load
Figure 3: Frequency Response vs CLfor unity
gain configuration
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance. Fairchild has evaluation boards to
use as a guide for high frequency layout and as aid in device
testing and characterization. Follow the steps below as a
basis for high frequency layout:
• Include 6.8µF and 0.01µF ceramic capacitors
• Place the 6.8µF capacitor within 0.75 inches of
the power pin
• Place the 0.01µF capacitor within 0.1 inches of
the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts shown in Figure 5 on
page 8 for more information.
+
LMV3XX
10kΩ
10kΩ
R
s
C
2kΩ
L
+V
s
6.8µF
+
+In
0.01µF
+
LMV3XX
Out
R
f
R
g
3
2
1
0
-1
-2
-3
-4
-5
Magnitude (dB)
-6
-7
-8
-9
0.01 0.1 1 10
CL = 50pF
Rs = 0
CL = 100pF
Rs = 400Ω
CL = 200pF
Rs = 450Ω
Frequency (MHz)
DATA SHEET LMV321/LMV358/LMV324
8 Rev. 1 November 2002
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of this device:
Evaluation board schematics and layouts are shown in Figures
4 and 5.
Eval Bd Description Products
KEB013 Single Channel, Dual Supply, LMV321AS5X
SOT23-5 for buffer-style pinout
KEB014 Single Channel, Dual Supply, LMV321AP5X
SC70-5 for buffer-style pinout
KEB006 Dual Channel, Dual Supply, LMV358AM8X
8 lead SOIC
KEB010 Dual Channel, Dual Supply, LMV358AMU8X
8 lead MSOP
KEB012 Quad Channel, Dual Supply, LMV324AMTC14X
14 lead TSSOP
KEB018 Quad Channel, Dual Supply, LMV324AM14X
14 lead SOIC
Evaluation Board Schematic Diagrams
Figure 4a: LMV321 KEB013 schematic Figure 4b: LMV321 KEB014 schematic
LMV321/LMV358/LMV324 DATA SHEET
Rev. 1 November 2002 9
Evaluation Board Schematic Diagrams (Continued)
Figure 4c: LMV358 KEB006/KEB010 schematic
Figure 4d: LMV324 KEB012/KEB018 schematic
DATA SHEET LMV321/LMV358/LMV324
10 Rev. 1 November 2002
Figure 5a: KEB013 (top side) Figure 5b: KEB013 (bottom side)
Figure 5c: KEB014 (top side) Figure 5d: KEB014 (bottom side)
LMV321 Evaluation Board Layout
LMV321/LMV358/LMV324 DATA SHEET
Rev. 1 November 2002 11
Figure 5g: KEB010 (top side) Figure 5h: KEB010 (bottom side)
LMV358 Evaluation Board Layout
Figure 5e: KEB006 (top side) Figure 5f: KEB006 (bottom side)
DATA SHEET LMV321/LMV358/LMV324
12 Rev. 1 November 2002
LMV324 Evaluation Board Layout
Figure 5i: KEB012 (top side) Figure 5j: KEB012 (bottom side)
Figure 5k: KEB018 (top side) Figure 5l: KEB018 (bottom side)
LMV321/LMV358/LMV324 DATA SHEET
Rev. 1 November 2002 13
LMV321 Package Dimensions
b
e
e1
D
C
L
E
C
L
C
L
A
A2
A1
α
E1
C
2
DATUM ’A’
C
L
NOTE:
1. All dimensions are in millimeters.
2 Foot length measured reference to flat
foot surface parallel to DATUM ’A’ and lead surface.
3. Package outline exclusive of mold flash & metal burr.
4. Package outline inclusive of solder plating.
5. Comply to EIAJ SC74A.
6. Package ST 0003 REV A supercedes SOT-D-2005 REV C.
SYMBOL MIN MAX
A 0.90 1.45
A1 0.00 0.15
A2 0.90 1.30
b 0.25 0.50
C 0.09 0.20
D 2.80 3.10
E 2.60 3.00
E1 1.50 1.75
L 0.35 0.55
e 0.95 ref
e1 1.90 ref
α 010
SOT23-5
SC70
C
L
b
C
L
A
A2
e
HE
D
C
L
A1
C
L
Q1
NOTE:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold flashing and metal burr.
4. All speccifications comply to EIAJ SC70.
L
SYMBOL MIN MAX
e 0.65 BSC
D1.802.20
E
C
b0.150.30
E1.151.35
HE 1.80 2.40
Q1 0.10 0.40
A2 0.80 1.00
A1 0.00 0.10
A 0.80 1.10
c 0.10 0.18
L 1.10 0.30
DATA SHEET LMV321/LMV358/LMV324
14 Rev. 1 November 2002
LMV358 Package Dimensions
HE
C
L
ZD
C
L
e
D
Pin No. 1
B
A
A1
A2
7°
L
DETAIL-A
DETAIL-A
C
h x 45°
α
NOTE:
1. All dimensions are in millimeters.
2. Lead coplanarity should be 0 to 0.10mm (.004") max.
3. Package surface finishing:
(2.1) Top: matte (charmilles #18~30).
(2.2) All sides: matte (charmilles #18~30).
(2.3) Bottom: smooth or matte (charmilles #18~30).
4. All dimensions excluding mold flashes and end flash
from the package body shall not exceed o.152mm (.006)
per side(d).
SYMBOL MIN MAX
A1 0.10 0.25
B 0.36 0.46
C 0.19 0.25
D 4.80 4.98
E 3.81 3.99
e 1.27 BSC
H 5.80 6.20
h 0.25 0.50
L 0.41 1.27
A 1.52 1.72
0
ZD 0.53 ref
A2 1.37 1.57
8
SOIC-8
SOIC
eS
E/2 2X
E3
E4
12
ccc
ABC
– B –
2
37
2
64
D2
A2
A
A1
– A –
– C –
bbb
AB
C
M
b
D
43
aaa
A
E1
– H –
t1
t2
Gauge
Plane
0.25mm
R1
R
L
L1
03
02
01
Detail A
Scale 40:1
Section A - A
b
cc1
b1
E2
E1
E
Detail A
5
A
A
SYMBOL MIN MAX
A 1.10
A1 0.10 ±0.05
A2 0.86 ±0.08
D 3.00 ±0.10
D2 2.95 ±0.10
E 4.90 ±0.15
E1 3.00 ±0.10
E2 2.95 ±0.10
E3 0.51 ±0.13
E4 0.51 ±0.13
R 0.15 +0.15/-0.06
R1 0.15 +0.15/-0.06
t1 0.31 ±0.08
t2 0.41 ±0.08
b 0.33 +0.07/-0.08
b1 0.30 ±0.05
c 0.18 ±0.05
c1 0.15 +0.03/-0.02
01 3.0°±3.0°
02 12.0°±3.0°
03 12.0°±3.0°
L 0.55 ±0.15
L1 0.95 BSC –
aaa 0.10 –
bbb 0.08 –
ccc 0.25 –
e 0.65 BSC –
S 0.525 BSC –
MSOP-8
–
NOTE:
1All dimensions are in millimeters (angle in degrees), unless otherwise specified.
2 Datums – B – and – C – to be determined at datum plane – H – .
3 Dimensions "D" and "E1" are to be determined at datum – H – .
4 Dimensions "D2" and "E2" are for top package and dimensions "D" and "E1" are for bottom package.
5 Cross sections A – A to be determined at 0.13 to 0.25mm from the leadtip.
6 Dimension "D" and "D2" does not include mold flash, protrusion or gate burrs.
7 Dimension "E1" and "E2" does not include interlead flash or protrusion.
MSOP
LMV321/LMV358/LMV324 DATA SHEET
Rev. 1 November 2002 15
E/22X
ddd C B A
6
6
1.0
1.0
123
9
e /2
E1 E
e
N
8
– B –
7
2X
N/2 TIPS
1.0 DIA
– A –
7
– C –
aaa C
ccc
8 3
D
CBAbbb
M
b NX
A1
A2
A
c1
c
(b)
b1
5
SECTION AA
10
A
A
– H –
GAGE
PLANE
0.25
(0.20)
(02)
R1
R
01
(L1)
L
(03)
NOTES:
1 All dimensions are in millimeters (angle in degrees).
2 Dimensioning and tolerancing per ASME Y14.5–1994.
3 Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side .
4 Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side.
5 Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum
material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm
for 0.5mm pitch packages.
6 Te rminal numbers are shown for reference only.
7 Datums – A – and – B – to be determined at datum plane – H – .
8 Dimensions "D" and "E1" to be determined at datum plane – H – .
9 This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center"
lead must be coincident with the package centerline, Datum A.
10
Cross sections A – A to be determined at 0.10 to 0.25mm from the leadtip.
SYMBOL MIN NOM MAX
A – – 1.10
A1 0.05 – 0.15
A2 0.85 0.90 0.95
L 0.50 0.60 0.75
R 0.09 – –
R1 0.09 – –
b 0.19 – 0.30
b1 0.19 0.22 0.25
c 0.09 – 0.20
c1 0.09 – 0.16
01 0° – 8°
L1 1.0 REF
aaa 0.10
bbb 0.10
ccc 0.05
ddd 0.20
e 0.65 BSC
02 12° REF
03 12° REF
TSSOP-14
D 4.90 5.00 5.10
E1 4.30 4.40 4.50
E 6.4 BSC
e 0.65 BSC
N 14
TSSOP
LMV324 Package Dimensions
SOIC
D
e
C
L
ZD
7°
HE
DETAIL-A
h x 45°
α
L
DETAIL-A
C
C
L
B
A2
Pin No. 1
A1
A
SYMBOL MIN MAX
A1 .0040 .0098
B .014 .018
C .0075 .0098
D .337 .344
E .150 .157
e .050 BSC
H .2284 .2440
h .0099 .0196
L .016 .050
A .060 .068
0
ZD 0.20 ref
A2 .054 .062
NOTE:
1. All dimensions are in inches.
2. Lead coplanarity should be 0 to 0.10mm (.004") max.
3. Package surface finishing:
(2.1) Top: matte (charmilles #18~30).
(2.2) All sides: matte (charmilles #18~30).
(2.3) Bottom: smooth or matte (charmilles #18~30).
4. All dimensions excluding mold flashes and end flash
from the package body shall not exceed o.152mm (.006)
per side (d).
SOIC-14
8
www.fairchildsemi.com © 2002 Fairchild Semiconductor Corporation
Ordering Information
Model Part Number Package Container Pack Qty
LMV321 LMV321AP5X SC70-5 Reel 3000
LMV321 LMV321AS5X SOT23-5 Reel 3000
LMV358 LMV358AM8X SOIC-8 Reel 2500
LMV358 LMV358AMU8X MSOP-8 Reel 3000
LMV324 LMV324AMTC14X TSSOP Reel 2500
LMV324 LMV324AM14X SOIC Reel 2500
Temperature range for all parts: -40°C to +125°C.
DATA SHEET LMV321/LMV358/LMV324
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN.
FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE
PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for
surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support device or system whose failure
to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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