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HUF75343G3, HUF75343P3, HUF75343S3,
HUF75343S3S
Data Sheet March 2003
75A, 55V, 0.009 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel pow er MOSFETs
are manufactured using the
innovat ive Ul traFET® pr ocess . This
advanced process technology
achieves the lowest possible onresistance per silicon area, resulting in outstanding
performance. This device is capable of w ithstanding high
energy in the avalanche mode and the diode exhibits very
low reverse recovery time and stored charge. It was
designed for use in applications where power efficiency is
important, such as switching regulators, switching
converters, motor drivers, relay drivers, low -voltage bus
switches, and power management in portable and battery
operated products .
Formerly developmental type TA75343.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75343G3 TO-247 75343G
HUF75343P3 TO-220AB 75343P
HUF75343S3 TO-262AA 75343S
HUF75343S3S TO-263AB 75343S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75343S3ST.
Features
• 75A, 55V
• Simulation Models
- Temperature Compensating PSPICE® and SABER™
Models
- Thermal Impedance PSPICE™ and SABER Models
Available on the WEB at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
Packaging
JEDEC STYLE TO-247 JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(TAB)
JEDEC TO-263AB JEDEC TO-262AA
GATE
SOURCE
Product reliabil it y information can be found at http ://www.fairchildsem i.com/products/di s crete/reliability/index.html
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 qualit y systems certification.
DRAIN
(FLANGE)
For severe environments, see our Automotive HUFA series.
DRAIN
(FLANGE)
SOURCE
DRAIN
(FLANGE)
DRAIN
GATE
SOURCE
DRAIN
GATE
©2003 Fairchild Semiconductor Corporation HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
DGR
GS
55 V
55 V
±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
DM
AS
D
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .T
, T
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
75
Figure 4
Figure 6
270
1.81
-55 to 175
300
260
A
W
W/oC
o
C
o
C
o
C
NOTE:
1. T
= 25oC to 150oC.
J
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV
Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
DSSID
DSS
GSS
= 250µA, VGS = 0V (Figure 11) 55 - - V
VDS = 50V, VGS = 0V - - 1 µA
= 45V, VGS = 0V, TC = 150oC--250µA
V
DS
VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V
Drain to Source On Resistance r
GS(TH)VGS
DS(ON)ID
= VDS, ID = 250µA (Figure 10) 2 - 4 V
= 75A, VGS = 10V (Figure 9) - 0.007 0.009 Ω
THERMAL SPECI FICATIONS
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R
SWITCHING SPECIFICATIONS (V
GS
= 10V)
Turn-On Time t
Turn-On Delay Time t
d(ON)
Rise Time t
Turn-Off Delay Time t
d(OFF)
Fall Time t
Turn-Off Time t
θJC
θJA
ON
r
f
OFF
(Figure 3) - - 0.55
TO-247 - - 30
TO-220, TO-263 - - 62
VDD = 30V, ID ≅ 75A,
= 0.4Ω, VGS = 10V,
R
L
= 2.5Ω
R
GS
--125ns
-9-ns
-75- ns
-32- ns
-18- ns
- - 75 ns
o
C/W
o
C/W
o
C/W
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q
Gate Charge at 10V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Gate to Drain “Miller” Charge Q
g(TOT)VGS
g(10)
g(TH)
gs
gd
= 0V to 20V VDD = 30V,
≅ 75A,
I
VGS = 0V to 10V - 92 110 nC
VGS = 0V to 2V - 6.0 7.2 nC
D
R
= 0.4Ω
L
I
g(REF)
= 1.0mA
(Figure 13)
- 170 205 nC
-13-nC
-42-nC
©2003 Fairchild Semiconductor Corporation HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1
HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
CAPACITANCE SPECIFICATIONS
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q
Typical Performance Curves
1.2
1.0
0.8
ISS
OSS
RSS
SD
rr
RR
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
- 3000 - pF
- 1100 - pF
- 230 - pF
ISD = 75A - - 1.25 V
ISD = 75A, dISD/dt = 100A/µs - - 100 ns
ISD = 75A, dISD/dt = 100A/µs - - 200 nC
80
60
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
TC, CASE TEMPERATURE (oC)
125 175
FIGURE 1. NORMALIZED POWER DISSIP ATION vs CASE
TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
0.1
, NORMALIZED
JC
θ
Z
THERMAL IMPEDANCE
0.01
-5
10
SINGLE PULSE
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
40
20
, DRAIN CURRENT (A)
D
I
0
25
50 75 100 125 150 175
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
P
DM
NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-2
10
-1
10
1/t2
x R
θ
JC
0
10
t
1
t
2
+ T
θ
JC
C
1
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2003 Fairchild Semiconductor Corporation HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Rev. B1