Fairchild HUF75332G3, HUF75332P3, HUF75332S3S service manual

HUF75332G3, HUF75332P3, HUF75332S3S
Data Sheet January 2005
60A, 55V, 0.019 Ohm, N-Channel UltraFET Power MOSFETs
These N-Channel pow er MOSFETs are manufactured using the innovat ive Ul traFET® pr ocess . This
advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outsta ndi ng p erformance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switch in g regul ators, switching converters, motor drivers, relay drivers, low­voltage bus switches, and power management in portable and battery-operated products.
Formerly developmental type TA75332.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75332G3 TO-247 75332G HUF75332P3 TO-220AB 75332P HUF75332S3S TO-263AB 75332S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75332S3ST.
Features
• 60A, 55V
• Simulation Models
- Temperature Com pen sated PSPI CE®
and SABER™
Models
- SPICE and SABER Thermal Impedance Models Available on the WEB at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount Components to PC Boards”
Symbol
D
G
S
Packaging
JEDEC STYLE TO-247 JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (TAB)
JEDEC TO-263AB
GATE
SOURCE
Product reliability information can be found at ht tp://www.fairchilds e m i.com/products/dis crete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 qualit y systems certification.
DRAIN
(FLANGE)
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
©2005 Fairchild Semiconductor Corporation HUF75332G3, HUF75332P3, HUF75332S3S Rev. B1
HUF75332G3, HUF75332P 3, HU F7 53 32S3S
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
DGR
GS
55 V 55 V
±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
DM
AS
D
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .T
, T
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
60
Figure 4
Figure 6
145
0.97
-55 to 175
300 260
A
W
W/oC
o
C
o
C
o
C
NOTE:
= 25oC to 150oC.
1. T
J
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
DSSID
DSS
GSS
= 250µA, VGS = 0V (Figure 11) 55 - - V VDS = 50V, VGS = 0V - - 1 µA V
= 45V, VGS = 0V, TC = 150oC--250µA
DS
VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V Drain to Source On Resistance r
GS(TH)VGS
DS(ON)ID
= VDS, ID = 250µA (Figure 10) 2 - 4 V
= 60A, VGS = 10V (Figure 9) - 0.016 0.019
THERMAL SPECI FICATIONS
Thermal Resistance Junction to Case R Thermal Resistance Junction to Ambient R
SWITCHING SPECIFICATIONS (V
GS
= 10V) Turn-On Time t Turn-On Delay Time t
d(ON)
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Turn-Off Time t
θJC θJA
ON
r
f
OFF
(Figure 3) - - 1.03 TO-247 - - 30 TO-220, TO-263 - - 62
VDD = 30V, ID 60A,
= 0.50Ω, VGS = 10V,
R
L
= 6.8
R
GS
--130ns
-9-ns
-90- ns
-50- ns
-45- ns
--125ns
o
C/W
o
C/W
o
C/W
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q Gate Charge at 10V Q Threshold Gate Charge Q Gate to Source Gate Charge Q Reverse Transfer Capacitance Q
g(TOT)VGS
g(10)
g(TH)
gs gd
= 0V to 20V VDD = 30V,
I
60A,
VGS = 0V to 10V - 40 50 nC VGS = 0V to 2V - 2.5 3.0 nC
D
= 0.50
R
L
I
g(REF)
= 1.0mA
(Figure 13)
-7085nC
-6-nC
-15-nC
©2005 Fairchild Semiconductor Corporation HUF75332G3, HUF75332P3, HUF75332S3S Rev. B1
HUF75332G3, HUF75332P 3, HU F7 53 32S3S
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
CAPACITANCE SPECIFICATIONS
Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V Reverse Recovery Time t Reverse Recovered Charge Q
Typical Performance Curves
1.2
1.0
0.8
ISS OSS RSS
SD
rr
RR
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
- 1300 - pF
- 480 - pF
- 115 - pF
ISD = 60A - - 1.25 V ISD = 60A, dISD/dt = 100A/µs--75ns ISD = 60A, dISD/dt = 100A/µs - - 140 nC
80
60
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
TC, CASE TEMPERATURE (oC)
125 175
FIGURE 1. NORMALIZED POWER DISSIP ATION vs CASE
TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
0.1
, NORMALIZED
θJC
Z
THERMAL IMPEDANCE
0.01
-5
10
SINGLE PULSE
-4
10
-3
10
t, RECTANGULAR PULSE DURATION (s)
40
20
, DRAIN CURRENT (A)
D
I
0
25
50 75 100 125 150 175
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
P
DM
t
1
NOTES: DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-2
10
-1
10
1/t2
x R
θJC
θJC
0
10
t
2
+ T
C
1
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2005 Fairchild Semiconductor Corporation HUF75332G3, HUF75332P3, HUF75332S3S Rev. B1
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