Fairchild FSQ500L service manual

April 2012

FSQ500L Compact, Green Mode, Fairchild Power Switch (FPS™)

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Features

 Single Chip 700V SenseFET Power Switch  Precision Fixed Operating Frequency: 130kHz  No-load consumption 250mW at 265V

Burst Mode and Down to 60mW with External Bias

AC

with

 Internal Startup Switch  Soft-Start Time Tuned by External Capacitor  Under-Voltage Lockout (UVLO) with Hysteresis  Pulse-by-Pulse Current Limit  Overload Protection (OLP) and Internal Thermal

Shutdown Function (TSD) with Hysteresis

 Auto-Restart Mode  No Need for Auxiliary Bias Winding

Applications

 Cost-Effective Linear Power Supplies Replacement  Charger and Adapter for Mobile Phone, PDA, MP3,

and Cordless Phone

Related Resources

AN4137 — Design Guidelines for Off-line Flyback



Converters Using Fairchild Power Switch (FPS™)

 AN4141 — Troubleshooting and Design Tips for

Fairchild Power Switch (FPS™) Flyback Applications

 AN-4147 — Design Guidelines for RCD Snubber of

Flyback Converters

 AN-6075 — Compact Green Mode Adapter Using

FSQ500L for Low Cost

 AN-4138 — Design Considerations for Battery

Charger Using Green Mode Fairchild Power Switch (FPS™)

 Evaluation Board: FEBFSQ500L_H257v1

Description

The FSQ500L is specially designed for a replacement of linear power supplies with low cost. This device combines current-mode Pulse Width Modulator (PWM) with a senseFET. The integrated PWM controller features include: a fixed oscillator, Under Voltage Lockout (UVLO) protection, Overload Protection (OLP), Leading-Edge Blanking (LEB), an optimized gate turnon/turn-off driver, Thermal Shutdown (TSD) protection with hysteresis, and temperature-compensated precision-current sources for loop compensation. When compared to a linear power supply, the FSQ500L device reduces total size and weight, while increasing efficiency, productivity, and system reliability. This device provides a basic platform for cost-effective flyback converters.

Maximum Output Power

230VAC ± 15%

Adapter

Notes:

1. The junction temperature can limit the maximum

2. 230V

3. Typical continuous power in a non-ventilated

4. Maximum practical continuous power in an open

(3)

2.5W 3.0W 2.0W 2.5W

output power.

or 100/115VAC with doubler.

AC

enclosed adapter measured at 50°C ambient.

frame design at 50°C ambient.

(2)

85-265VAC

Open

Frame

(4)

Adapter

(1)

Open

(3)

Frame

(4)

Ordering Information

Part Number

FSQ500L -40°C to +85°C 4-Lead, Small Outline Package (SOT223-4L) Tape & Reel

Operating

Temperature Range

Package Packing Method

Application Circuit Diagram

AC

IN

Figure 1. Typical Application Circuit

FB

PWM

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

DC

OUT

D

GNDV

V

CC

Internal Block Diagram

V

3

FB

V

VSD

V

CC

BURL/VBURH

I

DELAY

CC

OLP

FB

I

(BURST MODE:IFB/2)

8R

R

Soft-Soft

OSC

S

Q

A/R

R

TSD

Figure 2. Internal Block Diagram

7.7V

S

Q

R

HV/REG OFF

V

CC

2

6.5V

HV/REG

Z

V

REF

UVLO

D

1

250ns

LEB

R

sense

(0.3V)

4

GND

Pin Assignments

Pin Definitions

GND

FSQ500L

V

CC VFBD

Figure 3. Package / Pin Diagram

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Pin # Name Description

High-voltage power senseFET drain connection. In addition, at startup, the internal high-voltage current source supplies internal bias and charges the external capacitor connected to the V

1 D

2 VCC

3 VFB

4 GND This pin is the control ground and the senseFET source.

Once V is alive until V irregularly to maintain V

This pin is connected to a storage capacitor. A high-voltage regulator connected between pin 1 (D) and this pin provides the supply voltage to the FSQ500L at startup and when switching during normal operation. The FSQ500L eliminates the need for auxiliary bias winding and associated external components.

This pin is internally connected to the non-inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 4.5V, the overload protection triggers, which shuts down the FPS.

reaches 6.0V, all internal blocks are activated. The internal high-voltage current source

CC

reaches 6.5V. After that, the internal high voltage current source turns on and off

CC

at 6.5V.

CC

pin.

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDS Drain Pin Voltage

VCC Supply Voltage 10 V

VFB Feedback Voltage Range -0.3 VCC V

PD Total Power Dissipation 0.78 W

IDM Drain Current Pulsed

TJ Operating Junction Temperature -40 Internally Limited

T

Storage Temperature -55 +150

STG

Notes:

5. LDMOS available drain voltage is -0.3V ~ 700V.

6. Repetitive rating: pulse width is limited by maximum junction temperature.

(5)

700 V

(6)

0.41 A

°C

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Thermal Impedance

Symbol Parameter Value Unit

θJA Junction-to-Ambient Thermal Resistance

Note:

7. Free-standing with no heat sink; minimum land pattern.

(7)

+160 °C/W

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Electrical Characteristics

TJ = 25°C unless otherwise specified.

Symbol Parameter Condition Min. Typ. Max. Unit

SenseFET Section

BV

Drain-Source Breakdown Voltage

DSS

I

Zero-Gate-Voltage Drain Current V

DSS

R

Drain-Source On-State Resistance

DS(ON)

C

Input Capacitance

ISS

C

Output Capacitance

OSS

t

Rise Time

r

t

Fall Time

f

(8)

V

(8)

V

VCC = 6.5V, VFB = 0V, ID = 150μA

= 6.5V, VFB = 0V, VDS = 560V 150

CC

TJ = 25°C, ID = 25mA

TJ = 100°C, ID = 25mA

= 6.5V 42 pF

GS

= 40V, fS = 1MHz 25 pF

DS

= 350V, ID = 25mA 100 ns

DS

= 350V, lD = 25mA 50 ns

DS

Control Section

fS Switching Frequency VCC = 6.5V, VFB = 1.0V 120 130 140 kHz

ΔfS

I

FB(Burst)

I

FB(Normal)

D

V

START

V

DLY_EN

Switching Frequency Variation

Feedback Source Current

V

Maximum Duty Ratio V

MAX

Minimum Duty Ratio V

MIN

UVLO Threshold Voltage

After Turn-on, V

STOP

Shutdown Delay Current Enable Voltage

(8)

-25°C < TJ < 125°C

VCC = 6.5V, VFB = 0V 98 110 122

= 6.5V 200 225 250

CC

= 6.5V, VFB = 4.0V 54 60 66 %

CC

= 6.5V, VFB = 0V 0 %

CC

VFB = 0V, VCC Sweep 5.5 6.0 6.5 V

= 0V, VCC Sweep 4.5 5.0 5.5 V

FB

V

= VSD, VCC Sweep from 6V 6.0 6.5 7.0 V

FB

Burst-Mode Section

V

BURH

V

0.70 0.75 0.80 V

Burst Mode Voltage V

BURL

= 6.5V, VFB Sweep

CC

HYS 30 50 80 mV

Protection Section

I

Peak Current Limit di/dt = 150mA/µs 245 280 315 mA

LIM

V

Shutdown Feedback Voltage V

SD

I

Shutdown Delay Current V

DELAY

t

Leading Edge Blanking Time

LEB

t

Current Limit Delay Time

CLD

TDS HYS 80

Thermal Shutdown Temperature

(8)

250 ns

(8)

100 ns

(8)

= 6.5V, VFB Sweep 4.1 4.5 4.9 V

CC

= 6.5V, VFB = 4.0V 4 5 6

CC

130 140 150

Total Device Section

I

OP-BURST

V

Operating Supply Current (Control

I

OP-FB

I

CCREG

CCREG_

TSD

Part Only)

V

Startup Charging Current V

CH

Supply Shunt Regulator V

Supply Shunt Regulator During

(8)

TSD

VCC = 6.5V, VFB = 0V 360 430 500

= 6.5V, VFB = 4V 640 760 880

CC

= VFB = 0V, VDS = 40V 3.3 mA

CC

= 40V, VFB = 0V 6.0 6.5 7.0 V

DS

5.2 5.7 6.2 V

Note:

8. These parameters, although guaranteed, are not 100% tested in production.

700 V

μA

25 29

35 41

Ω

±5 ±7 %

μA

0.75 0.80 0.85 V

μA

°C

μA

Typical Performance Characteristics

These characteristic graphs are measured at TA = 25°C.

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Oper ating Supply Current (IOP) vs Temperature

490

470

450

430

(μA)

OP

I

410

390

370

-40 - 25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

Figure 4. Operating Supply Current (I

vs. Temperature

UVLO Thres hold Voltage (V

6.5

6.3

6.1

(V)

START

5.9

V

5.7

) vs Tem pera ture

START

OP_Burst

)

Sw itching Frequenc y (fS) vs Temperature

140

135

130

(KHZ)

S

f

125

120

-40 -25 -10 5 20 3 5 50 6 5 80 95 110 125

Temperature (℃)

Figure 5. Switching Frequency (fS)

vs. Temperature

(V)

STOP

V

UVLO Thre shold Voltage (V

5.5

5.3

5.1

4.9

4.7

) vs Temperature

STOP

5.5

-40 -25 -10 5 20 35 50 65 80 95 110 125

Tem peratur e (℃)

Figure 6. UVLO Threshold Voltage (V

vs. Temperature

Burst Mode Voltage (V

850

830

810

(mV)

790

BURH

V

770

750

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

) vs Tem peratur e

BURH

Figure 8. Burst-Mode Voltage (V

vs. Temperature

BURH

START

)

4.5

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

Figure 7. UVLO Threshold Voltage (V

vs. Temperature

Burst Mode Voltage (V

800

780

760

(mV)

740

BURL

V

720

700

-40 -25 -1 0 5 20 35 50 65 80 95 110 125

Temperature (℃)

Figure 9. Burst-Mode Voltage (V

) vs Temperature

BURL

vs. Temperature

STOP

)

Typical Performance Characteristics (Continued)

These characteristic graphs are measured at TA = 25°C.

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Maximum Duty Ratio (D

64.0

63.0

62.0

61.0

(%)

60.0

MAx

D

59.0

58.0

57.0

56.0

-40 - 25 - 10 5 20 35 50 65 80 95 110 125

Tempe rature (℃)

) vs Tem pera ture

MAX

Figure 10. Maximum Duty Ratio (D

Pea k Curr ent Lim it (I

310.0

300.0

290.0

280.0

(mA)

270.0

LIM

I

260.0

250.0

240.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

) vs Temperature

LIM

) vs. Temperature

MAX

Shutdown Feedback Voltage (VSD) vs Temper ature

5.0

4.8

4.6

(V)

SD

V

4.4

4.2

4.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

Figure 11. Shutdown Feedback Voltage (V

vs. Temperature

Shutdow n Delay Cur rent (I

5.5

5.3

5.1

(μA)

4.9

DELAY

I

4.7

4.5

-40 - 25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

) vs Temperature

DELAY

SD

)

Figure 12. Peak Current Limit (I

Supply Shunt Re gulator (V

7.0

6.8

6.6

(V)

CCRGE

6.4

V

6.2

6.0

-40 - 25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

) vs. Temperature

LIM

) vs Temperature

CCREG

Figure 14. Supply Shunt Regulator (V

vs. Temperature

CCREG

Figure 13. Shutdown Delay Current (I

vs. Temperature

)

DELAY

)

Functional Description

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

1. Startup and VCC Regulation: At startup, an internal

high-voltage current source supplies the internal bias and charges the external capacitor (C the V

pin, as illustrated in Figure 15. An internal high-

CC

) connected to

A

voltage regulator (HV/REG) located between the D and V

pins regulates the VCC to be 6.5V and supplies

CC

operating current. Therefore, FSQ500L needs no auxiliary bias winding.

Transformer

D

2

VCC

3

A

Figure 15. Startup Block

2. Feedback Control: FSQ500L employs current mode

control, as shown in Figure 16. An opto-coupler (such as the FOD817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the R switching duty cycle. When the reference pin voltage of the regulator exceeds the internal reference voltage of

2.5V, the opto-coupler LED current increases, pulling down the feedback voltage and reducing the duty cycle. This typically happens when the line input voltage increases or the output load current decreases.

2.1 Pulse-by-Pulse Current Limit: Because current mode control is employed, the peak current through the senseFET is limited by the non-inverting input of PWM comparator (V that 225µA current source flows only through the internal resistor (8R + R = 12kΩ), the cathode voltage of diode D2 is about 2.7V. Since D1 is blocked when the feedback voltage (V voltage of the cathode of D2 is clamped at this voltage, clamping V through the senseFET is limited.

2.2 Leading-Edge Blanking (LEB): At the instant the internal senseFET is turned on, a high-current spike occurs through the senseFET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the R would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading-edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (t = 250ns) after the senseFET turns on.

resistor makes it possible to control the

sense

*), as shown in Figure 16. Assuming

FB

*. Therefore, the peak value of the current

FB

ICH

6.5V

HV/REG

ISTART

V

REF

) exceeds 2.7V, the maximum

FB

UVLO

sense

resistor

LEB

V

CC

I

DELAYIFB

FOD817A

KA431

V

FB

2

D1 D2

C

B

V

SD

OSC

8R

+

V

*

FB

R

-

OLP

Gate

driver

SenseFET

R

sense

V

O

Figure 16. Pulse Width Modulation (PWM) Circuit

3. Protection Circuits: The FSQ500L has two self-

protective functions: overload protection (OLP) and thermal shutdown (TSD). While OLP is implemented as auto-restart mode, there is no switching when TSD triggers. Once the overload condition is detected, switching is terminated, the senseFET remains off, and HV/REG turns off. This causes V

to fall. When VCC

CC

falls below the under voltage lockout (UVLO) stop voltage of 5.0V, the protection is reset and the startup circuit charges the V

capacitor. When VCC reaches the

CC

start voltage of 6.0V, the FSQ500L resumes its normal operation. If the fault condition is still not removed, the senseFET and HV/REG remain off and V V

again. In this manner, the auto-restart can

STOP

drops to

CC

alternately enable and disable the switching of the power senseFET until the fault condition is eliminated, as shown in Figure 17.

Because these protection circuits are fully integrated into the IC without external components, reliability is improved without increasing cost.

V

6.5V

6.0V

5.0V

Normal

operation

OLP

occurs

Fault

situation

Power

DS

on

CC

OLP

removed

Normal

operation

t

Figure 17. Auto Restart Protection Waveforms

3.1 Overload Protection (OLP): Overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger to protect the SMPS. However, even when the SMPS is in the normal operation, the overload protection circuit can be triggered during the load transition. To avoid this undesired operation, the overload protection circuit is designed to trigger after a specified time to determine whether the situation is transient or a true overload. Because of the pulse-by-pulse current limit capability, the maximum peak current through the senseFET is limited and, therefore, the maximum input power is restricted with a given input voltage. If the output consumes more than this maximum power, the output voltage (V

) decreases below the set voltage. This

O

reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (V

). If VFB

FB

exceeds 2.7V, D1 is blocked and the 5µA current source starts to charge C V

continues increasing until it reaches 4.5V, when the

FB

slowly up to VCC. In this condition,

B

switching operation is terminated, as shown in Figure

18. The delay time for shutdown is the time required to charge C

from 2.7V to 4.5V with 5µA. In general, a 10

B

~ 50ms delay time is typical for most applications. This protection is implemented in auto restart mode.

V

4.5V

2.7V

FB

Overload protection

T12= CB*(4.5-2.7)/I

T

1

DELAY

t

T

2

Figure 18. Overload Protection

3.2 Thermal Shutdown (TSD): The senseFET and the

control IC in one package makes it easy for the control IC to detect an abnormal over temperature of the senseFET. When the temperature exceeds approximately 140°C, the thermal shutdown triggers. When TSD triggers, delay current is disabled, switching operation stops, and V

through the internal high-

CC

voltage current source is set to 5.7V from 6.5V, as shown in Figure 19. Since TSD signal prohibits the senseFET from switching, there is no switching until the junction temperature decreases sufficiently. If the junction temperature is lower than 60°C typically, TSD signal is removed and V

V

increases from 5.7V to 6.5V, the soft-start function

CC

is set to 6.5V again. While

CC

makes the senseFET turn on and off with no voltage and/or current stress.

V

6.5V

6.0V

5.7V

Normal

operation

TSD

occurs

Fault

situation

Power

DS

on

CC

TSD

removed

Normal

operation

t

Figure 19. Over-Temperature Protection (OTP)

4. Soft-Start: The soft-start time is tuned by an external

VCC capacitor (CA), which increases PWM comparator non-inverting input voltage together with the senseFET current slowly after it starts up. Before V V

, CA is charged by the current ICH-I

START

and I V

START

current consuming inside IC becomes I is charged by the current I increasing slope of V

are described in Figure 15. After VCC reaches

START

, all internal blocks are activated, so that the

OP

, which makes the

CH-IOP

become sluggish. VCC is shifted

CC

reaches

CC

, where ICH

START

. Therefore, CA

by 6.0V negatively (it is performed in soft-start block in Figure 2), and then V

-6.0V is an input of one of the

CC

input terminals of the PWM comparator. The drain current follows V

-6.0V instead of the VFB* because of

CC

the low-dominant feature of the PWM comparator. The soft-start time can be made long or short by selecting C

, as described in Figure 20. During t

A

disabled to avoid unwanted OLP. Typically, t around 4.6ms with 27µF of C

V

CC

6.5V

6V

5V

t1=CA×6V/(ICH-I

START

) t

.

A

t

S/S

t

1

2

×0.5V/(ICH-IOP)

S/S=CA

S/S

, I

DELAY

V

CCREG

V

START

V

S/S

STOP

is

t

Figure 20. Soft-Start Function

The peak value of the drain current of the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce stress on the secondary diode during startup.

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

5. Burst Operation: To minimize power dissipation in standby mode, the FPS enters burst-mode operation. During the burst mode operation, I of I

FB(Normal)

. As the load decreases, the feedback

decreases half

FB(Burst)

voltage decreases. As shown in Figure 21, the device automatically enters burst mode when the feedback voltage drops below V

(750mV). At this point,

BURL

switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes V

BURH

(800mV), switching resumes. The feedback voltage then falls and the process repeats. Burst mode alternately enables and disables switching of the power senseFET, reducing

switching loss in standby mode.

Vo

V

FB

0.80V

0.75V

I

DS

V

DS

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

set

t

1

Switching

disabled

t2t

Switching

disabled

3

t

4

Figure 21. Burst-Mode Operation

time

Package Dimensions

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Figure 22. 4-Lead, Small Outline Package (SOT223-4L)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Fairchild FSQ500L service manual

Specifications and Main Features

Frequently Asked Questions

User Manual