Charger & Adapter for Mobile Phone, PDA, MP3
Auxiliary Power for White Goods, PC, C-TV, Monitor
Related Application Notes
Description
The FSQ100 consists of an integrated Pulse Width
Modulator (PWM) and SenseFET, specifically designed
for high-performance, off-line, Switch-Mode Power
Supplies (SMPS) with minimal external components.
This device is an integrated high-voltage power
switching regulator that combines a VDMOS SenseFET
with a voltage mode PWM control block. The integrated
PWM controller features include a fixed oscillator,
Under-Voltage Lockout (UVLO) protection, Leading
Edge Blanking (LEB), an optimized gate turn-on/turn-off
driver, Thermal Shutdown (TSD) protection, and
temperature-compensated precision-current sources for
loop compensation and fault protection circuitry.
When compared to a discrete MOSFET and controller or
RCC solution, the FSQ100 device reduces total
component count and design size and weight, while
increasing efficiency, productivity, and system reliability.
This device provides a basic platform well suited for
cost-effective flyback converters.
TM
)
AN-4137 — Design Guidelines for Off-line Flyback
Converters using FPS™
AN-4141 — Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
AN-4147 — Design Guidelines for RCD Snubber of
Flyback
AN-4134 — Design Guidelines for Off-line Forward
Converters using FPS™
AN-4138 — Design Considerations for Battery
Charger Using Green Mode Fairchild Power Switch
(FPS™)
Ordering Information
Product Number Package Marking Code BV
FSQ100 8-DIP Q100 650V 67KHz
FPS™ is a trademark of Fairchild Semiconductor Corporation.
Ground. SenseFET source terminal on primary-side and internal control ground.
Positive Supply Voltage Input. Although connected to an auxiliary transformer winding,
current is supplied from pin 5 (V
V
reaches the UVLO upper threshold (9V), the internal startup switch opens and device power
CC
) via an internal switch during startup (see Figure 2). When
STR
is supplied via the auxiliary transformer winding.
Feedback. Inverting input to the PWM comparator with its normal input level lies between 0.5V
and 2.5V. It has a 0.4mA current source connected internally, while a capacitor and optocoupler are typically connected externally. A feedback voltage of 4.5V triggers overload
protection (OLP). There is a time delay while charging external capacitor C
using an internal 5µA current source. This time delay prevents false triggering under transient
conditions, but still allows the protection mechanism to operate in true overload conditions.
No Connection.
Startup. This pin connects directly to the rectified AC line voltage source. At startup, the internal
switch supplies internal bias and charges an external storage capacitor placed between the VCC
pin and ground. Once the V
reaches 9V, the internal switch stops charging the capacitor.
CC
SenseFET Drain. The drain pins are designed to connect directly to the primary lead of the
transformer and are capable of switching a maximum of 650V. Minimizing the length of the trace
connecting these pins to the transformer decreases leakage inductance.
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T
Symbol Parameter Value Unit
V
Drain Pin Voltage 650 V
DRAIN
V
VSTR Pin Voltage 650 V
STR
VDG Drain-Gate Voltage 650 V
VGS Gate-Source Voltage
VCC Supply Voltage 20 V
VFB Feedback Voltage Range -0.3 to V
PD Total Power Dissipation 1.40 W
TJ Operating Junction Temperature Internally limited °C
TA Operating Ambient Temperature -25 to +85 °C
T
Storage Temperature -55 to +150 °C
STG
Notes:
1. Repetitive rating: Pulse width is limited by maximum junction temperature.
2. L = 24mH, starting T
= 25C.
J
= 25°C, unless otherwise specified.
A
±20
STOP
V
V
TM
)
Thermal Impedance
TA = 25°C, unless otherwise specified. All items are tested with the JEDEC standards JESD 51-2 and 51-10 (DIP).
Symbol Parameter Value Unit
θJA Junction-to-Ambient Thermal Impedance
θJC Junction-to-Case Thermal Impedance
Notes:
3. Free-standing with no heatsink; without copper clad. Measurement condition; just before junction temperature TJ
enters into OTP.
4. Measured on the DRAIN pin close to plastic interface.
1. Startup: At startup, the internal high-voltage current
source supplies the internal bias and charges the
external V
V
reaches 9V, the device starts switching and the
CC
internal high-voltage current source stops charging the
capacitor. The device is in normal operation provided
V
does not drop below 7V. After startup, the bias is
CC
supplied from the auxiliary transformer winding.
Calculating the V
design with the FSQ100. At initial startup, the maximum
value of start operating current I
which supplies current to UVLO and V
charging current I
– 100µA. After V
the bias winding supplies V
When the bias winding voltage is not sufficient, the V
level decreases to the UVLO stop voltage and the
internal current source is activated again to charge the
V
capacitor. To prevent this VCC fluctuation
CC
(charging/discharging), the V
chosen to have a value between 10µF and 47µF.
V
capacitor, as shown in Figure 14. When
CC
VIN,dc
I
STR
Vstr
V
CC
L
H
9V/ 7V
Figure 14. Internal Startup Circuit
capacitor is an important step to
CC
is about 100µA,
START
of the V
VCC
reaches the UVLO start voltage, only
CC
VIN,dc
I
=I
- I
Vc c
STR
ST
R T
I
= I
-I
Vcc
STR
START
V
CC
CC
capacitor is equal to I
CC
current to the device.
CC
CC
I
ST
R T
U VLO
V
REF
capacitor should be
I
STR
V
ST
J-F ET
re
blocks. The
STR
CC
When the shunt regulator reference pin voltage exceeds
the internal reference voltage of 2.5V, the opto-coupler
LED current increases, the feedback voltage V
pulled down, and it reduces the duty cycle. This
happens when the input voltage increases or the output
load decreases.
V
CC
5µA
KA431
V
fb
4
+
C
fb
V
fb
V
SD
V
O
OSC
V
ref
400µA
R
OLP
Gate
driver
Figure 16. PWM and Feedback Circuit
3. Leading Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, the primary-side
capacitance and secondary-side rectifier diode reverse
recovery typically causes a high-current spike through
the SenseFET. Excessive voltage across the R
resistor lead to incorrect pulse-by-pulse current limit
protection. To avoid this, a leading edge blanking (LEB)
circuit disables pulse-by-pulse current-limit protection
block for a fixed time (t
) after the SenseFET turns on.
LEB
4. Protection Circuit: The FSQ100 has protective
functions, such as overload protection (OLP), over
voltage protection (OVP), under-voltage lockout (UVLO),
and thermal shutdown (TSD). Because these protection
circuits are fully integrated inside the IC without external
components, reliability is improved without increasing
costs. Once a fault condition occurs, switching is
terminated and the SenseFET remains off. This causes
V
to fall. When VCC reaches the UVLO stop voltage
CC
V
(7V), the protection is reset and the internal high-
STOP
voltage current source charges the V
V
pin. When VCC reaches the UVLO start voltage
STR
V
(9V), the device resumes normal operation. In
START
capacitor via the
CC
this manner, the auto-restart can alternately enable and
disable the switching of the power SenseFET until the
fault condition is eliminated.
FB
SENSE
FSQ100 — Green Mode Fairchild Power Switch (FPS
is
TM
)
V
START
V
STOP
Figure 15. Charging V
UV LO
V
must not d
CC
belo
Biaswinding
voltage
Capacitor through Vstr
CC
op
V
STOP
t
2. Feedback Control: The FSQ100 is a voltage mode
controlled device, as shown in Figure 16. Usually, an
5 µA4 00 µ A
V
fb
4
C
fb
RESET
Figure 17. Protection Block
OSC
+
-
R
OLP
4.5 V
TSD
SRQ
SRQ
A/R
GATE
DRIVER
OLP, TSD
Protection Block
opto-coupler and shunt regulator, like KA431 are used
to implement the feedback network. The feedback
voltage is compared with an internally generated
sawtooth waveform. This directly controls the duty cycle.
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding a pre-set level due to an
unexpected event. In this situation, the protection circuit
should be activated to protect the SMPS. However,
even when the SMPS is operating normally, the over
load protection (OLP) circuit can be activated during the
load transition. To avoid this undesired operation, the
OLP circuit is designed to be activated after a specified
time to determine whether it is a transient situation or a
true overload situation. If the output consumes more
than the maximum power determined by I
voltage (V
) decreases below its rating voltage. This
O
, the output
LIM
reduces the current through the opto-coupler LED,
which also reduces the opto-coupler transistor current,
thus increasing the feedback voltage (V
). If VFB
FB
exceeds 3V, the feedback input diode is blocked and the
5µA current source (I
up to V
. In this condition, VFB increases until it reaches
CC
) starts to charge CFB slowly
DELAY
4.5V, when the switching operation is terminated, as
shown in Figure 18. The shutdown delay time is the time
required to charge C
from 3V to 4.5V with a 5µA
FB
current source.
V
FB
Overload Protection
4.5V
Drain current
0.55A
2.14ms
0.31A
7steps
t
Figure 19. Internal Soft-Start
6. Burst Operation: To minimize the power dissipation
in standby mode, the FSQ100 enters burst-mode
operation. As the load decreases, the feedback voltage
decreases. The device automatically enters burst mode
when the feedback voltage drops below V
BURL
(0.55V).
At this point, switching stops and the output voltages
start to drop. This causes the feedback voltage to rise.
Once is passes V
(0.70V), switching starts again.
BURH
The feedback voltage falls and the process repeats.
Burst-mode operation alternately enables and disables
switching of the power MOSFET to reduce the switching
loss in standby mode.
OSC
FSQ100 — Green Mode Fairchild Power Switch (FPS
TM
)
3V
DELAY
t
)-V( t
)) /
2
I
1
DELAY
t
t
2
VtVVtVAI
5.4)(,3)(,5;
===
21
=Cfb×(V(
t
12
t
1
tVtV
)()(
−
I
DELAY
12
Cfbt
=µ
12
Figure 18. Overload Protection (OLP)
4.2 Thermal Shutdown (TSD): The SenseFET and the
control IC are integrated, making it easier for the control
IC to detect the temperature of the SenseFET. When
the temperature exceeds approximately 145C, thermal
shutdown is activated.
5. Soft-Start: The FPS has an internal soft-start circuit
that slowly increases the feedback voltage, together with
the SenseFET current, right after it starts. The typical
soft-start time is 15ms, as shown in Figure 19, where
progressive increment of the SenseFET current is
allowed during the startup phase. Soft-start circuit
progressively increases current limits to establish proper
working conditions for transformers, inductors,
capacitors, and switching devices. It also helps to
prevent transformer saturation and reduces the stress
on the secondary diode.
Switching mode power converters have electronic and
magnetic components that generate audible noise when
the operating frequency is in the range of 20~20,000Hz.
Even though they operate above 20kHz, they can make
noise, depending on the load condition. Designers can
employ several methods to reduce noise.
Glue or Varnish
The most common method involves using glue or
varnish to tighten magnetic components. The motion of
core, bobbin and coil, and the chattering or
magnetostriction of core can cause the transformer to
produce audible noise. The use of rigid glue and varnish
helps reduce the transformer noise, but can crack the
core. This is because sudden changes in the ambient
temperature cause the core and the glue to expand or
shrink in a different ratio.
Ceramic Capacitor
Using a film capacitor instead of a ceramic capacitor as
a snubber capacitor is another noise-reduction solution.
Some dielectric materials show a piezoelectric effect,
depending on the electric field intensity. Hence, a
snubber capacitor becomes one of the most significant
sources of audible noise. It is possible to use a Zener
clamp circuit instead of an RCD snubber for higher
efficiency as and lower audible noise.
Adjusting Sound Frequency
Moving the fundamental frequency of noise out of
2~4kHz range is the third method. Generally, humans
are more sensitive to noise in the range of 2~4kHz.
When the fundamental frequency of noise is located in
this range, the noise is perceived as louder, although
the noise intensity level is identical (refer to Figure 22
Equal Loudness Curves).
When FPS acts in burst mode and the burst operation is
suspected to be a source of noise, this method may be
helpful. If the frequency of burst-mode operation lies in
the range of 2~4 kHz, adjusting the feedback loop can
shift the burst operation frequency. To reduce the burst
operation frequency, increase a feedback gain capacitor
(C
), opto-coupler supply resistor (RD), and feedback
F
capacitor (C
(R
), as shown in Figure 23.
F
); and decrease a feedback gain resistor
B
Figure 22. Equal Loudness Curves
Figure 23. Typical Feedback Network of FPS™
2. Reference Materials
AN-4134 — Design Guidelines for Off-line Forward
Converters using FPS™
AN-4137 — Design Guidelines for Off-line Flyback
Converters using FPS™
AN-4138 — Design Considerations for Battery Charger
Using Green Mode Fairchild Power Switch (FPS™)
AN-4140 — Transformer Design Consideration for Offline Flyback Converters Using Fairchild Power Switch
(FPS™)
AN-4141 — Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
AN-4147 — Design Guidelines for RCD Snubber of
Flyback
AN-4148 — Audible Noise Reduction Techniques for
FPS™Applications