Charger & Adapter for Mobile Phone, PDA, MP3
Auxiliary Power for White Goods, PC, C-TV, Monitor
Related Application Notes
Description
The FSQ100 consists of an integrated Pulse Width
Modulator (PWM) and SenseFET, specifically designed
for high-performance, off-line, Switch-Mode Power
Supplies (SMPS) with minimal external components.
This device is an integrated high-voltage power
switching regulator that combines a VDMOS SenseFET
with a voltage mode PWM control block. The integrated
PWM controller features include a fixed oscillator,
Under-Voltage Lockout (UVLO) protection, Leading
Edge Blanking (LEB), an optimized gate turn-on/turn-off
driver, Thermal Shutdown (TSD) protection, and
temperature-compensated precision-current sources for
loop compensation and fault protection circuitry.
When compared to a discrete MOSFET and controller or
RCC solution, the FSQ100 device reduces total
component count and design size and weight, while
increasing efficiency, productivity, and system reliability.
This device provides a basic platform well suited for
cost-effective flyback converters.
TM
)
AN-4137 — Design Guidelines for Off-line Flyback
Converters using FPS™
AN-4141 — Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
AN-4147 — Design Guidelines for RCD Snubber of
Flyback
AN-4134 — Design Guidelines for Off-line Forward
Converters using FPS™
AN-4138 — Design Considerations for Battery
Charger Using Green Mode Fairchild Power Switch
(FPS™)
Ordering Information
Product Number Package Marking Code BV
FSQ100 8-DIP Q100 650V 67KHz
FPS™ is a trademark of Fairchild Semiconductor Corporation.
Ground. SenseFET source terminal on primary-side and internal control ground.
Positive Supply Voltage Input. Although connected to an auxiliary transformer winding,
current is supplied from pin 5 (V
V
reaches the UVLO upper threshold (9V), the internal startup switch opens and device power
CC
) via an internal switch during startup (see Figure 2). When
STR
is supplied via the auxiliary transformer winding.
Feedback. Inverting input to the PWM comparator with its normal input level lies between 0.5V
and 2.5V. It has a 0.4mA current source connected internally, while a capacitor and optocoupler are typically connected externally. A feedback voltage of 4.5V triggers overload
protection (OLP). There is a time delay while charging external capacitor C
using an internal 5µA current source. This time delay prevents false triggering under transient
conditions, but still allows the protection mechanism to operate in true overload conditions.
No Connection.
Startup. This pin connects directly to the rectified AC line voltage source. At startup, the internal
switch supplies internal bias and charges an external storage capacitor placed between the VCC
pin and ground. Once the V
reaches 9V, the internal switch stops charging the capacitor.
CC
SenseFET Drain. The drain pins are designed to connect directly to the primary lead of the
transformer and are capable of switching a maximum of 650V. Minimizing the length of the trace
connecting these pins to the transformer decreases leakage inductance.
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T
Symbol Parameter Value Unit
V
Drain Pin Voltage 650 V
DRAIN
V
VSTR Pin Voltage 650 V
STR
VDG Drain-Gate Voltage 650 V
VGS Gate-Source Voltage
VCC Supply Voltage 20 V
VFB Feedback Voltage Range -0.3 to V
PD Total Power Dissipation 1.40 W
TJ Operating Junction Temperature Internally limited °C
TA Operating Ambient Temperature -25 to +85 °C
T
Storage Temperature -55 to +150 °C
STG
Notes:
1. Repetitive rating: Pulse width is limited by maximum junction temperature.
2. L = 24mH, starting T
= 25C.
J
= 25°C, unless otherwise specified.
A
±20
STOP
V
V
TM
)
Thermal Impedance
TA = 25°C, unless otherwise specified. All items are tested with the JEDEC standards JESD 51-2 and 51-10 (DIP).
Symbol Parameter Value Unit
θJA Junction-to-Ambient Thermal Impedance
θJC Junction-to-Case Thermal Impedance
Notes:
3. Free-standing with no heatsink; without copper clad. Measurement condition; just before junction temperature TJ
enters into OTP.
4. Measured on the DRAIN pin close to plastic interface.