Fairchild FSQ100 service manual

FSQ100 Green Mode Fairchild Power Switch (FPS™)
FSQ100 — Green Mode Fairchild Power Switch (FPS
March 2011
Internal Avalanche-Rugged SenseFET Precision Fixed Operating Frequency: 67KHz Burst-Mode Operation Internal Startup Circuit Pulse-by-Pulse Current Limiting Over-Voltage Protection (OVP) Overload Protection (OLP) Internal Thermal Shutdown Function (TSD) Auto-Restart Mode Under-Voltage Lockout (UVLO) with Hysteresis Built-in Soft-Start Secondary-Side Regulation
Applications
Charger & Adapter for Mobile Phone, PDA, MP3 Auxiliary Power for White Goods, PC, C-TV, Monitor
Related Application Notes
Description
The FSQ100 consists of an integrated Pulse Width Modulator (PWM) and SenseFET, specifically designed for high-performance, off-line, Switch-Mode Power Supplies (SMPS) with minimal external components. This device is an integrated high-voltage power switching regulator that combines a VDMOS SenseFET with a voltage mode PWM control block. The integrated PWM controller features include a fixed oscillator, Under-Voltage Lockout (UVLO) protection, Leading Edge Blanking (LEB), an optimized gate turn-on/turn-off driver, Thermal Shutdown (TSD) protection, and temperature-compensated precision-current sources for loop compensation and fault protection circuitry.
When compared to a discrete MOSFET and controller or RCC solution, the FSQ100 device reduces total component count and design size and weight, while increasing efficiency, productivity, and system reliability. This device provides a basic platform well suited for cost-effective flyback converters.
TM
)
AN-4137 Design Guidelines for Off-line Flyback
Converters using FPS™
AN-4141 Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
AN-4147 Design Guidelines for RCD Snubber of
Flyback
AN-4134 Design Guidelines for Off-line Forward
Converters using FPS™
AN-4138 Design Considerations for Battery
Charger Using Green Mode Fairchild Power Switch (FPS™)
Ordering Information
Product Number Package Marking Code BV
FSQ100 8-DIP Q100 650V 67KHz
FPS™ is a trademark of Fairchild Semiconductor Corporation.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2
f
DSS
R
OSC
DS(ON)
16
A
f
A
r
Typical Application
FSQ100 — Green Mode Fairchild Power Switch (FPS
C
IN
V
STR
Drain
PWM
DC
OUT
V
V
FB
GND
CC
Figure 1. Typical Flyback Application
Table 1. Output Power Table
Product
230VAC ±15%
FSQ100 13W 8W
Notes:
1. Maximum practical continuous power in an open-frame design with sufficient drain pattern as a heat sinker, at 50C ambient.
2. 230VAC or 100/115VAC with doubler.
(2)
Open Frame
(1)
85~265V
AC
Internal Block Diagram
V
STR
V
2
CC
OSC
PWM
Internal
Bias
9/7V
Vck
SRQ
UVLO
I
I
delay
fb
µA
µA
40
5
V
FB
3
0
Voltage
Re
L
H
5
DR IVER
D
6,7,8
ain
SFET
TM
)
S/ S
15ms
V
/
BURL
V
BURH
C
N
4
Reset
V
Min.20V
OV P
BURST
LEB
OLP
SD
TSD
SRQ
/R
I
LIM
R
V
th
sense
1
GND
Figure 2. Functional Block Diagram
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 2
r
r
Pin Assignments
FSQ100 — Green Mode Fairchild Power Switch (FPS
1
2
V
CC
V
3
FB
45
NC
Drain
8GND
ain
D
7
ain
6
D
V
STR
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
1 GND
2 VCC
3 VFB
4 NC
5 V
STR
6,7,8 Drain
Ground. SenseFET source terminal on primary-side and internal control ground. Positive Supply Voltage Input. Although connected to an auxiliary transformer winding,
current is supplied from pin 5 (V V
reaches the UVLO upper threshold (9V), the internal startup switch opens and device power
CC
) via an internal switch during startup (see Figure 2). When
STR
is supplied via the auxiliary transformer winding.
Feedback. Inverting input to the PWM comparator with its normal input level lies between 0.5V
and 2.5V. It has a 0.4mA current source connected internally, while a capacitor and opto­coupler are typically connected externally. A feedback voltage of 4.5V triggers overload protection (OLP). There is a time delay while charging external capacitor C using an internal 5µA current source. This time delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate in true overload conditions.
No Connection. Startup. This pin connects directly to the rectified AC line voltage source. At startup, the internal
switch supplies internal bias and charges an external storage capacitor placed between the VCC pin and ground. Once the V
reaches 9V, the internal switch stops charging the capacitor.
CC
SenseFET Drain. The drain pins are designed to connect directly to the primary lead of the
transformer and are capable of switching a maximum of 650V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance.
TM
)
from 3V to 4.5V
fb
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 3
FSQ100 — Green Mode Fairchild Power Switch (FPS
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. T
Symbol Parameter Value Unit
V
Drain Pin Voltage 650 V
DRAIN
V
VSTR Pin Voltage 650 V
STR
VDG Drain-Gate Voltage 650 V
VGS Gate-Source Voltage
VCC Supply Voltage 20 V
VFB Feedback Voltage Range -0.3 to V
PD Total Power Dissipation 1.40 W
TJ Operating Junction Temperature Internally limited °C
TA Operating Ambient Temperature -25 to +85 °C
T
Storage Temperature -55 to +150 °C
STG
Notes:
1. Repetitive rating: Pulse width is limited by maximum junction temperature.
2. L = 24mH, starting T
= 25C.
J
= 25°C, unless otherwise specified.
A
±20
STOP
V
V
TM
)
Thermal Impedance
TA = 25°C, unless otherwise specified. All items are tested with the JEDEC standards JESD 51-2 and 51-10 (DIP).
Symbol Parameter Value Unit
θJA Junction-to-Ambient Thermal Impedance
θJC Junction-to-Case Thermal Impedance
Notes:
3. Free-standing with no heatsink; without copper clad. Measurement condition; just before junction temperature TJ enters into OTP.
4. Measured on the DRAIN pin close to plastic interface.
(3)
88.84 °C/W
(4)
13.94 °C/W
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 4
FSQ100 — Green Mode Fairchild Power Switch (FPS
Electrical Characteristics
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min. Typ. Max. Unit
SenseFET Section
I
Zero-Gate-Voltage Drain Current
DSS
R
Drain-Source On-State Resistance
DS(ON)
gfs Forward Trans-Conductance VDS=50V, ID=0.5A 1.0 1.3 S
C
Input Capacitance
ISS
Output Capacitance 18
OSS
C
Reverse Transfer Capacitance 3.8
RSS
Control Section
f
Switching Frequency 61 67 73 kHz
OSC
Δf
Switching Frequency Variation
OSC
D
Maximum Duty Cycle 60 67 74 %
MAX
V
START
V
STOP
UVLO Threshold Voltage
V
(6)
-25°C ≤ TA 85°C ±5 ±10 %
IFB Feedback Source Current 0V ≤ VFB 3V 0.35 0.40 0.45 mA
t
Internal Soft Start Time 10 15 20 ms
S/S
Burst Mode Section
V
BURH
V
0.45 0.55 0.65 V
BURL
V
BUR(HYS)
Burst Mode Voltage
Hysteresis 150 mV
Protection Section
I
Peak Current Limit 0.475 0.550 0.650 A
LIM
TSD Thermal Shutdown Temperature
(7)
VSD Shutdown Feedback Voltage 4.0 4.5 5.0 V
V
Over-Voltage Protection 20 V
OVP
I
Shutdown Delay Current 3V ≤ VFB VSD 4 5 6 µA
DELAY
Total Device Section
IOP Operating Supply Current
(8)
V
ICH Startup Charging Current VCC=0V , V
Notes:
5. Pulse test: Pulse width 300µs, duty 2%.
6. These parameters, although guaranteed, are tested in EDS (wafer test) process.
7. These parameters, although guaranteed, are not 100% tested in production.
8. Control part only.
VDS=650V, VGS=0V 25
VDS=520V, VGS=0V, TC=125C
(5)
VGS=10V, ID=0.5A 16 22
200
µA
162
=0V, VDS=25V, f=1MHz
V
GS
pF C
VFB=GND 8 9 10 V
=GND 6 7 8 V
FB
TJ=25°C
0.6 0.7 0.8 V
125 145 °C
16V 1.5 3.0 mA
CC
=50V 450 550 650 µA
STR
TM
)
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 5
Typical Performance Characteristics
These characteristic graphs are normalized at T
= 25°C.
A
FSQ100 — Green Mode Fairchild Power Switch (FPS
1.15
1.10
1.05
1.00
OVP
V
0.95
0.90
0.85
-50 0 50 100 150
Temperature [°C]
Figure 4. Over-Voltage Protection (V
1.15
1.10
1.05
1.00
OP
) vs. TA Figure 5. Operating Supply Current (IOP) vs. TA
OVP
I
0.95
0.90
0.85
-50 0 50 100 150
Temperature [°C]
1.15
1.10
1.05
1.00
STAART
V
0.95
0.90
0.85
-50 0 50 100 150
1.15
1.10
1.05
1.00
STOP
V
0.95
0.90
0.85
-50 0 50 100 150
TM
)
Temperature [°C]
Figure 6. Start Threshold Voltage (V
) vs. TA Figure 7. Stop Threshold Voltage (V
START
Temperature [°C]
STOP
) vs. TA
1.15
1.10
1.05
1.00
OSC
f
0.95
0.90
0.85
-50 0 50 100 150
Temperature [°C]
Figure 8. Operating Frequency (f
1.15
1.10
1.05
1.00
MAX
D
0.95
0.90
0.85
-50 0 50 100 150
Temperature [°C]
) vs. TA Figure 9. Maximum Duty Cycle (D
OSC
) vs. TA
MAX
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 6
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at T
= 25°C.
A
FSQ100 — Green Mode Fairchild Power Switch (FPS
1.15
1.10
1.05
1.00
LIM
I
0.95
0.90
0.85
-50 0 50 100 150
Temperature [°C]
Figure 10. Peak Current Limit (I
1.15
1.10
1.05
1.00
FB
) vs. TA Figure 11. Feedback Source Current (IFB) vs. TA
LIM
I
0.95
0.90
0.85
-50 0 50 100 150
Temperature [°C]
1.15
1.10
1.05
1.00
DELAY
I
0.95
0.90
0.85
-50 0 50 100 150
1.15
1.10
1.05
SD
1.00
V
0.95
0.90
0.85
-50 0 50 100 150
TM
)
Temperature [°C]
Figure 12. Shutdown Delay Current (I
) vs. TA Figure 13. Shutdown Feedback Voltage (VSD) vs. TA
DELAY
Temperature [°C]
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 7
R
f
A
A
r
w
Functional Description
1. Startup: At startup, the internal high-voltage current
source supplies the internal bias and charges the external V V
reaches 9V, the device starts switching and the
CC
internal high-voltage current source stops charging the capacitor. The device is in normal operation provided V
does not drop below 7V. After startup, the bias is
CC
supplied from the auxiliary transformer winding.
Calculating the V design with the FSQ100. At initial startup, the maximum value of start operating current I which supplies current to UVLO and V charging current I – 100µA. After V the bias winding supplies V When the bias winding voltage is not sufficient, the V level decreases to the UVLO stop voltage and the internal current source is activated again to charge the V
capacitor. To prevent this VCC fluctuation
CC
(charging/discharging), the V chosen to have a value between 10µF and 47µF.
V
capacitor, as shown in Figure 14. When
CC
VIN,dc
I
STR
Vstr
V
CC
L
H
9V/ 7V
Figure 14. Internal Startup Circuit
capacitor is an important step to
CC
is about 100µA,
START
of the V
VCC
reaches the UVLO start voltage, only
CC
VIN,dc
I
=I
- I
Vc c
STR
ST
R T
I
= I
-I
Vcc
STR
START
V
CC
CC
capacitor is equal to I
CC
current to the device.
CC
CC
I
ST
R T
U VLO
V
REF
capacitor should be
I
STR
V
ST
J-F ET
re
blocks. The
STR
CC
When the shunt regulator reference pin voltage exceeds the internal reference voltage of 2.5V, the opto-coupler LED current increases, the feedback voltage V pulled down, and it reduces the duty cycle. This happens when the input voltage increases or the output load decreases.
V
CC
5µA
KA431
V
fb
4
+
C
fb
V
fb
V
SD
V
O
OSC
V
ref
400µA
R
OLP
Gate
driver
Figure 16. PWM and Feedback Circuit
3. Leading Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, the primary-side capacitance and secondary-side rectifier diode reverse recovery typically causes a high-current spike through the SenseFET. Excessive voltage across the R resistor lead to incorrect pulse-by-pulse current limit protection. To avoid this, a leading edge blanking (LEB) circuit disables pulse-by-pulse current-limit protection block for a fixed time (t
) after the SenseFET turns on.
LEB
4. Protection Circuit: The FSQ100 has protective
functions, such as overload protection (OLP), over voltage protection (OVP), under-voltage lockout (UVLO), and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, reliability is improved without increasing costs. Once a fault condition occurs, switching is terminated and the SenseFET remains off. This causes V
to fall. When VCC reaches the UVLO stop voltage
CC
V
(7V), the protection is reset and the internal high-
STOP
voltage current source charges the V V
pin. When VCC reaches the UVLO start voltage
STR
V
(9V), the device resumes normal operation. In
START
capacitor via the
CC
this manner, the auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated.
FB
SENSE
FSQ100 — Green Mode Fairchild Power Switch (FPS
is
TM
)
V
START
V
STOP
Figure 15. Charging V
UV LO
V
must not d
CC
belo
Biaswinding
voltage
Capacitor through Vstr
CC
op
V
STOP
t
2. Feedback Control: The FSQ100 is a voltage mode
controlled device, as shown in Figure 16. Usually, an
5 µA 4 00 µ A
V
fb
4
C
fb
RESET
Figure 17. Protection Block
OSC
+
-
R
OLP
4.5 V TSD
SRQ
SRQ
A/R
GATE
DRIVER
OLP, TSD
Protection Block
opto-coupler and shunt regulator, like KA431 are used to implement the feedback network. The feedback voltage is compared with an internally generated sawtooth waveform. This directly controls the duty cycle.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 8
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated to protect the SMPS. However, even when the SMPS is operating normally, the over load protection (OLP) circuit can be activated during the load transition. To avoid this undesired operation, the OLP circuit is designed to be activated after a specified time to determine whether it is a transient situation or a true overload situation. If the output consumes more than the maximum power determined by I voltage (V
) decreases below its rating voltage. This
O
, the output
LIM
reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (V
). If VFB
FB
exceeds 3V, the feedback input diode is blocked and the 5µA current source (I up to V
. In this condition, VFB increases until it reaches
CC
) starts to charge CFB slowly
DELAY
4.5V, when the switching operation is terminated, as shown in Figure 18. The shutdown delay time is the time required to charge C
from 3V to 4.5V with a 5µA
FB
current source.
V
FB
Overload Protection
4.5V
Drain current
0.55A
2.14ms
0.31A
7steps
t
Figure 19. Internal Soft-Start
6. Burst Operation: To minimize the power dissipation
in standby mode, the FSQ100 enters burst-mode operation. As the load decreases, the feedback voltage decreases. The device automatically enters burst mode when the feedback voltage drops below V
BURL
(0.55V). At this point, switching stops and the output voltages start to drop. This causes the feedback voltage to rise. Once is passes V
(0.70V), switching starts again.
BURH
The feedback voltage falls and the process repeats. Burst-mode operation alternately enables and disables switching of the power MOSFET to reduce the switching loss in standby mode.
OSC
FSQ100 — Green Mode Fairchild Power Switch (FPS
TM
)
3V
DELAY
t
)-V( t
)) /
2
I
1
DELAY
t
t
2
VtVVtVAI
5.4)(,3)(,5;
===
21
=Cfb×(V(
t
12
t
1
tVtV
)()(
I
DELAY
12
Cfbt
12
Figure 18. Overload Protection (OLP)
4.2 Thermal Shutdown (TSD): The SenseFET and the
control IC are integrated, making it easier for the control IC to detect the temperature of the SenseFET. When the temperature exceeds approximately 145C, thermal shutdown is activated.
5. Soft-Start: The FPS has an internal soft-start circuit
that slowly increases the feedback voltage, together with the SenseFET current, right after it starts. The typical soft-start time is 15ms, as shown in Figure 19, where progressive increment of the SenseFET current is allowed during the startup phase. Soft-start circuit progressively increases current limits to establish proper working conditions for transformers, inductors, capacitors, and switching devices. It also helps to prevent transformer saturation and reduces the stress on the secondary diode.
5µA 400µA
4
V
fb
Figure 20. Burst Operation Block
V
O
set
V
O
V
FB
0. 70V
0.55V
I
ds
V
ds
Figure 21. Burst Operation Function
SRQ
0.7 0 V
/0.55V
Burst Operati on Bloc k
GATE
DRIVER
on /off
t
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 9
Application Tips
1. Methods of Reducing Audible Noise
Switching mode power converters have electronic and magnetic components that generate audible noise when the operating frequency is in the range of 20~20,000Hz. Even though they operate above 20kHz, they can make noise, depending on the load condition. Designers can employ several methods to reduce noise.
Glue or Varnish
The most common method involves using glue or varnish to tighten magnetic components. The motion of core, bobbin and coil, and the chattering or magnetostriction of core can cause the transformer to produce audible noise. The use of rigid glue and varnish helps reduce the transformer noise, but can crack the core. This is because sudden changes in the ambient temperature cause the core and the glue to expand or shrink in a different ratio.
Ceramic Capacitor
Using a film capacitor instead of a ceramic capacitor as a snubber capacitor is another noise-reduction solution. Some dielectric materials show a piezoelectric effect, depending on the electric field intensity. Hence, a snubber capacitor becomes one of the most significant sources of audible noise. It is possible to use a Zener clamp circuit instead of an RCD snubber for higher efficiency as and lower audible noise.
Adjusting Sound Frequency
Moving the fundamental frequency of noise out of 2~4kHz range is the third method. Generally, humans are more sensitive to noise in the range of 2~4kHz. When the fundamental frequency of noise is located in this range, the noise is perceived as louder, although the noise intensity level is identical (refer to Figure 22
Equal Loudness Curves).
When FPS acts in burst mode and the burst operation is suspected to be a source of noise, this method may be helpful. If the frequency of burst-mode operation lies in the range of 2~4 kHz, adjusting the feedback loop can shift the burst operation frequency. To reduce the burst operation frequency, increase a feedback gain capacitor (C
), opto-coupler supply resistor (RD), and feedback
F
capacitor (C (R
), as shown in Figure 23.
F
); and decrease a feedback gain resistor
B
Figure 22. Equal Loudness Curves
Figure 23. Typical Feedback Network of FPS™
2. Reference Materials
AN-4134 Design Guidelines for Off-line Forward Converters using FPS™
AN-4137 Design Guidelines for Off-line Flyback Converters using FPS™
AN-4138 Design Considerations for Battery Charger Using Green Mode Fairchild Power Switch (FPS™)
AN-4140 — Transformer Design Consideration for Off­line Flyback Converters Using Fairchild Power Switch (FPS™)
AN-4141 Troubleshooting and Design Tips for Fairchild Power Switch (FPS™) Flyback Applications
AN-4147 Design Guidelines for RCD Snubber of Flyback
AN-4148 — Audible Noise Reduction Techniques for FPS™Applications
FSQ100 — Green Mode Fairchild Power Switch (FPS
TM
)
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 10
Physical Dimensions
0.400
0.355
10.160
9.017
[
FSQ100 Green Mode Fairchild Power Switch (FPS
]
PIN 1 INDICATOR
HALF LEAD 4X
0.005 [0.126]
SEATING PLANE
MIN 0.015 [0.381]
0.100 [2.540]
0.022
0.014
[
0.562
0.358
85
0.280
7.112
0.240
6.096
[
41
FULL LEAD 4X
0.005 [0.126] MIN
MAX 0.210 [5.334]
0.150
0.115
C
0.045
0.030
[
]
0.10 C
Figure 24. 8-Pin Dual Inline Package (DIP)
0.070
1.778
0.045
1.143
[
NOTES:
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) CONTROLING DIMS ARE IN INCHES
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER ASME
Y14.5M -1982
E) DRAWING FILENAME AND REVSION: MKT-N08MREV1.
]
0.195
0.115
[
1.144
0.763
4X
]
3.811
2.922
]
[
4X
4.965
2.933
]
0.325
8.263
0.300
7.628
[
]
]
0.015 [0.389] GAGE PLANE
TM
)
0.300 [7.618]
0.430 [10.922] MAX
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 11
FSQ100 Green Mode Fairchild Power Switch (FPS
TM
)
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ100 Rev. 1.0.2 12
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