A Valley Switching Converter generally shows lower EMI
and higher power conversion efficiency than a
conventional hard-switched converter with a fixed
switching frequency. The FSQ-series is an integrated
Pulse-Width Modulation (PWM) controller and
SenseFET specifically designed for valley switching
operation with minimal external components. The PWM
controller includes an integrated fixed-frequency
oscillator, under-voltage lockout, Leading-Edge Blanking
(LEB), optimized gate driver, internal soft-start,
temperature-compensated precise current sources for
loop compensation, and self-protection circuitry.
Compared with discrete MOSFET and PWM controller
solutions, the FSQ-series reduces total cost, component
count, size and weight; while simultaneously increasing
efficiency, productivity, and system reliability. This
device provides a basic platform for cost-effective
designs of valley switching fly-back converters.
Related Application Notes
AN-4137 - Design Guidelines for Offline Flyback
Converters Using Fairchild Power Switch (FPS™)
AN-4141 - Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback
Applications
Power Supplies for DVP Player, DVD Recorder,
Set-Top Box
Adapter
Auxiliary Power Supply for PC, LCD TV, and PDP TV
AN-4147 - Design Guidelines for RCD Snubber of
Flyback Converters
AN-4150 - Design Guidelines for Flyback
Converters Using FSQ-series Fairchild Power
Switch (FPS™)
AN-4134 - Design Guidelines for Off-line Forward
1 GND SenseFET source terminal on primary side and internal control ground.
Positive supply voltage input. Although connected to an auxiliary transformer winding,
2 VCC
3 Vfb
4 Sync
5 Vstr
6, 7, 8 Drain
current is supplied from pin 5 (Vstr) via an internal switch during startup (see Figure 2).
It is not until V
reaches the UVLO upper threshold (12V) that the internal startup switch
CC
opens and device power is supplied via the auxiliary transformer winding.
The feedback voltage pin is the non-inverting input to the PWM comparator. It has a
0.9mA current source connected internally while a capacitor and opto-coupler are typically
connected externally. There is a time delay while charging external capacitor C
to 6V using an internal 5A current source. This delay prevents false triggering under
transient conditions, but still allows the protection mechanism to operate under true
overload conditions.
This pin is internally connected to the sync-detect comparator for valley switching.
Typically the voltage of the auxiliary winding is used as Sync input voltage and external
resistors and capacitor are needed to make delay to match valley point. The threshold of
the internal sync comparator is 0.7V/0.2V.
This pin is connected to the rectified AC line voltage source. At startup, the internal switch
supplies internal bias and charges an external storage capacitor placed between the Vcc
pin and ground. Once the V
reaches 12V, the internal switch is opened.
CC
The drain pins are designed to connect directly to the primary lead of the transformer and
are capable of switching a maximum of 650V. Minimizing the length of the trace
connecting these pins to the transformer decreases leakage inductance.
from 3V
fb
FSQ0365/0265/0165/321 — Green Mode Fairchild Power Switch (FPS™) for Valley Switching Converter
FSQ0365/0265/0165/321 — Green Mode Fairchild Power Switch (FPS™) for Valley Switching Converter
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T
Symbol Parameter Min. Max. Unit
V
Vstr Pin Voltage 500 V
STR
V
Drain Pin Voltage 650 V
DS
V
Supply Voltage 20 V
CC
V
Feedback Voltage Range -0.3 9.0 V
FB
V
Sync Pin Voltage -0.3 9.0 V
Sync
IDM Drain Current Pulsed
EAS Single Pulsed Avalanche Energy
P
Total Power Dissipation 1.5 W
D
T
Recommended Operating Junction Temperature -40 Internally Limited
J
TA Operating Ambient Temperature -40 +85
T
Storage Temperature -55 +150
STG
ESD
Human Body Model; JESD22-A114
Machine Model; JESD22-A115
Notes:
5. Repetitive rating: Pulse width limited by maximum junction temperature.
6. L=51mH, starting T
=25°C.
J
(6)
(7)
=25°C, unless otherwise specified.
A
FSQ0365 12.0
FSQ0265 8.0
FSQ0165 4.0
FSQ321 1.5
FSQ0365 230
FSQ0265 140
FSQ0165 50
FSQ321 10
CLASS 1C
CLASS B
A
mJ
C
C
C
Thermal Impedance
Symbol Parameter Value Unit
(7)
8-DIP
Notes:
7. All items are tested with the standards JESD 51-2 and 51-10 (DIP).
8. Free-standing with no heat-sink, under natural convection.
9. Infinite cooling condition - refer to the SEMI G30-88.
FSQ0365/0265/0165/321 — Green Mode Fairchild Power Switch (FPS™) for Valley Switching Converter
1. Startup: At startup, an internal high-voltage current
source supplies the internal bias and charges the
external capacitor (C
illustrated in Figure 20. When V
) connected to the VCC pin, as
a
reaches 12V, the
CC
FPS™ begins switching and the internal high-voltage
current source is disabled. The FPS continues its
normal switching operation and the power is supplied
from the auxiliary transformer winding unless V
goes
CC
below the stop voltage of 8V.
V
DC
C
a
8V/12V
V
CC
25
I
CH
VCC good
V
str
V
ref
Internal
FSQ0365RN Rev.00
Bias
Figure 20. Startup Circuit
2. Feedback Control: FPS employs Current Mode
control, as shown in Figure 21. An opto-coupler (such as
FOD817A) and shunt regulator (such as KA431) are
FOD817A
KA431
V
FB
C
B
V
O
FSQ0365RN Rev. 00
Figure 21. Pulse-Width-Modulation (PWM) Circuit
3. Synchronization: The FSQ-series employs a valley
switching technique to minimize the switching noise and
loss. The basic waveforms of the valley switching
converter are shown in Figure 22. To minimize the
MOSFET's switching loss, the MOSFET should be
turned on when the drain voltage reaches its minimum
value, as shown in Figure 22. The minimum drain
voltage is indirectly detected by monitoring the V
winding voltage, as shown in Figure 22.
V
ds
V
DC
V
V
ref
CC
I
delay
3
V
SD
I
D1D2
V
FB
Gate
driver
SenseFET
R
sense
OSC
3R
+
*
FB
R
-
OLP
CC
V
RO
V
RO
often used to implement the feedback network.
Comparing the feedback voltage with the voltage across
the R
resistor makes it possible to control the
SENSE
switching duty cycle. When the reference pin voltage of
V
sync
t
F
V
(6V)
ovp
the shunt regulator exceeds the internal reference
voltage of 2.5V, the opto-coupler LED current increases,
pulling down the feedback voltage and reducing the duty
cycle. This event typically occurs when input voltage is
increased or output load is decreased.
2.1 Pulse-by-Pulse Current Limit: Because Current
MOSFET Gate
0.7V
0.2V
300ns Delay
Mode control is employed, the peak current through the
SenseFET is limited by the inverting input of PWM
comparator (V
*), as shown in Figure 21. Assuming
FB
ONON
that the 0.9mA current source flows only through the
internal resistor (3R + R = 2.8kΩ), the cathode voltage
of diode D2 is about 2.5V. Since D1 is blocked when the
feedback voltage (V
) exceeds 2.5V, the maximum
FB
voltage of the cathode of D2 is clamped at this voltage,
clamping V
*. Therefore, the peak value of the current
FB
through the SenseFET is limited.
2.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
usually occurs through the SenseFET, caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. Excessive voltage across the R
sense
resistor would lead to incorrect feedback operation in the
Current Mode PWM control. To counter this effect, the
FPS employs a leading-edge blanking (LEB) circuit. This
circuit inhibits the PWM comparator for a short time
(t
4. Protection Circuits: The FSQ-series has several
self-protective functions, such as Overload Protection
(OLP), Abnormal Over-Current protection (AOCP),
Over-Voltage Protection (OVP), and Thermal Shutdown
(TSD). All the protections are implemented as AutoRestart Mode. Once the fault condition is detected,
switching is terminated and the SenseFET remains off.
This causes V
Under-Voltage Lockout (UVLO) stop voltage of 8V, the
to fall. When VCC falls down to the
CC
protection is reset and the startup circuit charges the
V
capacitor. When the VCC reaches the start voltage
CC
of 12V, the FSQ-series resumes normal operation. If the
fault condition is not removed, the SenseFET remains
off and V
drops to stop voltage again. In this manner,
CC
FSQ0365RN Rev.00
the auto-restart can alternately enable and disable the
switching of the power SenseFET until the fault
condition is eliminated. Because these protection
circuits are fully integrated into the IC without external
components, the reliability is improved without
increasing cost.
V
FB
6.0V
FSQ0365RN Rev.00
FSQ0365/0265/0165/321 — Green Mode Fairchild Power Switch (FPS™) for Valley Switching Converter
Overload protection
Fault
V
V
12V
8V
Power
DS
on
CC
occurs
Fault
removed
t
FSQ0365RN Rev. 00
Normal
operation
Fault
situation
Normal
operation
Figure 23. Auto-Restart Protection Waveforms
4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding its normal level due to an
unexpected abnormal event. In this situation, the
protection circuit should trigger to protect the SMPS.
However, even when the SMPS is in the normal
operation, the overload protection circuit can be
triggered during load transition. To avoid this undesired
operation, the overload protection circuit is designed to
trigger only after a specified time to determine whether it
is a transient situation or a true overload situation.
Because of the pulse-by-pulse current limit capability,
the maximum peak current through the SenseFET is
limited, and therefore the maximum input power is
restricted with a given input voltage. If the output
consumes more than this maximum power, the output
voltage (V
) decreases below the set voltage. This
O
reduces the current through the opto-coupler LED,
which also reduces the opto-coupler transistor current,
thus increasing the feedback voltage (V
). If VFB
FB
exceeds 2.8V, D1 is blocked and the 5µA current source
starts to charge CB slowly up to V
V
continues increasing until it reaches 6V, when the
FB
. In this condition,
CC
switching operation is terminated, as shown in Figure
24. The delay for shutdown is the time required to
charge CB from 2.8V to 6V with 5µA. A 20 ~ 50ms delay
is typical for most applications.
2.8V
t12= CFB*(6.0-2.8)/I
t
1
delay
t
t
2
Figure 24. Overload Protection
4.2 Abnormal Over-Current Protection (AOCP)
: When
the secondary rectifier diodes or the transformer pins
are shorted, a steep current with extremely high-di/dt
can flow through the SenseFET during the LEB time.
Even though the FSQ-series has Overload Protection
(OLP), it is not enough to protect the FSQ-series in that
abnormal case, since severe current stress is imposed
on the SenseFET until OLP triggers. The FSQ-series
has an internal Abnormal Over-Current Protection
(AOCP) circuit as shown in Figure 25. When the gate
turn-on signal is applied to the power SenseFET, the
AOCP block is enabled and monitors the current
through the sensing resistor. The voltage across the
resistor is compared with a preset AOCP level. If the
sensing resistor voltage is greater than the AOCP level,
the set signal is applied to the latch, resulting in the
shutdown of the SMPS.
FSQ0365/0265/0165/321 — Green Mode Fairchild Power Switch (FPS™) for Valley Switching Converter
4.3 Over-Voltage Protection (OVP): If the secondary-
side feedback circuit malfunctions or a solder defect
causes an opening in the feedback path, the current
through the opto-coupler transistor becomes almost
zero. Then V
climbs up in a similar manner to the
FB
overload situation, forcing the preset maximum current
to be supplied to the SMPS until the overload protection
triggers. Because more energy than required is provided
to the output, the output voltage may exceed the rated
voltage before the overload protection triggers, resulting
in the breakdown of the devices in the secondary side.
To prevent this situation, an OVP circuit is employed. In
general, the peak voltage of the sync signal is
proportional to the output voltage and the FSQ-series
uses a sync signal instead of directly monitoring the
output voltage. If the sync signal exceeds 6V, an OVP is
triggered, shutting down the SMPS. To avoid undesired
triggering of OVP during normal operation, the peak
voltage of the sync signal should be designed below 6V.
4.4 Thermal Shutdown (TSD): The SenseFET and the
control IC are built in one package. This makes it easy
for the control IC to detect the abnormal over
temperature of the SenseFET. If the temperature
exceeds ~150°C, the thermal shutdown triggers.
5. Soft-Start: An internal soft-start circuit increases
PWM comparator inverting input voltage with the
SenseFET current slowly after it starts up. The typical
soft-start time is 15ms. The pulsewidth to the power
switching device is progressively increased to establish
the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased with the intention
of smoothly establishing the required output voltage.
This helps prevent transformer saturation and reduces
stress on the secondary diode during startup.
6. Burst Operation: To minimize power dissipation in
Standby Mode, the FPS enters Burst-Mode operation.
As the load decreases, the feedback voltage decreases.
As shown in Figure 26, the device automatically enters
Burst Mode when the feedback voltage drops below
V
(350mV). At this point, switching stops and the
BURL
output voltages start to drop at a rate dependent on
standby current load. This causes the feedback voltage
to rise. Once it passes V
(550mV), switching
BURH
resumes. The feedback voltage then falls and the
process repeats. Burst Mode alternately enables and
disables switching of the power SenseFET, reducing
switching loss in Standby Mode.
V
O
set
V
O
V
FB
0.55V
0.35V
I
DS
V
DS
time
t4
FSQ0365RN Rev.00
Switching
disabled
t1
t2 t3
Switching
disabled
Figure 26. Waveforms of Burst Operation
7. Switching Frequency Limit
: To minimize switching
loss and Electromagnetic Interference (EMI), the
MOSFET turns on when the drain voltage reaches its
minimum value in valley switching operation. However,
this causes switching frequency to increases at light
load conditions. As the load decreases, the peak drain
current diminishes and the switching frequency
increases. This results in severe switching losses at
light-load condition, as well as intermittent switching and
audible noise. Because of these problems, the valley
switching converter topology has limitations in a wide
range of applications.
To overcome this problem, FSQ-series employs a
frequency-limit function, as shown in Figure 27 and
Figure 28. Once the SenseFET is turned on, the next
turn-on is prohibited during the blanking time (t
). After
B
the blanking time, the controller finds the valley within
the detection time window (t
) and turns on the
W
MOSFET, as shown in Figure 27 and Figure 28 (cases
A, B, and C). If no valley is found during t
SenseFET is forced to turn on at the end of t
, the internal
W
(case D).
W
Therefore, FSQ devices have a minimum switching
frequency of 55kHz and a maximum switching frequency
of 67kHz, as shown in Figure 28.
FSQ0365/0265/0165/321 — Green Mode Fairchild Power Switch (FPS™) for Valley Switching Converter
]
PIN #1
.021
0.53
.015
0.37
[
.001[.025]
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MS-001,
VARIATIONS BA
B. CONTROLING DIMENSIONS ARE IN INCHES
REFERENCE DIMENSIONS ARE IN MILLIMETERS
C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS SHALL NOT EXCEED
.010 INCHES OR 0.25MM.
E. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M-1994.
[5.33]
(.032) [R0.813]
PIN #1
.310±.010 [7.87±0.25]
7° TYP
TOP VIEW
OPTION 2
.060 MAX
[1.52]
+.005
.010
-.000
.300
[7.62]
.430 MAX
[10.92]
0.254
[
+0.127
-0.000
]
.250±.005 [6.35±0.13]
TOP VIEW
OPTION 1
.070
.045
7° TYP
C
]
C
.100
[2.54]
B
1.78
1.14
[
]
.130±.005 [3.3±0.13]
.015 MIN
[0.38]
.140
3.55
[
.125
3.17
.210 MAX
]
N08EREVG
Figure 31. 8-Lead , Dual Inline Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
FSQ0365/0265/0165/321 — Green Mode Fairchild Power Switch (FPS™) for Valley Switching Converter
MKT-MLSOP08ArevA
Figure 32. 8-Lead , MLSOP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: