The FSL146MRBN is an integrated Pulse Width
Modulation (PWM) controller and SenseFET designed
for offline Switch-Mode Power Supplies (SMPS) with
minimal external components. The PWM controller
includes an integrated fixed-frequency oscillator, UnderVoltage Lockout (UVLO), Leading-Edge Blanking (LEB),
optimized gate driver, internal soft-start, temperaturecompensated precise current sources for loop
compensation, and self-protection circuitry. Compared
with a discrete MOSFET and PWM controller solution,
the FSL146MRBN can reduce total cost, component
count, size, and weight; while simultaneously increasing
efficiency, productivity, and system reliability. This
device provides a basic platform suited for cost-effective
design of a flyback converter.
FSL146MRBN — Green-Mode Fairchild Power Switch (FPS™)
April 2012
Applications
Power Supply for LCD Monitor, STB, and
DVD Combination
Ordering Information
Output Power Table
Operating
Part Number Package
Junction
Temperature
FSL146MRBN 8-DIP
Notes:
1. Lead-free package per JEDEC J-STD-020B.
2. The junction temperature can limit the maximum output power.
3. 230V
4. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.
5. Maximum practical continuous power in an open-frame design at 50C ambient temperature.
FSL146MRBN — Green-Mode Fairchild Power Switch (FPS™)
Figure 3. Pin Configuration (Top View)
Pin # Name Description
1 GND
2 VCC
3 FB
4 N.C. No Connection
5, 6, 7, 8 Drain
Ground. This pin is the control ground and the SenseFET source.
Power Supply. This pin is the positive supply input, which provides the internal operating
current for both startup and steady-state operation.
Feedback. This pin is internally connected to the inverting input of the PWM comparator.
The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor
should be placed between this pin and GND. If the voltage of this pin reaches 7.0V, the
overload protection triggers, which shuts down the FPS™.
SenseFET Drain. High-voltage power SenseFET drain connection.
FSL146MRBN — Green-Mode Fairchild Power Switch (FPS™)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
V
Drain Pin Voltage 650 V
DS
V
V
CC
V
FB
I
Drain Current Pulsed 3.4 A
DM
I
Continuous Switching Drain Current
DS
EAS Single Pulsed Avalanche Energy
PD
T
J
T
STG
ESD
Notes:
6. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (D
and junction temperature (see Figure 4).
7. L=45mH, starting T
8. Infinite cooling condition (refer to the SEMI G30-88).
9. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.
Pin Voltage 26 V
CC
Feedback Pin Voltage
Total Power Dissipation (TC=25C)
Maximum Junction Temperature
Operating Junction Temperature
(9)
Storage Temperature
Electrostatic
Discharge Capability
=25C.
J
Human Body Model, JESD22-A114 5
Charged Device Model, JESD22-C101 2
T
=25C
(6)
C
TC=100C
(7)
250 mJ
(8)
-0.3
10.0 V
1.7 A
1.1 A
1.5 W
150
-40
-55
+125
+150
MAX
C
C
C
kV
=0.73)
Figure 4. Repetitive Peak Switching Current
Thermal Impedance
TA=25°C unless otherwise specified.
SymbolParameterValueUnit
JA Junction-to-Ambient Thermal Impedance
JL Junction-to-Lead Thermal Impedance
Notes:
10. JEDEC recommended environment, JESD51-2 and test board, JESD51-10 with minimum land pattern.
11. Measured on the SOURCE pin #7, close to the plastic interface.
1. Startup: At startup, an internal high-voltage current
source supplies the internal bias and charges the
external capacitor (C
illustrated in Figure 17. When V
FSL146MRBN begins switching and the internal highvoltage current source is disabled. The FSL146MRBN
continues normal switching operation and the power is
supplied from the auxiliary transformer winding unless
V
goes below the stop voltage of 7.5V.
CC
Figure 17. Startup Block
2. Soft-Start: The internal soft-start circuit increases
PWM comparator inverting input voltage, together with
the SenseFET current, slowly after it starts. The typical
soft-start time is 15ms. The pulse width to the power
switching device is progressively increased to establish
the correct working conditions for transformers,
inductors, and capacitors. The voltage on the output
capacitors is progressively increased to smoothly
establish the required output voltage. This helps prevent
transformer saturation and reduces stress on the
secondary diode during startup.
) connected to the VCC pin, as
Vcc
reaches 12V, the
CC
3. Feedback Control: This device employs CurrentMode control, as shown in Figure 18. An opto-coupler
(such as the FOD817) and shunt regulator (such as the
KA431) are typically used to implement the feedback
network. Comparing the feedback voltage with the
voltage across the R
resistor makes it possible to
SENSE
control the switching duty cycle. When the reference pin
voltage of the shunt regulator exceeds the internal
reference voltage of 2.5V, the opto-coupler LED current
increases, pulling down the feedback voltage and
reducing drain current. This typically occurs when the
input voltage is increased or the output load is decreased.
3.1 Pulse-by-Pulse Current Limit: Because CurrentMode control is employed, the peak current through
the SenseFET is limited by the inverting input of the
PWM comparator (V
*), as shown in Figure 18.
FB
Assuming that the 90A current source flows only
through the internal resistor (3R + R =27k), the
cathode voltage of diode D2 is about 2.5V. Since D1
is blocked when the feedback voltage (VFB) exceeds
2.5V, the maximum voltage of the cathode of D2 is
clamped at this voltage. Therefore, the peak value of
the current through the SenseFET is limited.
3.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
usually occurs through the SenseFET, caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. Excessive voltage across the R
SENSE
resistor leads to incorrect feedback operation in the
Current-Mode PWM control. To counter this effect, the
leading-edge blanking (LEB) circuit inhibits the PWM
comparator for t
(300ns) after the SenseFET is
LEB
turned on.
FSL146MRBN — Green-Mode Fairchild Power Switch (FPS™)
4. Protection Circuits: The self-protective functions
include: Overload Protection (OLP), Abnormal OverCurrent Protection (AOCP), Output-Short Protection
(OSP), Over-Voltage Protection (OVP), and Thermal
Shutdown (TSD). All the protections are implemented as
Auto Restart Mode. Once the fault condition is detected,
switching is terminated and the SenseFET remains off.
This causes V
to fall. When VB
CC
B falls to the Under-
CC
Voltage Lockout (UVLO) stop voltage of 7.5V, the
protection is reset and the startup circuit charges the
capacitor. When VCC reaches the start voltage of
V
CC
12.0V, normal operation resumes. If the fault condition
is not removed, the SenseFET remains off and VCC
drops to stop voltage again. In this manner, the AutoRestart can alternately enable and disable the switching
of the power SenseFET until the fault condition is
eliminated. Because these protection circuits are fully
integrated into the IC without external components, the
reliability is improved without increasing cost.
Fault
Fault
removed
Normal
operation
t
V
V
12.0V
7.5V
Power
DS
on
CC
operation
Fault
occurs
Normal
situation
Figure 19. Auto-Restart Protection Waveforms
4.1 Overload Protection (OLP): Overload is defined
as the load current exceeding its normal level due to
an unexpected abnormal event. In this situation, the
protection circuit should trigger to protect the SMPS.
However, in normal operation, the overload protection
circuit can be triggered during load transition. To
avoid this undesired operation, the overload
protection circuit is designed to trigger only after a
specified time to determine whether it is a transient
situation or a true overload situation. Because of the
pulse-by-pulse current-limit capability, the maximum
peak current through the SenseFET is limited and,
therefore, the maximum input power is restricted with
a given input voltage. If the output consumes more
than this maximum power, the output voltage (V
OUT
)
decreases below the set voltage. This reduces the
current through the opto-coupler LED, which also
reduces the opto-coupler transistor current, thus
increasing the feedback voltage (VFB). If VFB exceeds
2.5V, D1 is blocked and the 2.0µA current source
starts to charge C
slowly up. In this condition, VFB
FB
continues increasing until it reaches 7.0V, when the
switching operation is terminated, as shown in Figure
20. The delay for shutdown is the time required to
charge C
from 2.5V to 7.0V with 2.0µA. A 25 ~
FB
50ms delay is typical for most applications. This
protection is implemented in Auto-Restart Mode.
Figure 20. Overload Protection
4.2 Abnormal Over-Current Protection (AOCP):
When the secondary rectifier diodes or the
transformer pins are shorted, a steep current with
extremely high di/dt can flow through the SenseFET
during the minimum turn-on time. Even though the
FSL146MRBN has overload protection, it is not
enough to protect the FSL146MRBN in that abnormal
case; since severe current stress is imposed on the
SenseFET until OLP is triggered. The internal AOCP
circuit is shown in Figure 21. When the gate turn-on
signal is applied to the power SenseFET, the AOCP
block is enabled and monitors the current through the
sensing resistor. The voltage across the resistor is
compared with a preset AOCP level. If the sensing
resistor voltage is greater than the AOCP level, the
set signal is applied to the S-R latch, resulting in the
shutdown of the SMPS.
Figure 21. Abnormal Over-Current Protection
FSL146MRBN — Green-Mode Fairchild Power Switch (FPS™)
4.3. Output-Short Protection (OSP): If the output is
shorted, steep current with extremely high di/dt can
flow through the SenseFET during the minimum turnon time. Such a steep current brings high-voltage
stress on the drain of the SenseFET when turned off.
OSP protects the device from this abnormal condition.
It is comprised of detecting V
on time. When the V
is higher than 2.0V and the
FB
and SenseFET turn-
FB
SenseFET turn-on time is lower than 1.0s, this
condition is recognized as an abnormal error and
PWM switching shuts down until V
reaches V
CC
again. An abnormal condition output short is shown in
Figure 22.
START
5. Soft Burst-Mode Operation: To minimize power
dissipation in Standby Mode, the FSL146MRBN enters
Burst-Mode operation. As the load decreases, the
feedback voltage decreases. As shown in Figure 23, the
device automatically enters Burst Mode when the
feedback voltage drops below V
(350mV). At this
BURL
point, switching stops and the output voltages start to
drop at a rate dependent on the standby current load.
This causes the feedback voltage to rise. Once it
passes V
feedback voltage then falls and the process repeats.
(500mV), switching resumes. The
BURH
Burst Mode alternately enables and disables switching
of the SenseFET, thereby reducing switching loss in
Standby Mode.
FSL146MRBN — Green-Mode Fairchild Power Switch (FPS™)
Figure 22. Output-Short Protection
4.4 Over-Voltage Protection (OVP): If the
secondary-side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path,
the current through the opto-coupler transistor
becomes almost zero. Then V
climbs up in a similar
FB
manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is triggered. Because more
energy than required is provided to the output, the
output voltage may exceed the rated voltage before
the overload protection is triggered, resulting in the
breakdown of the devices in the secondary side. To
prevent this situation, an OVP circuit is employed. In
general, the V
and the FSL146MRBN uses V
monitoring the output voltage. If V
is proportional to the output voltage
CC
instead of directly
CC
exceeds 24.5V,
CC
an OVP circuit is triggered, resulting in the termination
of the switching operation. To avoid undesired
activation of OVP during normal operation, V
should
CC
be designed to be below 24.5V.
4.5 Thermal Shutdown (TSD): The SenseFET and
the control IC on a die in one package make it easier
for the control IC to detect the over temperature of the
SenseFET. If the temperature exceeds ~135C, the
thermal shutdown is triggered and stops operation.
The FSL146MRBN operates in Auto-Restart Mode
until the temperature decreases to around 75C,
when normal operation resumes.
Figure 23. Burst Mode Operation
6. Random Frequency Fluctuation (RFF): Fluctuating
switching frequency of an SMPS can reduce EMI by
spreading the energy over a wide frequency range. The
amount of EMI reduction is directly related to the
switching frequency variation, which is limited internally.
The switching frequency is determined randomly by an
external feedback voltage and internal free-running
oscillator at every switching instant. RFF effectively
scatters the EMI noise around typical switching
frequency (67kHz) and can reduce the cost of the input
filter used to meet EMI requirements (e.g. EN55022).
Application Input Voltage Rated Output Rated Power
LCD Monitor
Power Supply
85 ~ 265V
AC
Key Design Notes:
1. The delay for overload protection is designed to be about 30ms with C105 (8.2nF). OLP time between 39ms
(12nF) and 46ms (15nF) is recommended.
2. The SMD-type capacitor (C106) must be placed as close as possible to the V
abrupt pulsating noises and to improve ESD and surge immunity. Capacitance between 100nF and 220nF
is recommended.
Schematic
5.0V (2A)
14.0V (1.2A)
26.8W
pin to avoid malfunction by
CC
FSL146MRBN — Green-Mode Fairchild Power Switch (FPS™)
FSL146MRBN — Green-Mode Fairchild Power Switch (FPS™)
9.83
9.00
6.67
6.096
8.255
7.61
1.65
1.27
3.60
3.00
3.683
3.20
0.356
0.20
5.08 MAX
0.33 MIN
(0.56)
2.54
0.56
0.355
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ES PER
ASME Y14.5M-1994
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
7.62
9.957
7.87
Figure 27. 8-Lead, MDIP, JEDEC MS-001, .300" Wide
Package drawings are provided as a se
manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
rvice to customers considering Fairchild components. Drawings may change in any