Fairchild FDS8962C service manual

± 20 ±
° C
θ
°
θ
°
FDS8962C Dual N & P-Channel PowerTrench
June 2006
FDS8962C Dual N & P-Channel PowerTrench
®
MOSFET
Features
Q1: N-Channel
7.0A, 30V R R
Q2: P-Channel
-5A, -30V R R
Fast switching speed
High power and handling capability in a widely used surface mount package
Absolute Maximum Ratings
= 0.030 Ω @ V
DS(on)
= 0.044 Ω @ V
DS(on)
= 0.052 Ω @ V
DS(on)
= 0.080 Ω @ V
DS(on)
D1
SO-8
D1
D2
Pin 1
D2
= 10V
GS
= 4.5V
GS
= -10V
GS
= -4.5V
GS
S1
G2
S2
G1
T
= 25°C unless otherwise noted
A
General Description
These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state ressitance and yet maintain superior switching performance.
These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required.
Q2
5
6
Q1
7
8
4
3
2
1
Symbol Parameter Q1 Q2 Units
V
DSS
V
GSS
I
D
P
D
T
, T
J
Thermal Characteristics
R
JA
R
JC
Drain-Source Voltage 30 -30 V
Gate-Source Voltage
Drain Current – Continuous (Note 1a) 7 -5 A
– Pulsed 20 -20
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
Operating and Storage Junction Temperature Range -55 to +150
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 78
Thermal Resistance, Junction-to-Case (Note 1) 40
20 V
C/W
C/W
®
MOSFET
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS8962C FDS8962C 13” 12mm 2500 units
©2005 Fairchild Semiconductor Corporation
FDS8962C Rev. A1
1
www.fairchildsemi.com
µ
Electrical Characteristics
T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
DSS
BV
∆ T
I
DSS
I
GSSF
I
GSSR
On Characteristics (Note 2)
V
GS(th)
GS(th)
V
∆ T
R
DS(on)
I
D(on)
g
FS
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Switching Characteristics (Note 2)
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Drain-Source Breakdown Voltage V
DSS
Breakdown Voltage Temperature Coefficient
J
Zero Gate Voltage Drain Current V
Gate-Body Leakage, Forward V
Gate-Body Leakage, Reverse V
Gate Threshold Voltage V
Gate Threshold Voltage Temperature Coefficient
J
Static Drain-Source On-Resistance
On-State Drain Current V
Forward Transconductance V
= 0 V, I
GS
V
= 0 V, I
GS
I
= 250 µ A, Referenced to 25 ° C
D
I
= -250 µA, Referenced to 25 ° C
D
= 24 V, V
DS
V
= -24 V, V
DS
= 20 V, V
GS
= -20 V, V
GS
= V
DS
V
= V
DS
I
= 250 µ A, Referenced to 25 ° C
D
I
= -250 µA, Referenced to 25 ° C
D
V
= 10 V, I
GS
V
= 10 V, I
GS
V
= 4.5 V, I
GS
V
= -10 V, I
GS
V
= -10 V, I
GS
V
= -4.5 V, I
GS
= 10 V, V
GS
V
= -10 V, V
GS
= 5 V, I
DS
V
= -5 V, I
DS
= 250 µ A
D
= -250 µ A
D
= 0 V
GS
= 0 V
GS
= 0 V All 100 nA
DS
= 0 V All -100 nA
DS
, I
= 250 µ A
GS
D
, I
= -250 µA
GS
D
= 7 A
D
= 7 A, T
D
= 6 A
D
= -5 A
D
= -5 A, T
D
D
DS
DS
= 7 A
D
=-5 A
D
= -4 A
= 5 V
= -5 V
= 125 ° C
J
J
Input Capacitance Q1
V
= 15 V, V
DS
Output Capacitance Q1
Reverse Transfer Capacitance Q1
Gate Resistance V
Q2 V
= -15 V, V
DS
= 15 mV, f = 1.0 MHz Q1
GS
= 0 V, f = 1.0 MHz
GS
= 0 V, f = 1.0 MHz
GS
Tu r n-On Delay Time Q1
V
= 15 V, I
DD
Tu r n-On Rise Time Q1
VGS = 10V, R
= 1 A,
D
GEN
= 6
Q2
Tu r n-Off Delay Time Q1
VDD = -15 V, ID = -1 A, VGS = -10V, R
GEN
= 6
Tu r n-Off Fall Time Q1
Total Gate Charge Q1
VDS = 15 V, ID = 7 A, VGS = 10 V
Gate-Source Charge Q1
Q2 VDS = -15 V, ID = -5 A,VGS = -10 V
Gate-Drain Charge Q1
= 125 ° C
Q1 Q2
Q1 Q2
30
-30
25
-23
Q1 Q2
Q1 Q2
Q1 Q2
1
1.9
-1
-1.7
-4.5
4.5
Q1 21
29 26
Q2 42
57 65
Q1 Q2
Q1 Q2
Q1 Q2
20
-20
25 10
575 528
145
Q2
132
65
Q2
70
2.1
Q2
6.0
Q1 Q2
Q2
13
23
Q2
14
Q2
Q1 Q2
10.7
9.6
1.7
Q2
2.2
2.1
Q2
1.7
mV/ ° C
1
-1
3
-3
mV/ ° C
30
m Ω 46 44
52 78 80
pF
pF
pF
8 7
5
16 14
10
ns
ns
24
37
ns
25
3 9
17
26
6
ns
nC
13
nC
nC
FDS8962C Dual N & P-Channel PowerTrench
V
A
V
®
MOSFET
A
S
FDS8962C Rev. A1
2
www.fairchildsemi.com
FDS8962C Dual N & P-Channel PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted (Continued)
A
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
t
rr
Q
rr
Notes:
Notes:
1. R
θJA
R
θJC
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
Maximum Continuous Drain-Source Diode Forward Current Q1
Q2
Drain-Source Diode Forward Voltage
Diode Reverse Recovery Time Q1
Diode Reverse Recovery Charge Q1
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. is guaranteed by design while R
a) 78°/W when mounted
is determined by the user's board design.
θCA
2
on a 0.5 in copper
pad of 2 oz
VGS = 0 V, IS = 1.3 A (Note 2) VGS = 0 V, IS = -1.3 A (Note 2)
IF = 7 A, diF/dt = 100 A/µs Q2 IF = -5 A, diF/dt = 100 A/µs
b) 125°/W when mounted
on a .02 in copper
2
pad of 2 oz
Q1 Q2
Q1 Q2
Q2
0.75
-0.88
19 19
1.3
-1.3
1.2
-1.2
9 6
c) 135°/W when mounted
on a minimum pad.
nS
nC
A
V
®
MOSFET
FDS8962C Rev. A1
3 www.fairchildsemi.com
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