Fairchild FDS8949 service manual
tm
October 2006
FDS8949
Dual N-Channel Logic Level PowerTrench® MOSFET
40V, 6A, 29mΩ
Features
Max r
Max r
Low gate charge
High performance trench technology for extremely low
r
DS(on)
High power and current handling capability
RoHS compliant
DS(on)
DS(on)
= 29mΩ at V
= 36mΩ at V
D2
D1
D1
GS
GS
D2
= 10V
= 4.5V
General Description
These N-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor’s advanced
PowerTrench® process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Applications
Inverter
Power suppliers
FDS8949 Dual N-Channel Logic Level PowerTrench
SO-8
Pin 1
S1
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
E
AS
P
D
, T
T
J
STG
Drain to Source Voltage 40 V
Gate to Source Voltage ±20 V
Drain Current -Continuous (Note 1a) 6
-Pulsed 20
Drain-Source Avalanche Energy (Note 3) 26 mJ
Power Dissipation for Dual Operation 2
Power Dissipation for Single Operation (Note 1a)
(Note 1b)
Operating and Storage Junction Temperature Range -55 to 150 °C
G2
S2
G1
= 25°C unless otherwise noted
A
1.6
0.9
Thermal Characteristics
R
θJA
θJA
R
θJC
Thermal Resistance-Single operation, Junction to Ambient (Note 1a) 81
Thermal Resistance-Single operation, Junction to Ambient (Note 1b) 135
Thermal Resistance, Junction to Case (Note 1) 40
Package Marking and Ordering Information
Device Marking Device Reel Size Tape Width Quantity
FDS8949 FDS8949 13’’ 12mm 2500 units
®
MOSFET
A
W
°C/WR
©2006 Fairchild Semiconductor Corporation
FDS8949 Rev. B1
www.fairchildsemi.com1
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
FDS8949 Dual N-Channel Logic Level PowerTrench
Off Characteristics
BV
∆BV
∆T
I
DSS
I
GSS
DSS
DSS
J
Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 40 V
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current VGS = ±20V,V
On Characteristics
V
GS(th)
∆V
∆T
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1 1.9 3 V
Gate to Source Threshold Voltage
Temperature Coefficient
Drain to Source On Resistance
Forward Transconductance VDS = 10V,ID = 6A 22 S
(Note 2)
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance 105 140 pF
Reverse Transfer Capacitance 60 90 pF
Gate Resistance f = 1MHz 1.1 Ω
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
g
gs
gd
Turn-On Delay Time
Rise Time 5 10 ns
Turn-Off D elay Time 23 37 ns
Fall Time 3 6 ns
Total Gate Charge
Gate to Source Gate Charge 2.4 nC
Gate to Drain “Miller”Charge 2.8 nC
ID = 250µA, referenced to 25°C 33 mV/°C
V
= 32V, V
DS
= 0V 1 µA
GS
TJ = 55°C 10 µA
= 0V ±100 nA
DS
ID = 250µA, referenced to 25°C -4.6 mV/°C
VGS = 10V, ID = 6A 21 29
mΩVGS = 4.5V, ID = 4.5A 26 36
VGS = 10V, ID = 6A,TJ = 125°C 29 43
VDS = 20V, VGS = 0V,
715 955 pF
f = 1MHz
VDD = 20V, ID = 1A
VGS = 10V, R
GEN
= 6Ω
9 18 ns
7.7 11 nC
VDS = 20V, ID = 6A,VGS = 5V
®
MOSFET
Drain-Source Diode Characteristics
V
SD
t
rr
Q
rr
Notes:
1: R
θJA
drain pins. R
2: Pulse Test: Pulse Width < 300 us, Duty Cycle < 2.0%.
3: Starting T
FDS8949 Rev. B1 www.fairchildsemi.com2
Source to Drain Diode Forward Voltage V
Reverse Recovery Time (note 3)
Reverse Recovery Charge 7 11 nC
is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
is guaranteed by design while R
θJC
= 25°C, L = 1mH, IAS = 7.3A, VDD = 40V, VGS = 10V.
J
is determined by the user’s board design.
θJA
a) 81°C/W wh en
mounted on a 1in
pad of 2 oz copper
Scale 1:1 on letter size paper
and Maximum Ratings
= 0V, IS = 6A (note 2) 0.8 1.2 V
GS
IF = 6A, diF/dt = 100A/µs
2
17 26 ns
b) 135°C/W when mounted on a
minimum pad .
Loading...