Fairchild FDS8928A service manual

FDS8928A
Dual N & P-Channel Enhancement Mode Field Effect Transistor

General Description Features

These dual N- and P -Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other battery powered circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.

N-Channel 5.5 A,30 V, R
R
P-Channel -4 A,-20 V, R
R

=0.030 Ω @ VGS=4.5 V

DS(ON)

DS(ON)

=0.055 Ω @ VGS=-4.5 V

DS(ON)

DS(ON)

High density cell design for extremely low R
High power and current handling capability in a widely used

surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.

July 1998

=0.038 Ω @ VGS=2.5 V.
=0.072 Ω @ VGS=-2.5 V.

.

DS(ON)

SuperSOTTM-6

SOIC-16SOT-23 SuperSOTTM-8 SO-8 SOT-223

D1

D1

D2

D2

FDS

8928A

5

6

7

3
2

G2

SO-8

pin 1

G1

S1

Absolute Maximum Ratings T

S2

= 25°C unless otherwise noted

A

8

Symbol Parameter N-Channel P-Channel Units

V

DSS

V

GSS

I

D

Drain-Source Voltage 30 -20 V
Gate-Source Voltage 8 -8 V
Drain Current - Continuous (Note 1a) 5.5 -4 A

- Pulsed 20 -20

P

D

Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9

TJ,T

Operating and Storage Temperature Range -55 to 150 °C

STG

THERMAL CHARACTERISTICS

R

θJA

R

θ

JC

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W

141

© 1998 Fairchild Semiconductor Corporation

FDS8928A Rev. B

Electrical Characteristics (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Type Min Typ Max Units
OFF CHARACTERISTICS

BV

∆BV

I

DSS

I

GSSF

I

GSSR

DSS

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 30 V

VGS = 0 V, ID = -250 µA

Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC N-Ch 32 mV/oC

/∆T

J

ID = -250 µA, Referenced to 25 oC

Zero Gate Voltage Drain Current VDS = 24 V, V

VDS = -16 V, V

= 0 V N-Ch 1 µA

GS

= 0 V

GS

P-Ch -20 V

P-Ch -23

P-Ch -1 µA
Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V All 100 nA
Gate - Body Leakage, Reverse

VGS = -8 V, V

DS

= 0 V

All -100 nA

ON CHARACTERISTICS (Note 2)

V

∆V

R

I

D(on)

GS(th)

GS(th)

DS(ON)

Gate Threshold Voltage

Gate Threshold Voltage Temp. Coefficient

/∆T

J

Static Drain-Source On-Resistance

On-State Drain Current

V

= VGS, ID = 250 µA

DS

V

= VGS, ID = -250 µA

DS

ID = 250 µA, Referenced to 25 oC
ID = -250 µA, Referenced to 25 oC
V

= 4.5 V, ID = 5.5 A

GS

V

= 2.5 V, ID = 4.5 A 0.031 0.038

GS

V

= -4.5 V, ID = -4 A

GS

V

= -2.5 V, ID = -3.4 A 0.059 0.072

GS

VGS = 4.5 V, VDS= 5 V

N-Ch 0.4 0.67 1 V

P-Ch -0.4 -0.6 -1 V

N-Ch -3

mV/oC
P-Ch 4
N-Ch 0.025 0.03

P-Ch 0.043 0.055

N-Ch 20 A

Ω

VGS = -4.5 V, VDS= -5 V P-Ch -20

g

FS

Forward Transconductance

VDS = 5 V, I D = 5.5 A

N-Ch 20 S

VDS = -5 V, I D = -4 A P-Ch 13 S

DYNAMIC CHARACTERISTICS

C

iss

C

oss

Input Capacitance

VDS = 10 V, VGS = 0 V,
f = 1.0 MHz

Input Capacitance N-Ch 410 pF

VDS = -10 V, VGS = 0 V,

C

rss

Reverse Transfer Capacitance N-Ch 110 pF

f = 1.0 MHz

N-Ch 900 pF
P-Ch 1130

P-Ch 480

P-Ch 120

FDS8928A Rev. B

Electrical Characteristics (continued)

SWITCHING CHARACTERISTICS (Note 2)
Symbol Parameter Conditions Type Min Typ Max Units

t

D(on)

t

r

t

D(off)

t

f

Q

g

Q

gs

Q

gd

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1. R

JA

θ

design while R

Turn - On Delay Time V

= 6 V, I D = 1 A N-Ch 6 12 ns

DS

VGS = 4.5 V , R

GEN

= 6 Ω

P-Ch 8 16

Turn - On Rise Time N-Ch 19 31 ns

P-Ch 23 37

Turn - Off Delay Time VDS= -10 V, I D = -1 A N-Ch 42 67 ns

VGS = -4.5 V , R

GEN

= 6 Ω

P-Ch 260 360

Turn - Off Fall Time N-Ch 13 24 ns

P-Ch 90 125

Total Gate Charge

VDS = 10 V, I D = 5.5 A,
VGS = 4.5 V

N-Ch 19.8 28 nC
P-Ch 20 28

Gate-Source Charge N-Ch 2 nC

VDS = -5 V, I D = -4 A, P-Ch 2.8

Gate-Drain Charge

VGS = -5 V

N-Ch 6.3 nC
P-Ch 3.2

Maximum Continuous Drain-Source Diode Forward Current N-Ch 1.3 A

P-Ch -1.3 A

Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A

VGS = 0 V, IS = -1.3 A

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

is determined by the user's board design.

CA

θ

(Note 2) N-Ch 0.68 1.2 V

(Note 2)

P-Ch -0.7 -1.2 V

is guaranteed by

JC

θ

a. 78OC/W on a 0.5 in

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%..

pad of 2oz copper.

2

b. 125OC/W on a 0.02 in

pad of 2oz copper.

2

c. 135OC/W on a 0.003 in

pad of 2oz copper.

2

FDS8928A Rev. B