Fairchild FDS6912 service manual
FDS6912
Dual N-Channel Logic Level PWM Optimized PowerTrench
MOSFET
FDS6912
July 2000
General Description
These N-Channel Logic Level MOSFETs have been
designed specifically to improve the overall effic iency of
DC/DC converters using either synchronous or
conventional switching PWM controllers.
These MOSFETs feature faster switching and lower
gate charge than other MOSFETs with comparable
RDS(ON) specifications.
The result is a MOSFET that is easy and safer to drive
Features
6 A, 30 V. R
•
Optimized for use in switching DC/DC converters
•
with PWM controllers
Very fast switching.
•
Low gate charge
•
= 0.028 Ω @ VGS = 10 V
DS(ON)
R
= 0.042 Ω @ VGS = 4.5 V.
DS(ON)
(even at very high frequencies), and DC/DC power
supply designs with higher overall efficiency.
D1
D1
D2
D2
G1
S2
S1
G2
SO-8
Absolute Maximum Ratings
TA=25oC unless otherwise noted
5
Q1
6
7
Q2
8
4
3
2
1
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
stg
Drain-Source Voltage 30 V
Gate-Source Voltage
Drain Current – Continuous
(Note 1a)
25
±
6A
– Pulsed 20
Power Dissipation for Dual Operation 2
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
1.6
1
0.9
Operating and Storage Junction Temperature Range -55 to +150
V
W
C
°
Thermal Characteristics
R
JA
θ
R
JC
θ
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
40
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS6912 FDS6912 13’’ 12mm 2500 units
2000 Fairchild Semiconductor Corpor ation
C/W
°
C/W
°
FDS6912 Rev F (W)
FDS6912
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
∆
∆
I
DSS
I
GSSF
I
GSSR
DSS
BV
T
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
DSS
Coefficient
J
Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V
Gate–Body Leakage, Forward VGS = 25 V, VDS = 0 V 100 nA
Gate–Body Leakage, Reverse VGS = –25 V VDS = 0 V –100 nA
On Characteristics
V
∆
∆
R
I
D(on)
g
GS(th)
GS(th)
V
T
DS(on)
FS
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
J
Static Drain–Source
On–Resistance
On–State Drain Current VGS = 10 V, VDS = 5 V 20 A
Forward Transconductance VDS = 10 V, ID = 6 A 20 S
(Note 2)
= 0 V, ID = 250 µA
V
GS
I
= 250 µA, Referenced to 25°C
D
T
= VGS, ID = 250 µA
V
DS
= 250 µA, Referenced to 25°C
I
D
= 55°C
J
VGS = 10 V, ID = 6 A
T
= 125°C
J
VGS = 4.5 V, ID = 4.9 A 0.035 0.042
30 V
20
mV/°C
1
10
123 V
–5
0.024
0.034
mV/°C
0.028
0.048
Dynamic Characteristics
C
iss
C
oss
C
rss
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Input Capacitance 740 pF
Output Capacitance 170 pF
Reverse Transfer Capacitance
(Note 2)
Turn–On Delay Time 8 16 ns
Turn–On Rise Time 13 24 ns
V
= 15 V, V
DS
f = 1.0 MHz
= 15 V, ID = 1 A,
V
DD
= 10 V, R
V
GS
GS
GEN
= 0 V,
= 6
75 pF
Ω
Turn–Off Delay Time 18 29 ns
Turn–Off Fall Time
Total Gate Charge 7 10 nC
Gate–Source Charge 3.8 nC
V
= 10 V, ID = 6 A,
DS
= 5 V
V
GS
Gate–Drain Charge
816ns
2.5 nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
1.
JA
θ
the drain pins. R
Maximum Continuous Drain–Source Diode Forward Current 1.3 A
Drain–Source Diode Forward
VGS = 0 V, IS = 1.3 A
(Note 2)
0.75 1.2 V
Voltage
is guaranteed by design while R
JC
θ
is determined by the user's board design.
CA
θ
A
µ
Ω
a) 78°/W when
Scale 1 : 1 on letter size paper
Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
2.
mounted on a 0.5in
pad of 2 oz copper
2
b) 125°/W when
mounted on a 0.02
2
in
pad of 2 oz
copper
c) 135°/W when mounted on a
minimum mounting pad.
FDS6912 Rev E (W)
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