Fairchild FDS4897C service manual
FD
S
89
C
ua
&
C
a
e
o
e
e
c
OS
November 2005
FDS4897C
Dual N & P-Channel PowerTrench® MOSFET
General Description
These dual N- and P-Channel enhancement mode
power field effect transistors are produced using
Fairchild Semiconductor’s advanced PowerTrench
process that has been especially tailored to minimize
on-state resistance and yet maintain superior switching
performance.
Application
• Inverter
• Power Supplies
D2
D
D2
D
D1
D
D1
D
SO-8
Pin 1
SO-8
S1
G2
S2
G
G1
S
S
S
Features
• Q1: N-Channel
6.2A, 40V R
R
• Q2: P-Channel
–4.4A, –40V R
R
• High power handling capability in a widely used
surface mount package
• RoHS compliant
5
6
7
8
= 29mΩ @ VGS = 10V
DS(on)
= 36mΩ @ VGS = 4.5V
DS(on)
= 46mΩ @ VGS = –10V
DS(on)
= 63mΩ @ VGS = –4.5V
DS(on)
Q2
Q1
4
3
2
1
4
7
D
l N
Ph
nn
l P
w
rTr
n
h
®
M
FET
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter Q1 Q2 Units
V
Drain-Source Voltage 40 40 V
DSS
V
Gate-Source Voltage
GSS
ID Drain Current - Continuous (Note 1a) 6.2 –4.4 A
- Pulsed 20 –20
PD Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
TJ, T
STG
Operating and Storage Junction Temperature Range –55 to +150
(Note 1b)
(Note 1c)
±20 ±20
1
0.9
V
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a) 78
(Note 1) 40
°C/W
°C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS4897C FDS4897C 13” 12mm 2500 units
©2005 Fairchild Semiconductor Corporation
FDS4897C Rev C(W)
www.fairchildsemi.com
S
89
C
ua
&
C
a
e
o
e
e
c
OS
FD
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Avalanche Ratings (Note 3)
E
Drain-Source Avalanche
AS
I
Drain-Source Avalanche
AS
Energy (Single Pulse)
Current
VDD = 40 V, ID = 7.3 A, L = 1 mH Q1 27 mJ
= –40 V, ID =–8.7 A, L = 1 mH Q2 38 mJ
V
DD
Q1
Q2
7.3
–8.7
A
Off Characteristics
Q1
40
BV
Drain-Source Breakdown
DSS
ΔBVDSS
ΔT
I
Zero Gate Voltage Drain
DSS
I
Gate-Body Leakage
GSS
Voltage
Breakdown Voltage
Temperature Coefficient
J
Current
= 0 V, ID = 250 μA
V
GS
= 0 V, ID = –250 μA
V
GS
= 250 μA, Referenced to 25°C
I
D
= –250 µA, Referenced to 25°C
I
D
VDS = 32 V, VGS = 0 V
= –32 V, VGS = 0 V
V
DS
= ±20 V, VDS = 0 V
V
GS
Q2
–40
Q1
Q2
Q1
Q2
All
V
34
–40
1
–1
±100
mV/°C
μA
nA
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
ΔVGS(th)
ΔTJ
R
DS(on)
gFS Forward Transconductance VDS = 10 V, ID = 6.2 A
Gate Threshold Voltage
Temperature Coefficient
Static Drain-Source
On-Resistance
= VGS, ID = 250 μA
V
DS
= VGS, ID = –250 µA
V
DS
= 250 μA, Referenced to 25°C
I
D
I
= –250 µA, Referenced to 25°C
D
VGS = 10 V, ID = 6.2 A
= 4.5 V, ID = 4.8 A
V
GS
= 10 V, ID = 6.2 A, TJ = 125°C
V
GS
= –10 V, ID = –4.4 A
V
GS
= –4.5 V, ID = –3.8 A
V
GS
= –10 V, ID = –4.4 A, TJ = 125°C
V
GS
= –10 V, ID =–4.4 A
V
DS
Q1
Q2 1 –1
Q1
Q2
Q1 21
Q2 37
Q1
Q2
1.9
–1.7 3 –3
–5 4
26
29
50
55
21
12
V
mV/°C
29
mΩ
36
43
46
63
73
S
Dynamic Characteristics
C
Input Capacitance Q1
iss
C
Output Capacitance Q1
oss
C
Reverse Transfer
rss
RG Gate Resistance f = 1.0 MHz
Capacitance
Q1
= 20 V, VGS = 0 V, f = 1.0 MHz
V
DS
Q2
= –20 V, VGS = 0 V, f = 1.0 MHz
V
DS
Q2
Q2
Q1
Q2
Q1
Q2
760
1050
100
140
60
70
1.2 9
pF
pF
pF
Ω
4
7
D
l N
Ph
nn
l P
w
rTr
n
h
®
M
FET
FDS4897C Rev C(W) www.fairchildsemi.com
S
89
C
ua
&
C
a
e
o
e
e
c
OS
FD
Electrical Characteristics (continued) T
Symbol
Parameter
Test Conditions
= 25°C unless otherwise noted
A
Type Min Typ Max Units
Switching Characteristics (Note 2)
t
Turn-On Delay Time
d(on)
tr Turn-On Rise Time
t
d(off)
tf Turn-Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
Turn -Off Del a y Time
Q1
= 20 V, ID = 1 A,
V
DD
= 10V, R
V
GS
Q2
= –20 V, ID = –1 A,
V
DD
= –10V, R
V
GS
Q1
= 20 V, ID = 6.2 A, VGS = 10 V
V
DS
Q2
= –20 V, ID = –4.4 A,VGS =–10 V
V
DS
GEN
GEN
= 6 Ω
= 6 Ω
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
9
12
5
15
23
45
3
18 6 32
14
20
2.4 3 nC
2.8 4 nC
Drain–Source Diode Characteristics
VSD Drain-Source Diode Forward
trr Diode Reverse Recovery
Qrr Diode Reverse Recovery
Notes:
1. R
θJA
the drain pins. R
Voltage
Time
Charge
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
is guaranteed by design while R
θJC
VGS = 0 V, IS = 1.3 A (Note 2)
VGS = 0 V, IS = –1.3 A (Note 2)
Q1
= 6.2 A, diF/dt = 100 A/µs
I
F
Q2
= –4.4 A, diF/dt = 100 A/µs
I
F
is determined by the user's board design.
θCA
Q1
Q2
Q1
Q2
Q1
Q2
0.7
–0.7
–1.2
17
24
7
12
1.2
18
22
10
27
37
72
20
28
ns
ns
ns
ns
nC
V
ns
nC
4
7
D
l N
Ph
nn
l P
w
rTr
n
h
®
M
a) 78°C/W when
mounted on a
0.5 in2 pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%
3. BV(avalanche) Single-Pulse rating is guaranteed by design if device is operated within the UIS SOA boundary of the device.
b) 125°C/W when
mounted on a .02 in2
pad of 2 oz copper
c) 135°C/W when mounted on a
minimum pad.
FET
FDS4897C Rev C(W) www.fairchildsemi.com
Loading...