Fairchild FDS4897AC service manual
FDS4897AC
Dual N & P-Channel PowerTrench® MOSFET
N-Channel: 40 V, 6.1 A, 26 mΩ P-Channel: -40 V, -5.2 A, 39 mΩ
FDS4897AC Dual N & P-Channel PowerTrench
October 2008
Features
Q1: N-Channel
Max r
Max r
Q2: P-Channel
Max r
Max r
100% UIL Tested
RoHS Compliant
= 26 mΩ at VGS = 10 V, ID = 6.1 A
DS(on)
= 31 mΩ at VGS = 4.5 V, ID = 5.6 A
DS(on)
= 39 mΩ at VGS = -10 V, ID = -5.2 A
DS(on)
= 65 mΩ at VGS = -4.5 V, ID = -4.1 A
DS(on)
D1
D1
Pin 1
D2
D2
SO-8
S1
G1
S2
G2
General Description
These dual N- and P-Channel MOSFETs are produced using
Fairchild Semiconductor's advanced PowerTrench
that has been especially tailored to minimize on-state resistance
and yet maintain superior switching performance
.
®
process
Applications
Inverter
Power Supplies
D2
D2
D1
D1
5
6
7
8
Q2
Q1Q2Q1
G2
4
S2
3
2
G1
S1
1
®
MOSFET
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
P
D
E
AS
, T
T
J
STG
Drain to Source Voltage 40 -40 V
Gate to Source Voltage ±20 ±20 V
Drain Current - Continuous 6.1 -5.2
- Pulsed 24 -24
Power Dissipation for Dual Operation 2.0
T
Single Pulse Avalanche Energy (Note 3) 37 73 mJ
Operating and Storage Junction Temperature Range -55 to +150 °C
= 25 °C unless otherwise noted
A
= 25 °C (Note 1a) 1.6
A
= 25 °C (Note 1b) 0.9
A
A
WPower Dissipation for Single Operation T
Thermal Characteristics
R
θJC
R
θJC
Thermal Resistance, Junction to Case, (Note 1) 40
Thermal Resistance, Junction to Ambient, (Note 1a) 78
°C/W
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDS4897AC FDS4897AC SO-8 13 ” 12 mm 2500 units
©2008 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FDS4897AC Rev.C
FDS4897AC Dual N & P-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
∆BV
∆T
I
DSS
I
GSS
DSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
DSS
Coefficient
J
Zero Gate Voltage Drain Current
Gate to Source Leakage Current VGS = ±20 V, V
= 250 µA, VGS = 0 V
D
I
= -250 µA, VGS = 0 V
D
ID = 250 µA, referenced to 25 °C
I
= -250 µA, referenced to 25 °C
D
V
= 32 V, V
DS
V
= -32 V, V
DS
GS
GS
DS
= 0 V
= 0 V
= 0 V
Q1Q240
-40
Q1
Q2
Q1
Q2
Q1
Q2
V
37
-32
±100
±100nAnA
mV/°C
1
-1
I
On Characteristics
V
V
GS(th)
∆V
∆T
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance
= VDS, ID = 250 µA
GS
V
= VDS, ID = -250 µA
GS
ID = 250 µA, referenced to 25 °C
I
= -250 µA, referenced to 25 °C
D
= 10 V, ID = 6.1 A
V
GS
V
= 4.5 V, ID = 5.6 A
GS
V
= 10 V, ID = 6.1 A, TJ = 125 °C
GS
V
= -10 V, ID = -5.2 A
GS
V
= -4.5 V, ID = -4.1 A
GS
V
= -10 V , ID = -5.2 A, TJ = 125 °C
GS
V
= 5 V, ID = 6.1 A
DD
V
= -5 V, ID = -5.2 A
DD
Q1Q21.5
-1.5
Q1
Q2
Q1
Q2
Q1
Q2
2.0
-2.0
-6
6
20
24
30
28
45
41
24
14
3.0
-3.0
mV/°C
26
31
39
39
65
57
µA
V
mΩ
S
®
MOSFET
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g(TOT)
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
795
Q1
= 20 V, VGS = 0 V, f = 1 MHZ
V
DS
Q2
= -20 V, VGS = 0 V, f = 1 MHZ
V
DS
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1055
765
1015
95
130
135
180
6580100
120
1.7
3.6
pF
pF
pF
Ω
6
17
17
15
15
12
15
10
10
30
30
10
10
21
20
ns
ns
ns
ns
nC
8
2
3
2
3
nC
nC
Q1
V
= 20 V, ID = 6.1 A,
DD
V
= 10 V, R
GS
GEN
= 6 Ω
Q2
= -20 V, ID = -5.2 A,
V
DD
V
= -10 V, R
GS
GEN
= 6 Ω
Q1
V
= 10 V, VDD = 20 V, ID = 6.1 A
GS
Q2
= -10 V, VDD = -20 V, ID = -5.2 A
V
GS
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
2.5
2.6
2.9
3.2
©2008 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com
FDS4897AC Rev.C
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
V
= 0 V, IS = 1.3 A (Note 2)
V
SD
t
rr
Q
Notes:
1: R
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
rr
is determined with the device mo unted on a 1i n2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJA
the user's board design.
GS
V
= 0 V, IS = -1.3 A (Note 2)Q1Q2
GS
Q1
I
= 6.1 A, di/dt = 100 A/s
F
Q2
I
= -5.2 A, di/dt = 100 A/s
F
0.75
-0.76
Q1
Q2
Q1
Q2
is guaranteed by design whil e R
θJC
17
20
10
1.2
-1.2
31
36
7
15
nC
20
is determined by
θCA
FDS4897AC Dual N & P-Channel PowerTrench
V
ns
a) 78 °C/W when
mounted on a 1 in2
pad of 2 oz copper
2: Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%.
3: Starting TJ = 25 °C, N-ch: L = 3 mH, IAS = 5 A, VDD = 40 V, VGS = 10 V; P-ch: L = 3 mH, IAS = -7 A, VDD = -40 V, VGS = -10 V.
b) 135 °C/W when
mounted on a
minimun pad
®
MOSFET
©2008 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com
FDS4897AC Rev.C
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