Fairchild FDS4685 service manual
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FDS4685 40V P-Channel PowerTrench
June 2005
FDS4685
40V P-Channel PowerTrench
®
MOSFET
Features
–8.2 A, –40 V R
R
Fast switching speed
High performance trench technology for extremely low
R
DS(ON)
High power and current handling capability
SO-8
Absolute Maximum Ratings
DS(ON)
DS(ON)
D
D
Pin 1
= 0.027 Ω @ V
= 0.035 Ω @ V
D
D
S
= –10 V
GS
= –4.5 V
GS
G
S
S
T
= 25°C unless otherwise noted
A
Applications
Power management
Load switch
Battery protection
General Description
This P-Channel MOSFET is a rugged gate version of Fairchild
Semiconductor’s advanced PowerTrench process. It has been
optimized for power management applications requiring a wide
range of gate drive voltage ratings (4.5V – 20V).
5
6
7
8
4
3
2
1
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
T
, T
J
STG
Thermal Characteristics
R
JA
R
JA
R
JC
Drain-Source Voltage –40 V
Gate-Source Voltage
Drain Current - Continuous (Note 1a) –8.2 A
- Pulsed –50
Power Dissipation for Single Operation (Note 1a) 2.5 W
(Note 1b) 1.4
(Note 1c) 1.2
Operating and Storage Junction Temperature Range –55 to +150
Thermal Resistance, Junction-to-Ambient (Note 1a) 50
Thermal Resistance, Junction-to-Ambient (Note 1c) 125
Thermal Resistance, Junction-to-Case (Note 1) 25
20 V
C/W
®
MOSFET
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS4685 FDS4685 13” 12mm 2500 units
©2005 Fairchild Semiconductor Corporation
FDS4685 Rev. C(W)
1
www.fairchildsemi.com
θ
θ
θ
∆
µ
±
∆
Ω
FDS4685 40V P-Channel PowerTrench
Electrical Characteristics
T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
BV
DSS
∆ T
J
I
DSS
I
GSS
On Characteristics (Note 2)
V
GS(th)
V
GS(th)
∆ T
J
R
DS(on)
g
FS
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Switching Characteristics (Note 2)
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Drain–Source Diode Characteristics
V
SD
t
rr
Q
rr
Notes:
1. R
JA
R
JC
Drain–Source Breakdown Voltage V
Breakdown Voltage Temperature
= 0 V, I
GS
I
= –250 µ A, Referenced to 25 ° C –32 mV/ ° C
D
= –250 µ A –40 V
D
Coefficient
Zero Gate Voltage Drain Current V
Gate–Body Leakage V
Gate Threshold Voltage V
Gate Threshold Voltage
= –32 V, V
DS
= ± 20 V, V
GS
= V
DS
GS
I
= –250 µ A, Referenced to 25 ° C 4.7 mV/ ° C
D
= 0 V –1
GS
= 0 V
DS
, I
= –250 µ A–1–1.6 –3 V
D
100 nA
Temperature Coefficient
Static Drain–Source
On–Resistance
Forward Transconductance V
Input Capacitance V
Output Capacitance 256 pF
V
= –10 V, I
GS
V
= –4.5 V, I
GS
V
= –10 V, I
GS
= –5 V, I
DS
= –20 V, V
DS
f = 1.0 MHz
= –8.2 A
D
= –7 A
D
= –8.2 A, T
D
= –8.2 A 22 S
D
= 0 V,
GS
= 125 ° C
J
22
27
29
35
31
42
1872 pF
m Ω
Reverse Transfer Capacitance 134 pF
Gate Resistance V
Tu r n–On Delay Time V
Tu r n–On Rise Time 11 20 ns
= 15 mV, f = 1MHz 4
GS
= –20 V, I
DD
V
= –10 V, R
GS
= –1 A,
D
GEN
= 6 Ω
14 25 ns
Tu r n–Off Delay Time 50 80 ns
Tu r n–Off Fall Time 18 32 ns
Total Gate Charge V
Gate–Source Charge 5.6 nC
DS
V
GS
= –20 V, I
= –5 V
= –8.2 A,
D
19 27 nC
Gate–Drain Charge 6.1 nC
Drain–Source Diode Forward Voltage V
Diode Reverse Recovery Time I
Diode Reverse Recovery Charge 15 nC
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
is guaranteed by design while R
a) 50°C/W when mounted
is determined by the user's board design..
CA
2
pad of 2 oz
on a 1 in
copper
= 0 V, I
GS
= –8.2 A,
F
d
/d
= 100 A/µs
iF
t
= –2.1 A (Note 2) –0.7 –1.2 V
S
26 nS
b) 105°/W when mounted
on a .04 in
copper
2
pad of 2 oz
c) 125°/W when mounted
on a minimum pad.
A
®
MOSFET
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300 µ s, Duty Cycle < 2.0%
FDS4685 Rev. C(W)
2
www.fairchildsemi.com
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