ESMT M52S128168A User Manual

ESMT M52S128168A

Revision History

Revision 1.0 (May. 29, 2007)

-Original

Revision 1.1 (Oct. 08, 2007)

-Add Speed -7 spec.

-Modify Icc spec

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 1/47

ESMT M52S128168A

Mobile SDRAM 2M x 16 Bit x 4 Banks

Synchronous DRAM

FEATURES

y 2.5V power supply
y LVTTL compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs

- CAS Latency (2 & 3)

- Burst Length (1, 2, 4, 8 & full page)

ORDERING INFORMATION

PRODUCT NO.

M52S128168A-7TG 143MHz 54 TSOP II Pb-free
M52S128168A-7BG 143MHz 54 Ball FBGA Pb-free

MAX

FREQ.

PACKAGE Comments

- Burst Type (Sequential & Interleave)

y EMRS cycle with address
y All inputs are sampled at the positive going edge of the

system clock

y Special function support

- PASR (Partial Array Self Refresh)

- TCSR (Temperature Compensated Self Refresh)

- DS (Driver Strength)

y DQM for masking
y Auto & self refresh
y 64ms refresh period (4K cycle)

M52S128168A-7.5TG 133MHz 54 TSOP II Pb-free
M52S128168A-7.5BG 133MHz 54 Ball FBGA Pb-free
M52S128168A-10TG 100MHz 54 TSOP II Pb-free
M52S128168A-10BG 100MHz 54 Ball FBGA Pb-free

GENERAL DESCRIPTION

The M52S128168A is 134,217,728 bits synchronous high data rate D ynamic RAM organized as 4 x 2,097,152 words
by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst lengths an d programmabl e late ncies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.

PIN ASSIGNMENT (Top View)

V

V

V

V

LDQM

A

10/AP

V

DQ0

DDQ

DQ1
DQ2

SSQ

DQ3
DQ4

DDQ

DQ5
DQ6

SSQ

DQ7

V

WE
CAS
RAS

CS
BA 0
BA 1

VDD

1

DD

2
3
4
5
6
7
8
9
10
11
12
13
14

DD

15
16
17
18
19
20
21
22
23

A

0

24

A1

25

A2

26

A3

27

V

54

SS

53

DQ15

52

V

SSQ

51

DQ14

50

DQ13

49

V

DDQ

48

DQ12

47

DQ11

46

SSQ

V

45

DQ10

44

DQ9

43

V

DDQ

42

DQ8

41

V

SS

40

NC

39

UDQM

38

CLK

37

CKE

36

NC

35

A

11

34

A9

33

A8

32

A7

31

A6

30

A5

29

A4

28

VSS

123456789

A

B

C

D

E

F

G

H

J

VSS DQ15

DQ14 DQ13

DQ12 DQ11

DQ10 DQ9

DQ8 NC

UDQM CLK

NC A11

A8

A7

A5

VSS

VSSQ

VDDQ

VSSQ

VDDQ

VSS

CKE

A9

A6

A4

VDDQ DQ0

VSSQ DQ2

VDDQ

VSSQ DQ6

VDD LDQM

CAS

BA0 BA1

A0

A3 A2

DQ4

RAS

VDD

DQ1

DQ3

DQ5

DQ7

WE

CS

A10

A1

VDD

54 Ball FBGA

(8x8mm)

(mm ball pitch)

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 2/47

ESMT M52S128168A

FUNCTIONAL BLOCK DIAGRAM

CLK
CKE

Address

Clock

Generator

Row
Address

Mode
Register

Buffer
&
Refresh
Counter

Row Decoder

Bank D

Bank C

Bank B

Bank A

CS
RAS
CAS
WE

Control Logic

Command Decoder

Column
Address
Buffer
&
Refresh
Counter

Sense Amplifier

Column Decoder

Data Control Circuit

Latch Circuit

Input & Output

PIN FUNCTION DESCRIPTION

PIN NAME INPUT FUNCTION

CLK System Clock Active on the positive going edge to sample all inputs

CS

CKE Clock Enable

A0 ~ A11 Address

BA0 , BA1 Bank Select Address

RAS

CAS

WE

L(U)DQM Data Input / Output Mask
DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.

VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.
VDDQ / VSSQ Data Output Power / Ground

NC No Connection This pin is recommended to be left No Connection on the device.

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

Disables or enables device oper ation by masking or enabling all
inputs except CLK , CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.

Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~ CA8

Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch ti me.

Latches row addresses on the positive goin g edge of the CLK with

RAS low.

Enables row access & precharge.
Latches column address on the positive going edge of the CLK with

CAS low.

Enables column access.
Enables write operation and row precharge.
Latches data in starting from

Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.

Isolated power supply and ground for the output buffers to provide
improved noise immunity.

CAS,

WE

active.

L(U)DQM

Buffer

DQ

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 3/47

ESMT M52S128168A

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL VALUE UNIT

Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 3.6 V
Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V
Storage temperature TSTG -55 ~ +150

Power dissipation PD 1 W
Short circuit current IOS 50 mA

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.

Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

C°

DC OPERATING CONDITION

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C° )

PARAMETER SYMBOL MIN TYP MAX UNIT NOTE

Supply voltage VDD, VDDQ 2.3 2.5 2.7 V
Input logic high voltage VIH 0.8xVDDQ 2.5 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.3 V 2
Output logic high voltage VOH VDDQ-0.2 - - V IOH = -0.1mA
Output logic low voltage VOL - - 0.2 V IOL = 0.1mA
Input leakage current IIL -2 - 2

Output leakage current IOL -2 - 2

Note: 1. VIH(max) = 3.0V AC for pulse width ≤ 3ns acceptable.

2. V

3. Any input 0V ≤ VIN ≤ VDDQ, all other pins are not under test = 0V.

4. Dout is disabled , 0V ≤ VOUT ≤ VDDQ.

IL(min) = -1.0V AC for pulse width

≤

3ns acceptable.

μ A
μ A

3
4

CAPACITANCE (V

= 2.5V, TA = 25 C° , f = 1MHZ)

DD

PARAMETER SYMBOL MIN MAX UNIT

Input capacitance (A0 ~ A11, BA0 ~ BA1) CIN1 1.5 3.0 pF
Input capacitance

C

(CLK, CKE,
L(U)DQM)

Data input/output capacitance (DQ0 ~ DQ15) COUT 2.0 4.5 pF

CS, RAS , CAS ,

WE

&

IN2 1.5 3.5 pF

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 4/47

ESMT M52S128168A

≤

≤

DC CHARACTERISTICS

Recommended operating condition unless otherwise noted，TA = 0 to 70 C°

Parameter Symbol Test Condition

Operating Current
(One Bank Active)

Precharge Standby
Current in power-down
mode

Precharge Standby
Current in non
power-down mode

Active Standby Current
in power-down mode

Active Standby Current
in non power-down
mode
(One Bank Active)

Operating Current
(Burst Mode)

Refresh Current

ICC1

ICC2P
ICC2PS

ICC2N

ICC2NS
ICC3P
ICC3PS

ICC3N

ICC3NS

I

CC4

CC5 tRC ≥ tRC(min)

I

Burst Length = 1

≥

RC

tRC (min), tCC≥ tCC (min), IOL= 0mA

t
CKE

≤ VIL(max), tCC =15ns

CKE

≤ VIL(max), CLK

CKE

≥ VIH(min), CS ≥ VIH(min), tCC =10ns

Input signals are changed one time during 20ns
CKE≥ VIH(min), CLK≤VIL(max), tCC = ∞

Input signals are stable
CKE

≤ VIL(max), tCC =15ns

≤

CKE
CKE

Input signals are changed one time during 2clks
All other pins

CKE
Input signals are stable

OL= 0mA, Page Burst

I
All Band Activated, tCCD = tCCD (min)

VIL(max), CLK≤ VIL(max), tCC = ∞

≥ VIH(min), CS ≥ VIH(min), tCC=15ns

≥ VIH (min), CLK

VIL(max), tCC = ∞

≥ V

-0.2V or ≤ 0.2V

DD

VIL(max), tCC=∞

CAS

Latency

Version

-7 -7.5 -10

80 mA 1

0.5

0.5

10 mA

10 mA

5
2

25

15 mA

85

150 130 120

Unit Note

mA
mA

mA

mA

mA 1

mA 2

-N/L 500 uA

-G/F

Self Refresh Current

Deep Power Down
Current

Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).

2.Refresh period is 64ms. Addresses are changed only one time during t

CC6 CKE≤ 0.2V

I

CC7 CKE≤ 0.2V 10 uA

I

TCSR range 15 45 70

4 Banks 380 400 500

2 Bank 360 380 450
1 Bank 340 350 400

CC(min).

C°

uA

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 5/47

ESMT M52S128168A

AC OPERATING TEST CONDITIONS (VDD=2.5V ± 0.2V,TA= 0 C° ~ 70C°)

Parameter Value Unit

Input levels (Vih/Vil) 0.9 x VDDQ / 0.2 V
Input timing measurement reference level 0.5 x VDDQ V
Input rise and fall time tr / tf = 1 / 1 ns
Output timing measurement reference level 0.5 x VDDQ V
Output load condition See Fig.2

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Row active to row active delay tRRD(min) 14 15 20 ns 1

RAS to CASdelay

Row precharge time tRP(min) 14 15 20 ns 1

Row active time

Row cycle time

Last data in to new col. Address delay tCDL(min) 1 CLK 2
Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. Address to col. Address delay tCCD(min) 1 CLK 3

Mode Register command to Active or Refresh Command

Number of valid output data

Refresh period(4,096 rows)

Note: 1. The minimum number of cloc k cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

3. Minimum delay is required to complete write.

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks

5. A new command may be given T

6. A maximum of eight consecutive AUTO REFRESH commands (with t
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μs.)

@Operating tRC(min) 63 67.5 90 ns 1
@Auto refresh t

rfc after self refresh exit.

Symbol

t

RCD(min) 14 15 20 ns 1

tRAS(min) 42 48 50 ns 1

RAS(max) 100 us -

t

RFC(min) 80 ns 1 , 5

tMRD(min) 2 CLK ­CAS latency=3 2
CAS latency=2 1

t

REF(max) 64

Version

Unit Note

-7 -7.5 -10

ea 4

ms 6

RFCmin) can be posted to any given SDRAM,and

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 6/47

ESMT M52S128168A

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter Symbol

CLK cycle time

CLK to valid
output delay

Output data hold time tOH 2.5 2.5 2.5 ns 2
CLK high pulse width tCH 2.5 2.5 3 ns 3
CLK low pulse width tCL 2.5 2.5 3 ns 3
Input setup time tSS 2 2 2.5 ns 3
Input hold time tSH 1 1 1 ns 3
CLK to output in Low-Z tSLZ 1 1 1 ns 2

Hi-Z

CAS Latency =3 7 1000 7.5 10
CAS Latency =2
CAS Latency =3 5.5 6 7
CAS Latency =2

CAS Latency =3 5.5 6 7 CLK to output in
CAS Latency =2

tCC

SAC

t

SHZ

t

-7 -7.5 -10

Min Max Min Max Min Max

9 9

7 7 10

7 7 10

1000

12

1000 ns 1

*All AC parameters are measured from half to half.

Unit Note

ns 1

ns

Note: 1.Parameters depend on programmed CAS latency.

2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.

3.Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 7/47

ESMT M52S128168A

SIMPLIFIED TRUTH TABLE

COMMAND CKEn-1 CKEn

Mode Register set

Register

Refresh

Read &

Column Address

Write &

Column Address

Precharge

Clock Suspend or
Active Power Down

Extended Mode Register

set

Auto Refresh H

Self
Refresh

Bank Active & Row Addr. H X L L H H X V Row Address

Burst Stop H X L H H L X X

CS RAS CAS

H X L L L L X OP CODE 1,2

Entry

Exit L H

Auto Precharge Disable L 4

Auto Precharge Enable

Auto Precharge Disable L 4

Auto Precharge Enable

Bank Selection V L
All Banks

Entry H L

Exit L H

H

H X L H L H X V

H X L H L L X V

H X L L H L X

L L L H X X

L

L H H H X

H X X X X

H X X X

L V V V

X X X X

WE

BA1

X H

X

X

A10/AP

H

H

BA0

DQM

A11

A9~A0

X

Column
Address
(A0~A8)

Column

Address

(A0~A8)

X

X

Note

3
3
3
3

4,5

4,5

6

Precharge Power Down Mode

DQM H X V X 7

No Operating Command H X

(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
Note : 1.OP Code : Operating Code

A0~A11 & BA0~BA1 : Program keys. (@ MRS). BA1=0 for MRS and BA1=1 for EMRS

2.MRS/EMRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS/EMRS.

3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.

4.BA0~BA1 : Bank select addresses.
If both BA0 and BA1 are “Low” at read ,write , row active and precharge ,bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read ,write , row active and precharge ,bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read ,write , row active and precharge ,bank C is selected.
If both BA0 and BA1 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.

5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.

6.Burst stop command is valid at every burst length.

7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)

Entry H L

Exit L H

H X X X

L H H H

H X X X

L V V V

H X X X

L H H H

X

X

X X

X

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 8/47

ESMT M52S128168A

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address BA0 BA1 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function 0 0 0 0 0 0 0 CAS Latency BT Burst Length

Test Mode CAS Latency Burst Type Burst Length

A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1

0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2

1 0 Reserved 0 1 0 2 0 1 0 4 4
1 1 Reserved 0 1 1 3

1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved

Full Page Length : 512

0 1 1 8 8

1 1 1 Full Page Reserved

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 9/47

ESMT M52S128168A

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus

1 0 0 0 0 0 0 DS 0 0 PASR Extended Mode Register Set

PASR

DS

Remark R : Reserved

A2-A0 Self Refresh Coverage

000 4Bank
001 2 Bank (BankA& BankB) or

(BA1=0)

010 1 Bank (BankA) or

(BA0=BA1=0)
011 R
100 R
101 R
111 R

A6-A5 Driver Strength

00 Full Strength
01 1/2 Strength
10 1/4 Strength
11 R

EXTENDED MODE REGISTER SET (EMRS)

The extended mode register stores for selecting PASR;DS. The extended mode register set must be done before any active
command after the power up sequence. The extended mode register is written by asserting low on CS,RAS,CAS,WE and high on
BA1,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended more
register). The state of address pins
A0~An in the same cycle as CS,RAS,CAS,WE going low is written in the extended mode register. Refer to the table for specific
codes.
The extended mode register can be changed by using the same command and clock c ycle requirements during operat ions as long
as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks
refreshed.

Internal Temperature Compensated Self Refresh (TCSR)

Note :

1. In order to save power consumption, Mobil e-DRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the three temperature range : 15°C, 45°C and 70°C.

2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.

3. It has +/-5°C tolerance

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 10/47

ESMT M52S128168A

BURST SEQUENCE (BURST LENGTH = 4)

Initial Adrress

A1 A0

0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0

Sequential Interleave

BURST SEQUENCE (BURST LENGTH = 8)

Initial

A2 A1 A0

0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6

0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5

0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4

1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3

1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2

1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1

1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

Sequential Interleave

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 11/47

ESMT M52S128168A

DEVICE OPERATIONS

CLOCK (CLK)

The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between V
high all inputs are assumed to be in valid state (low or high)
for the duration of setup and hold time around positive edge
of the clock for proper functionality and Icc specifications.

CLOCK ENABLE(CKE)

The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down mode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at
least “1CLK + tSS” before the high going edge of the clock,
then the SDRAM becomes active from the same clock edge
accepting all the input commands.

BANK ADDRESSES (BA0~BA1)

This SDRAM is organized as four independent banks of
2,097,152 words x 16 bits memory arrays. The BA0~BA1

inputs are latched at the time of assertion of

CAS to select the bank to be used for the operation. The

banks addressed BA0~BA1 are latched at bank active, read,
write, mode register set and precharge operations.

ADDRESS INPUTS (A0~A11)

The 21 address bits are required to decode the 2,097,152
word locations are multiplexed into 12 address input pins
(A0~A11). The 12 row addresses are latched along with

RAS and BA 0~BA1 during ba nk active command. T he 9 bit

column addresses are latched along with
BA0~BA1 during read or with command.

NOP and DEVICE DESELECT

IL and VIH. During operation with CKE

RAS and

CAS, WE and

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and
various vendor specific options to make SDRAM useful
for variety of different applications. The default value of
the mode register is not defined, therefore the mode
register must be written after power up to operate the
SDRAM. The mode register is written by asserting low

CS , RAS , CAS and WE (The SDRAM should

on
be in active mode with CKE already high prior to writing

the mode register). The state of address pins A0~A11
and BA0~BA1 in the same cycle as

WE

and
register. Two clock cycles is required to complete the
write in the mode register. The mode register contents
can be changed using the same command and clock
cycle requirements during operation as long as all banks
are in the idle state. The mode register is divided into
various fields into depending on functionality. The burst
length field uses A0~A2, burst type uses A3, CAS
latency (read latency from column address) use A4~A6,
test mode use A7~A8, vendor specific options use A9,
A10~A11 and BA1~BA0. A7~A8, A10/AP~A11 and
BA0~BA1 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for
various burst length, burst type and CAS latencies.

going low is the data written in the mode

CS , RAS , CAS

When
performs no operation (NOP). NOP does not initiate any new

operation, but is needed to complete operations which
require more than single clock cycle like bank activate, bu rst
read, auto refresh, etc. The device deselect is also a NOP

and is entered by asserting
the command decoder so that

the address inputs are ignored.

RAS , CAS and WE are high, The SDRAM

CS high. CS high disables

RAS , CAS, WE and all

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 12/47

ESMT M52S128168A

DEVICE OPERATIONS (Continued)

BANK ACTIVATE

The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and CS with

desired row and bank address, a row access is initiated. The
read or write operation can occur after a time delay of t

(min) from the time of bank activation. tRCD is the internal

RCD

timing parameter of SDRAM, therefore it is dependent on
operating clock frequency. The minimum number of clock
cycles required between bank activate and read or write
command should be calculated by dividing tRCD (min) with
cycle time of the clock and then rounding of the result to the
next higher integer. The SDRAM has four internal banks in
the same chip and shares part of the internal circuitry to
reduce chip area, therefore it restricts the activation of four
banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high requiring some time
for power supplies to recover before another bank can be
sensed reliably. t

RRD (min) specifie s the min imu m t ime r equired

between activating different bank. The number of clock
cycles required between different bank activation must be
calculated similar to t

RCD specification. The minimum time

required for the bank to be active to initiate sensing and
restoring the complete row of dynamic cells is determined by
t

RAS (min). Every SDRAM bank activate command must satisfy
RAS (min) specification before a precharge command to that

t
active bank can be asserted. The maximum time any bank
can be in the active state is determined by tRAS (max) and tRAS

(max) can be calculated similar to tRCD specification.

BURST READ

The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on

CS and RAS with WE being high on the positive edge

of the clock. The bank must be active for at least tRCD (min)
before the burst read command is issued. The first output
appears in CAS latency number of clock cycles after the
issue of burst read command. The burst length, burst
sequence and latency from the burst read command is
determined by the mode register which is already
programmed. The burst read can be initiated on any colu mn
address of the active row. The address wraps around if the
initial address does not start from a boundary such that
number of outputs from each I/O are equal to the burst
length programmed in the mode register. The output goes
into high-impedance at the end of burst, unless a new burst
read was initiated to keep the data output gapless. The burst
read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.

BURST WRITE

The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive
clock cycles in adjacent addresses depending on burst
length

and burst sequence. By asserting low on
and WE with valid column address, a write burst is

initiated. The data inputs are provided for the initial
address in the same clock cycle as the burst write
command. The input buffer is deselected at the end of
the burst length, even though the internal writing can be
completed yet. The writing can be complete by issuing a
burst read and DQM for blocking data inputs or burst
write in the same or another active bank. The burst stop
command is valid at every burst length. The write burst
can also be terminated by using DQM for blocking data
and procreating the bank tRDL after the last data input to
be written into the active row. See DQM OPERATION
also.

DQM OPERATION

The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits

writing during write operation. The read latency is two
cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in read cycle and
occurs in the same cycle during write cycle. DQM
operation is synchronous with the clock. The DQM
signal is important during burst interrupts of write with
read or precharge in the SDRAM. Due to asynchronous
nature of the internal write, the DQM operation is critical
to avoid unwanted or incomplete writes when the
complete burst write is required. Please refer to DQM
timing diagram also.

PRECHARGE

The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank

activate and

CS , RAS , WE and A10/AP with valid
BA0~BA1 of the bank to be procharged. The precharge
command can be asserted anytime after t

satisfy from the bank active command in the desired
bank. tRP is defined as the minimum number of clock
cycles required to complete row precharge is calculated
by dividing tRP with clock cycle time and rounding up to
the next higher integer. Care should be taken to make
sure that burst write is completed or DQM is used to
inhibit writing before precharge command is asserted.
The maximum time any bank can be active is specified

RAS (max). Therefore, each bank activate command. At

by t
the end of precharge, the bank enters the idle state and
is ready to be activated again. Entry to power-down,
Auto refresh, Self refresh and Mode register set etc. is
possible only when all banks are in idle state.

CS , CAS

RAS (min) is

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 13/47

ESMT M52S128168A

DEVICE OPERATIONS (Continued)

AUTO PRECHARGE

The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy t
and CAS latency. The auto precharge command is issu ed at
the same time as burst write by asserting high on A10/AP,
the bank is precharge command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.

BOTH BANKS PRECHARGE

A11 banks can be precharged at the same time by using
Precharge all command. Asserting low on CS ,RAS , and

WE with high on A10/AP after all banks have satisfied tRAS

(min) requirement, performs precharge on all banks. At the

end of t
state.

AUTO REFRESH

The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by

asserting low on
and

with both banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by t
required can be calculated by driving t
time and them rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us.

RAS (min) and “tRP” for the programmed burst length

RP after performing precharge all, all banks are in idle

CS, RAS and CAS with high on CKE

WE . The auto refresh command can only be asserted

RFC (min). The minimum number of clock cycles

RFC with clock cycle

SELF REFRESH

The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode
for data retention and low power operation of SDRAM.
In self refresh mode, the SDRAM disables the internal
clock and all the input buffers except CKE. The refresh
addressing and timing is internally generated to reduce
power consumption. The self refresh mode is entered

from all banks idle state by asserting low on

RAS , CAS and CKE with high on WE . Once the self

refresh mode is entered, only CKE state being low
matters, all the other inputs including clock are ignored
to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed
by NOP’s for a minimum time of t
reaches idle state to begin normal operation.

RFC before the SDRAM

CS ,

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 14/47

ESMT M52S128168A

COMMANDS

Mode register set command

(CS ,RAS ,CAS,WE, BA1, BA0 = Low)

The DRAM has a mode register that defines how the device operates. In this
command, A0 through A11, BA0 and BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.

The mode register can be set only when all banks are in idle state. During 2CLK
(tMRD) following this command, the DRAM cannot accept any other commands.

Extended Mode register set command

(CS ,RAS , CAS , WE , BA0 = Low ; BA1= High)

The DRAM has a extended mode register that defines how to set PASR, DS.

Activate command

(

CS ,RAS = Low, CAS, WE = High)

The DRAM has four banks, each with 4,096 rows.

This command activates the bank selected by BA1 and BA0 (BS) and a row
address selected by A0 through A11.

This command corresponds to a conventional DRAM’s

RAS falling.

Elite Semiconductor Memory Technology Inc. Publication Date: Oct. 2007

Revision: 1.1 15/47