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ESMT AD62550A
Class-D Audio Power Amplifier with USB / I2S Interface
Features
z Compliant with USB Specification v1.1, and USB
2.0 full speed
z Embedded high efficiency, high performance class
D stereo amplifier
z Support I
master mode
Sampling frequencies(Fs)：48kHz
z +6dB enhancement(Theater function)
z Support both bus-powered and self-powered
operation
z Supports Win Me//2000/XP and MacOS
z True plug-and-play application, no driver is
required for basic USB speaker application
z Support volume/mute control with external button
z Built-in 5V to 3.3V regulator for internal device
operation
z Total efficiency
80% for 8Ω load @ -1dB 1kHz sine wave input
z Loudspeaker PSNR & DR (A-weighting)
80dB (PSNR), 78dB (DR) with Bead filter
2
S input and I2S output interface of
Functional Block Diagram
82dB (PSNR), 78dB (DR) with Chock filter
z Anti-pop design
z Over-temperature protection
z Under-voltage shutdown
z Short-circuit detection
z 12 MHz Crystal Input
z 32-pin LQFP(Pb free)
Description
AD62550A is a single chip of Class-D audio
amplifier with USB/I
power supplied from the USB port, AD62550A can
drive a pair of up to 1W speakers due to the built-in,
high efficiency and high performance class D
amplifiers. The device also has an I
2
S output port. The I2S input port allows other
I
external audio sources to use the class D amplifier
to share the speakers. The I
other high performance audio device (i.e.
AD8356A/AD8256A) to be controlled by AD62550A.
2
S interface. When using the
2
S input port and
2
S output port allows
Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007
Revision: 1.3 1/14
Page 2
ESMT AD62550A
Pin Assignment
Pin Description
Pin Name Type Description Characteristics
1 MSDA I/O I2C’s SDA of Master mode Schmitt trigger TTL input buffer
2 MSCL O I2C’s SCL of master mode
3
4 SDATAO O
5 LRCIN O
6 BCLK O
7 SDATAI I Serial audio data input Schmitt trigger TTL input buffer
8 MCLK O Master clock(256xFs)
9 GNDR P Ground for right channel
10 RB O Right channel output-
11 RA O Right channel output+
12 VDDR P Supply for right channel
13 VDDL P Supply for left channel
PDO
O
Power-down output (Note1)
Serial audio output (Note1)
L/R clock output(Fs) (Note1)
BCLK output(64xFs) (Note1)
14 LA O Left channel output+
15 LB O Left channel output-
16 GNDL P Ground for left channel
Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007
Revision: 1.3 2/14
Page 3
ESMT AD62550A
17
2
S/IUSB
I Low is USB mode, high is I
18 SEL I Mode selection bit Schmitt trigger TTL input buffer
19 NC NC No connection
20 XO O Crystal output
21 XI I Crystal input
22 GND P Ground
23 REGO O 3.3V regulator output
24 VDD P 5V supply voltage
25 USBDM I/O USB data D-
26 USBDP I/O USB data D+
27 THEATER I Theater mode, high active Schmitt trigger TTL input buffer
2
S mode Schmitt trigger TTL input buffer
28
29
30
31
32
VOLDN
VOLUP
MUTE
ERROR
RESET
I Volume down, low active With internal pull-up resistor
I Volume up, low active With internal pull-up resistor
I Power-down and mute of Class D Schmitt trigger TTL input buffer
O Error output Open-Drain output
I Reset signal Schmitt trigger TTL input buffer
Note1: Must be strapped resistor 1MΩ to 3.3V(REGO) or GND. BCLK, LRCIN and PDO must be strapped
to GND. SDATAO is strapped to GND by 1MΩ when AD62550A’s volume/mute is controlled by
external button, otherwise strapped to 3.3V when AD62550A is I
2
C slave mode for SEL1 is logic
LOW.
Absolute Maximum Ratings
Symbol Parameter Min Max Units
VDD
VDDL(R) Supply for Left (Right) Channel 0 5.5 V
V
i
T
stg
T
a
Voltage Difference between V
Voltage Difference between V
V
Supply for regulator input 0 5.5 V
Input Voltage -0.3 3.6 V
Storage Temperature -65 150
Ambient Operating Temperature 0 70
DDL(VDDR
and V
DDL
DDL(VDDR
) and DVDD/AVDD -3 3 V
) Power-on Voltage Ramp 0.2
-1 1 V
DDR
o
C
o
C
V/μs
Recommended Operating Conditions
Symbol Parameter Typ Units
VDD
VDDL(R)
Supply for regulator input 4.5~5.5 V
Supply for Driver Stage 3.0~5.0 V
Ta Ambient Operating Temperature 0~70 oC
Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007
Revision: 1.3 3/14
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