ESMT F25L02PA-86PIG2F, F25L02PA-100PAIG2F, F25L02PA-86PAIG2F, F25L02PA-50HIG2F, F25L02PA-86HIG2F Series Manual

ESMT

F25L02PA (2F)

Flash



FEATURES

 Single supply voltage 2.3~3.6V
 Standard, Dual SPI

 Speed

- Read max frequency: 33MHz

- Fast Read max frequency: 50MHz; 86MHz; 100MHz

- Fast Read Dual max frequency: 50MHz / 86MHz
(100MHz / 172MHz equivalent Dual SPI)

 Low power consumption

- Active current: 20 mA

- Standby current: 25µA

- Deep Power Down current: 10µA

 Reliability

- 100,000 typical program/erase cycles

- 20 years Data Retention

 Program

- Page programming time: 0.7 ms (typical)



ORDERING INFORMATION

Operation Temperature Condition -40°C~85°C

3V Only 2 Mbit Serial Flash Memory

with Dual Output

 Erase

- Chip erase time 0.5 sec (typical)

- Block erase time 0.15 sec (typical)

- Sector erase time 30 ms (typical)

 Page Programming

- 256 byte per programmable page

 SPI Serial Interface

- SPI Compatible: Mode 0 and Mode 3

 End of program or erase detection

 Write Protect (



Hold Pin ( HOLD )



All Pb-free products are RoHS-Compliant

WP )

Product ID Speed

F25L02PA -50PIG2F 50MHz

F25L02PA -86PIG2F 86MHz

F25L02PA -100PIG2F 100MHz

F25L02PA -50PAIG2F 50MHz

F25L02PA -86PAIG2F 86MHz

F25L02PA -100PAIG2F 100MHz

F25L02PA -50HIG2F 50MHz

F25L02PA -86HIG2F 86MHz

F25L02PA -100HIG2F 100MHz



GENERAL DESCRIPTION

The F25L02PA is a 2Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.

The memory array can be organized into 1,024 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.

The device features sector erase architecture. The memory array

Package Comments

8-lead

SOIC

8-lead

SOIC

8-contact

WSON

150 mil

200 mil

6x5 mm

Pb-free

Pb-free

Pb-free

is divided into 64 uniform sectors with 4K byte each; 4 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.

The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jan. 2012

Revision: 1.0

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ESMT

VDD

WP

F25L02PA (2F)



PIN CONFIGURATIONS

8- Lead SOIC

(SOIC 8L, 150mil Body, 1.27mm Pin Pitch)
(SOIC 8L, 208mil Body, 1.27mm Pin Pitch)

CE

SO

VSS

1 8

2 7

3 6

4 5

Operation Temperature Condition -40°C~85°C

HOLD

SCK

SI

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ESMT

F25L02PA (2F)

8- Contact WSON

(WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch)

CE

SO

WP

VSS

1

2

3

4

Operation Temperature Condition -40°C~85°C

8

7

6

5

VDD

HOLD

SCK

SI



PIN DESCRIPTION

Symbol Pin Name Functions

SCK Serial Clock

SI Serial Data Input

SO Serial Data Output

CE

WP

HOLD

VDD Power Supply To provide power.

VSS Ground

Chip Enable

Write Protect

Hold

To provide the timing for serial input and
output operations

To transfer commands, addresses or data
serially into the device.
Data is latched on the rising edge of SCK.

To transfer data serially out of the device.
Data is shifted out on the falling edge of

SCK.

To activate the device when CE is low.

The Write Protect ( WP ) pin is used to
enable/disable BPL bit in the status
register.

To temporality stop serial communication
with SPI flash memory without resetting
the device.

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Publication Date: Jan. 2012

Revision: 1.0

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ESMT

F25L02PA (2F)



FUNCTIONAL BLOCK DIAGRAM

Address

Buffers

and

Latches

X-Decoder

Control Logic

Operation Temperature Condition -40°C~85°C

Flash

Y-Decoder

I/O Butters

and

Data Latches



SECTOR STRUCTURE

Block Sector

3

2

1

0

Serial Interface

CE

SCK

Table 1: F25L02PA Sector Address Table

SI

WPSO HOLD

Sector Size

(Kbytes)

63 4KB 03F000H – 03FFFFH

: : :

48 4KB 030000H – 030FFFH

47 4KB 02F000H – 02FFFFH

: : :

32 4KB 020000H – 020FFFH

31 4KB 01F000H – 01FFFFH

: : :

16 4KB 010000H – 010FFFH

15 4KB 00F000H – 00FFFFH

: : :

0 4KB 000000H – 000FFFH

Address range

Block Address

A17 A16

1 1

1 0

0 1

0 0

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ESMT

F25L02PA (2F)

Operation Temperature Condition -40°C~85°C



STATUS REGISTER

The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,

the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.

Table 2: Software Status Register

Bit Name Function

0 BUSY

1 WEL

2 BP0 Indicate current level of block write protection (See Table 3) 0 R/W
3 BP1 Indicate current level of block write protection (See Table 3) 0 R/W
4 BP2 Indicate current level of block write protection (See Table 3) 0 R/W
5 TB Top / Bottom write protect 0 R/W
6 RESERVED Reserved for future use 0 N/A

7 BPL

Note:

1. Only BP0, BP1, BP2, TB and BPL are writable.

2. BP0, BP1, BP2, TB and BPL are non-volatile.

3. All area are unprotected at power-on (BP2=BP1=BP0=0).

WRITE ENABLE LATCH (WEL)

The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:

•

Power-up

•

Write Disable (WRDI) instruction completion

•

Page Program instruction completion

•

Sector Erase instruction completion

•

Block Erase instruction completion

•

Chip Erase instruction completion

•

Write Status Register instructions

1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled

1 = BP2,BP1,BP0 and TB are read-only bits
0 = BP2,BP1,BP0 and TB are read/writable

BUSY

The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.

Top/Bottom Block Protect (TB)

The Top/Bottom bit (TB) controls if the Block-Protection (BP2,
BP1, BP0) bits protect from the Top (TB=0) or the Bottom (TB=1)
of the array as show in Table 3, The TB bit can be set with Write
Status Register (WRSR) instruction. The TB bit can not be written

to if the Block- Protection-Look (BPL) bit is 1 or WP is low.

Default at
Power-up

0 R

0 R

0 R/W

Read/Write

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ESMT

F25L02PA (2F)

Table 3: F25L02PA Block Protection Table

Protection Level

0 X 0 0 0 None None

Upper 1/4 0 0 0 1 Block 3 030000H – 03FFFFH

Upper 1/2 0 0 1 0 Block 2~3 020000H – 03FFFFH

Upper 3/4 0 1 1 0 Block 1~3 010000H – 03FFFFH

Lower 1/4 1 0 0 1 Block 0 000000H – 00FFFFH

Lower 1/2 1 0 1 0 Block 0~1 000000H – 01FFFFH

Lower 3/4 1 1 1 0 Block 0~2 000000H – 02FFFFH

All Blocks X X 1 1 Block 0~3 000000H – 03FFFFH

Block Protection (BP2, BP1, BP0)

The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the

BP2, BP1, BP0 bits as long as WP is high or the Block­Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to 0.

Status Register Bit

TB BP2 BP1 BP0 Block Range Address Range

Operation Temperature Condition -40°C~85°C

Block Protection Lock-Down (BPL)

WP pin driven low (VIL), enables the Block-Protection­Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the TB, BPL, BP2, BP1, and BP0 bits. When

the W P pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.

Protected Memory Area

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ESMT

WP

WP

F25L02PA (2F)



HOLD OPERATION

HOLD pin is used to pause a serial sequence underway with the

SPI flash memory without resetting the clocking sequence. To

activate the HOLD mode, CE must be in active low state. The

HOLD mode begins when the SCK active low state coincides

with the falling edge of the HOLD signal. The HOLD mode ends

when the HOLD signal’s rising edge coincides with the SCK
active low state.

If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the

SCK next reaches the active low state.

Similarly, if the rising edge of the HOLD signal does not
coincide with the SCK active low state, then the device exits in

Operation Temperature Condition -40°C~85°C

Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.

Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be VIL or VIH.

If CE is driven active high during a Hold condition, it resets the

internal logic of the device. As long as HOLD signal is low, the
memory remains in the Hold condition. To resume

communication with the device, HOLD must be driven active

high, and CE must be driven active low. See Figure 22 for Hold
timing.

S CK

H O L D

A ct iv e

Figure 1: HOLD Condition Waveform



WRITE PROTECTION

The device provides software Write Protection.

The Write-Protect pin ( WP ) enables or disables the lock-down
function of the status register. The Block-Protection bits (BP2,
BP1, BP0, TB and BPL) in the status register provide Write
protection to the memory array and the status register. See Table
3 for Block-Protection description.

H o ld

Write Protect Pin (

The Write-Protect ( WP ) pin enables the lock-down function of

the BPL bit (bit 7) in the status register. When W P is driven low,
the execution of the Write Status Register (WRSR) instruction is

determined by the value of the BPL bit (see Table 4). When W P
is high, the lock-down function of the BPL bit is disabled.

)

A cti ve

H o ld

A ct iv e

Table 4: Conditions to Execute Write-Status-Register (WRSR)

Instruction

BPL Execute WRSR Instruction

L 1 Not Allowed

L 0 Allowed

H X Allowed

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ESMT

MHz

bytes

MHz

F25L02PA (2F)



INSTRUCTIONS

Instructions are used to Read, Write (Erase and Program), and
configure the F25L02PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are

synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most

significant bit. CE must be driven low before an instruction is

Table 5: Device Operation Instructions

Operation

Read

11,12

13

Fast Read

Fast Read Dual
Output

Sector Erase4 (4K Byte)
Block Erase4, (64K Byte) D8H Hi-Z A23-A

Chip Erase

Page Program (PP)

Max.
Freq

1 2 3 4 5 6 N

SIN S

OUT

33 MHz 03H Hi-Z A23-A

50 MHz

~

100

0BH Hi-Z A23-A

50MHz

~

86 MHz

3BH A23-A16 A15-A8 A7-A0 X D

20H Hi-Z A23-A

60H /

C7H

Hi-Z

02H Hi-Z A23-A

SIN S

Hi-Z A15-A

16

Hi-Z A15-A

16

Hi-Z A15-A

16

Hi-Z A15-A

16

OUT

- - - - - - - - - - - -

Hi-Z A15-A

16

Operation Temperature Condition -40°C~85°C

entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high

transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the

device to the standby mode.

Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.

1~3

S

0

0

0

0

S

OUT

Hi-Z X D

S

IN

OUT

OUT0

Hi-Z X X X D

S

IN

X D

OUT0~1

S

OUT

OUT1

OUT0

S

IN

X cont.

X cont.

Hi-Z - - - - - ­Hi-Z - - - - - -

Up to

Hi-Z D

0

IN0

Hi-Z D

IN1

Hi-Z

256

S

IN

S

OUT

Hi-Z A7-A

8

Hi-Z A7-A

8

Hi-Z A7-A

8

Hi-Z A7-A

8

Hi-Z A7-A

8

Bus Cycle

S

IN

S

cont.

Hi-Z

OUT

Read Status Register
(RDSR) 6

Write Status Register
(WRSR)
Write Enable (WREN) 9
Write Disable (WRDI)
Deep Power Down (DP)
Release from Deep
Power Down (RDP)
Read Electronic
Signature (RES) 7
Jedec Read ID
(JEDEC-ID) 8

Read ID (RDID)

10

50 MHz

~

100

05H Hi-Z X D

- - - - - - - - - -

OUT

01H Hi-Z DIN Hi-Z - - -. - - - - - - -

06H Hi-Z
04H Hi-Z
B9h Hi-Z

ABH Hi-Z

- - - - - - - - - - - -

- - - - - - - - - - - -

- - - - - - - - - - - -

- - - - - - - - - - - -

ABH Hi-Z X X X X X X X 11H - - - -

9FH Hi-Z X 8CH X 30H X 12H - - - - - -

90H Hi-Z 00H Hi-Z 00H Hi-Z

00H Hi-Z X 8CH X 11H - ­01H Hi-Z X 11H X 8CH

Note:

1. Operation: SIN = Serial In, S

= Serial Out, Bus Cycle 1 = Op Code

OUT

2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous

3. One bus cycle is eight clock periods.

4. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH
Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH

5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.

6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on

- -

CE .

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ESMT

D

D

F25L02PA (2F)

Operation Temperature Condition -40°C~85°C

7. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .

8. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 30H as memory type; third byte 12H as
memory capacity.

9. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
instructions effective. WREN can enable WRSR, user just need to execute it. A successful WRSR can reset WREN.

10. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.

11. Dual commands use bidirectional IO pins. D

12. Dual output data:

IO0= (D6, D4, D2, D0), (D6, D4, D2, D0)
IO1= (D7, D5, D3, D1), (D7, D5, D3, D1)

OUT0

13. Max Load capacitance is 15pF.

OUT1

and cont. are serial data out; others are serial data in.

OUT

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ESMT

F25L02PA (2F)

Read (33MHz)

The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a

low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is

reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 2Mbit density, once

Operation Temperature Condition -40°C~85°C

the data from address location 03FFFFH had been read, the next
output will be from address location 000000H.

The Read instruction is initiated by executing an 8-bit command,

03H, followed by address bits [A
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.

]. CE must remain active

23 -A0

Figure 2: Read Sequence

Fast Read (50 MHz ~ 100 MHz)

The Fast Read instruction supporting up to 100 MHz is initiated
by executing an 8-bit command, 0BH, followed by address bits

[A

] and a dummy byte. CE must remain active low for the

23 -A0

duration of the Fast Read cycle. See Figure 3 for the Fast Read
sequence.

Following a dummy byte (8 clocks input dummy cycle), the Fast
Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through

Figure 3: Fast Read Sequence

CE

0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48

0B ADD. ADD. ADD.

MSB

HIGH IMPENANCE

MSB

SCK

SO

MODE3

MODE0

SI

all addresses until terminated by a low to high transition on CE .
The internal address pointer will automatically increment until the

highest memory address is reached. Once the highest memory
address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space,
i.e. for 2Mbit density, once the data from address location
03FFFFH has been read, the next output will be from address
location 000000H.

55 56 6 3 64 80

X

N+2

D

OUT

MSB

N

D

OUT

N+1

D

OUT

N+3

D

OU T

71 72

N+4

D

OUT

Note : X = Dummy Byte : 8 Clocks Input Dummy (V

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IL

or VIH)

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